BD8108FM [ROHM]
White LED driver IC (under development) HSOP-M28 package; 白光LED驱动器IC （正在开发） HSOP- M28包
| 型号： | BD8108FM |
| 厂家： | 
ROHM |
| 描述： | White LED driver IC (under development) HSOP-M28 package |
| 文件： | 总16页 (文件大小：814K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL NOTE
For LCD panel backlight
White LED driver IC（under development）
rev. 0.14
BD8108FM
● Outline
BD8108FM is a white LED driver of high-withstand-voltage (36V).
Step-up DC/DC converter and constant current output 4ch are built-in in 1chip.
The brightness can be controlled by either PWM or VDAC.
● Features
1) Input voltage range 4.5～30V
2) Built-in Step-up DC/DC controller
3) Built-in current driver 4ch (150mA max.) for LED drive
4) Compatible with PWM light-modulating 0.38～99.5%
5) Built-in protective functions (UVLO, OVP, TSD, OCP)
6) Built-in abnormal-status-detecting function (open/short)
7) HSOP-M28 package
● Application
Car navigation backlight and small & medium-sized LCD panel etc.
● Absolute maximum ratings (Ta=25℃)
Item
Symbol
Rating
Unit
V
Power supply voltage (Pin : 1)
Load switch output voltage (Pin : 2)
LED output voltage(Pin : 12,14,15,17)
FAIL output voltage (Pin : 3,20)
Input voltage (Pin : 5,6,10,11,24)
VDAC input voltage (Pin : 8)
Allowable loss
V
CC
LOADSW
LED
OL
IN
DAC
36
V
36
V
V
36
V
V
7
V
V
-0.3～7 < VCC
-0.3～7 < VCC
V
V
V
1
※
Pd
Tjmax
Topr
Tstg
2.20
150
W
℃
℃
℃
mA
Junction temperature
Operating temperature range
Storage temperature range
LED maximum output current (Pin :
12,14,15,17)
-40～+95
-55～+150
※2 ※3
I
LED
150
※1 It is mounted on a glass epoxy board of 70mm×70mm×1.6mm. And the allowable loss is reduced at a rate of 17.6mw/℃
at the time of over 25℃.
※2 Dispersion between columns of LED maximum output current and VF is correlated. Please refer to data on a separate
sheet.
※3 Amount of the current per 1ch.
● Operating condition (Ta=25℃)
Item
Symbol
Target value
4.5～30
Unit
V
Power supply voltage (Pin : 1)
Oscillating frequency range
External synchronization frequency
range ※4 ※5(Pin : 6)
V
CC
OSC
SYNC
F
50～550
kHz
kHz
F
fosc～550
External synchronization pulse duty
range (Pin : 6)
F
SDUTY
40～60
%
※4 Please connect SYNC to GND when external synchronization frequency is not used.
※5 Do not do such things as switching over to internal oscillating frequency while external synchronization frequency is
used.
2007.Jan.
ROHM Limited Corporation
● Electric characteristic (Unless otherwise specified, VCC=12V Ta=25℃)
Target value
Symbol
Unit
Condition
Minimum
2.5
-
standard
Maximum
EN=2V, SYNC=VREG, RT=OPEN
PWM=OPEN, ISET=OPEN, CIN=1µF
EN=Low
Circuit current
ICC
6
0
10
mA
µA
Standby current
IST
2
[VREG Part (VREG)]
Reference voltage
[SW Part (SWOUT,CS)]
V
REG
ONH
4.5
5
5.5
V
I
REG=-10mA, CREG=1µF
SWOUT
upper
ON
R
0.05
0.05
0.3
3
2
7
5
Ω
Ω
V
I
I
ON=-10mA
ON=10mA
resistance
SWOUT
lower
ON
R
ONL
resistance
Overcurrent
protection
V
DCS
0.4
0.5
V
CS=sweep up
operating voltage
[errorーamplifier (COMP,SS)]
LED control voltage
COMP sink current
COMP source current
SS charging current
SS maximum voltage
SS standby current
[Oscillator Part (RT,SWOUT)]
Oscillating frequency
[OVP Part (OVP)]
V
LED
SKCP
SCCP
SS
MXSS
0.7
40
0.8
100
-100
-10
2.5
0
0.9
200
-40
-6
V
I
µA
µA
µA
V
V
V
V
LED=2V, Vcomp=1V
LED=0V, Vcomp=1V
SS＝1.0V
I
-200
-14
2.0
-
I
V
3.0
2
EN＝High
EN＝Low
ISTSS
µA
F
OSC
250
300
350
KHz
RT=100kΩ
Overvoltage-detecting
reference voltage
V
DOVP
DOHS
1.86
0.35
2.0
2.14
0.55
V
V
V
V
OVP=Sweep up
OVP hysteresis width
[UVLO Part (VREG)]
Reduced-voltage
V
0.45
OVP=Sweep down
detecting
voltage
reference
V
DUVLO
2.5
50
2.8
100
0.15
3.1
200
0.3
V
mV
V
V
V
REG=Sweep down
REG=Sweep up
UVLO hysteresis width
VDUHS
[Load switch Part（open drain）(LOADSW)]
Load switch Low voltage 0.05
V
LDL
I
LOAD=10mA
[LED output Part (LED1-4,ISET,PWM,VDAC,OVP)]
LED
current
relative
△ILED1
△ILED2
-
-
3
5
-
-
%
%
I
I
LED=50mA
LED=50mA
dispersion width
LED current absolute
dispersion width
ISET voltage
V
ISET
1.92
0.38
0
2.0
-
2.08
99.5
20
V
%
※1, 2, 3
※2, 3
※2, 3
PWM light modulation
PWM frequency
Duty
F
PWM=150Hz, ILED=50mA
F
PWM
VDAC
DOP1
DOP2
DSHT
-
KHz
mA/V
V
Duty=50%，ILED=50mA
VDAC gain
G
V
V
V
20
25
0.15
1.7
4.5
30
V
V
V
V
DAC=0～2V, ILED=50mA
LED= Sweep down, VOVP＞VDOP2, VSS≧VMXSS
Open detecting voltage 1
Open detecting voltage 2
Short detecting voltage
0.05
1.56
4.0
0.3
1.84
5.0
V
OVP= Sweep up, VLED＞VDOP1, VSS
LED= Sweep up, , VSS≧VMXSS
VMXSS
V
[Logic input（EN,SYNC,PWM,LEDEN1,LEDEN2）]
Input High voltage
Input Low voltage
V
INH
3.0
GND
18
-
5.5
0.8
53
V
V
V
INL
IN
-
Input inflowing current
Input inflowing current
I
35
25
µA
µA
V
IN=5V (SYNC,PWM,LEDEN1,LEDEN2)
EN=5V (EN)
I
EN
13
38
V
[FAIL output（open drain）(FAIL1,FAIL2)]
FAIL Low voltage 0.05
VFLL
0.1
0.2
V
I
OL=1ｍA
※1 0%,100% input is possible
◎
There is no radiation-proof design in this product.
※2
※3
I
I
LED=VDAC÷RISET×3300
LED=VISET÷RISET×3300, VDAC＞VISET
2/16
● Reference data (unless otherwise specified, Ta=25℃)
5.5
5.3
5.1
4.9
4.7
4.5
6
5
4
3
2
1
0
400
360
320
280
240
200
VCC=12V
VCC=12V
VCC=12V
T.B.D.
T.B.D.
T.B.D.
-40
-15
10 35
Ta [℃]
60
85
-40
-15
10
35
Ta [℃]
60
85
0
40
80
VREG [mA]
120
160
I
Fig.1 VREG temperature characteristic
Fig.2 VREG current capacity
Fig.3 OSC temperature characteristic
50
120
50
100
80
45
T.B.D.
45
40
35
30
40
VCC=8V
T.B.D.
VCC=12V
VCC=10V
60
VCC=6V
35
30
40
T.B.D.
20
-40
-15
10
Ta [
35
]
℃
60
85
-40
-15
10
35
60
85
40
140
240
340
440
540
Ta [℃]
Total_Io [mA]
Fig.4 ILED’s dependence on VLED
Fig.5 ILED temperature characteristic
Fig.6 efficiency
0.50
0.45
0.40
0.35
0.30
8.0
6.0
4.0
2.0
0.0
0.90
0.85
0.80
0.75
0.70
Ta=25
℃
T.B.D.
T.B.D.
T.B.D.
-40
-15
10
35
Ta [℃]
60
85
0
6
12
18
Vcc [V]
24
30
36
-40
-15
10
35
60
85
Ta [
]
℃
Fig.8 overcurrent detecting voltage temperature
characteristic
Fig.9 VLED temperature characteristic
Fig.7 ICC-VCC
10
8
10
8
60
50
40
30
20
10
0
T.B.D.
T.B.D.
T.B.D.
6
6
4
2
0
4
d
2
0
0
0.5
1
1.5
2
0
1
2
3
4
5
0
1
2
3
4
5
VDAC [V]
V
PWM[V]
VEN [V]
Fig.10 EN threshold voltage
Fig.11 PWM threshold voltage
Fig.12 VDAC gain
3/16
● Block diagram
VREG
LOADSW
UVLO
4
2
25 OVP
1
VCC
EN
VREG
TSD
OVP
3
FAIL1
24
Driver
PWM Comp
SYNC
RT
6
－
＋
＋
Control
Logic
23 SWOUT
22 CS
OSC
26
－
＋
OCP
ERR Amp
－
－
－
－
＋
28
27
COMP
7
GND
12 LED1
Soft
SS
Start
14 LED2
15 LED3
17 LED4
Current driver
PWM
5
ISET
21
8
9
PGND
VDAC
ISET
Open-Short
Detect
20 FAIL2
10
11
LEDEN1
LEDEN2
Fig.13
● Pin layout drawing
● Terminal Number ・ Terminal name
BD8108FM（HSOP-M28）
PIN
Name of
terminal
VCC
function
NO.
1
2
3
4
5
Input power supply term inal
FET connection for load switch
Output signal at abnormal time
Internal constant voltage output
PW M light m odulating input term inal
External synchronization signal input
term inal
1
28
27
26
25
24
23
22
V
CC
COMP
SS
LOADSW
FAIL1
2
3
4
5
6
7
LOADSW
FAIL1
VREG
RT
PW M
VREG
PWM
OVP
EN
6
7
8
SYNC
GND
GND of sm all signal Part
DC variable light-modulating input
term inal
SYNC
GND
SWOUT
CS
VDAC
LED resistor for setting the output
current
9
ISET
10
11
12
13
14
15
16
17
18
19
20
21
22
LEDEN1
LED output terminal enable term inal 1
LED output terminal enable term inal 2
LED output terminal
LEDEN2
LED1
-
LED2
LED3
-
N.C.
LED output terminal
LED output terminal
8
21
20
19
18
17
16
15
N.C
VDAC
ISET
PGND
FAIL2
N.C.
LED4
-
LED output terminal
9
N.C.
10
11
12
13
14
LEDEN1
LEDEN2
LED1
-
N.C.
FAIL2
PGND
CS
LED open/short detecting output signal
LED output GND terminal
DC/DC term inal for output current
detecting
N.C.
LED4
N.C.
N.C.
23
24
25
SW OUT
EN
DC/DC switching output term inal
Enable term inal
LED2
LED3
OVP
Overvoltage detecting term inal
Fig.14
4/16
●5V constant voltage（VREG）
5V (Typ.) is generated from VCC input voltage when EN=H. This voltage is used as a power supply of the internal circuit, and
also when the device pins need to be fixed to H voltage.
UVLO is built-in in VREG, and the circuit begins to operate when the voltage is more than 2.9V (Typ.) and stops when the
voltage is less than 2.8V (Typ.).
Please connect Creg=10uF (Typ.) to VREG terminal for phase compensation. The circuit’s operation becomes remarkably
unstable when Creg is not connected.
● Self-diagnosis function
The operating condition of the built-in protection circuit is transmitted to FAIL1 and FAIL2 output pins (open drain).
When UVLO, OVP, OCP or TSD is operated, FAIL1 output becomes L SWOUT is fixed to L, and the step-up conversion is
stopped. For OCP, SWOUT is fixed to L for only 1 cycle of FOSC because of the pulse-to-pulse mode operation. For UVLO,
OVP, TSD operations, LED output pins become open (Hi-Z）. When FAIL1 becomes L, LOADSW is turned off as they are
inverted to each other.
OPEN
FAIL2
SHORT
FAIL1
OVP
OCP
TSD
S Q
MASK
R
EN=OFF
(UVLO)
UVLO
FAIL2 output becomes L when open or short is detected. The open/short detection is a latch mode, and the latch is released by
ON/OFF (UVLO) of EN. The device judges as open when LED output is lower than 0.15V (Typ.) as well as when the voltage of
OVP terminal reaches 1.7V (Typ.). The short is detected when LED output becomes more than 4.5V (Typ.). Therefore, there is
a possible scenario that short detection cannot be carried out if the difference between LED terminal voltage at the time of
being normal and LED terminal voltage at the time of being abnormal is less than 3.7V (4.5V-0.8V) (Typ.). As for short
detection hereon, if one LED in some column of LED output, for example, becomes short mode, and is in the status of nothing
but VF being low, then cathode voltage is in the status of nothing but VF being high. LED short detection and OCP are
separate protection circuits. Please take care because short detection is masked as soon as open/short is detected. However,
the open detection operates. An additional capacitance added to LED output slows down the operation and the short may be
detected.
For the two FAIL output pins, add pull-up resistors for each as they are open drain.
LED1
0.8V
GND
0.15V
OtherLED output
4.5V
Short detection is not turned off
because it is masked.
0.8V
Step-up voltage VOUT
VFxN+0.8V
2.0V
1.7V
OVP
FAIL2
LED1
Open
LED1
Off
● Constant-current driver
Please turn off the output with LEDEN if there is constant-current driver output that is not used. The truth-table is shown below.
If constant-current driver output that is not used is not treated with LEDEN but is made open, then the open detection will
operate. Also, please do not short the driver output to GND as the inputs of the error amplifier cannot be deactivated with
LEDEN. Instead keep the driver output to open or short it to VREG.
LED EN
LED
〈1〉 〈2〉
1
2
3
4
L
H
L
L
L
ON
ON
ON
ON
ON
ON
ON
OFF
ON
ON
ON
OFF
OFF
OFF
H
H
OFF
OFF
H
5/16
・Setting method of output current
ILED=min[VDAC , VISET(=2.0V)] / RSET x 3300 [mA]
min[VDAC , 2.0V] means the selection of smaller value is between VDAC or VISET(=2.0V).
3300 (Typ.) is a constant number determined by the circuit inside.
When the output current needs to be controlled with VDAC, please input in the range of 0.1～2.0V. In the case of more than
2.0V, the value of VISET is selected in such a way that it is given by the above-mentioned calculating formula. Please connect
VDAC with VREG if VDAC is not to be used. The open state of VDAC will cause malfunction. Please do not change the LED
EN status during the PWM operation. The following diagram shows the relation between RISET and ISET.
ILED vsRSET
160
140
120
100
80
ILED actual measurement [mA]
------2.0/RSETx3300
60
40
20
0
0
50 100 150 200 250 300 350 400 450 500
RSET[kΩ]
For the intensity control with PWM, the ON/OFF of current driver is controlled by PWM terminal. The duty ratio of PWM
terminal becomes the duty ratio of ILED. Please fix the PWM terminal to H if PWM intensity control is not to be used (100%). It
becomes brightest at the time of 100%. It is recommended to use a low-pass filter (cut off frequency: 30 kHz) for the PWM pin.
PWM
ILED
PWM
ILED
PWM
ILED(50mA/div)
PWM=150Hz Duty=0.38%
PWM=150Hz Duty=50%
PWM=20kHz Duty=50%
● Step-up DC/DC controller
・Number of LEDs in series connection
Output voltage of the step-up converter is controlled such that the LED output pin becomes 0.8V (Typ.). Step-up operation is
performed only when LED output is operating. When more than one LED outputs are operating, the LED output in the column
in which the LED’s VF is the highest is controlled in such a way that it becomes 0.8V (Typ.).
The voltage of other LED outputs are increased with the portion of variation becomes high voltage. Please use the following
equation to calculate allowable VF variation.
VF variation allowable voltage 3.7V（Typ.）
= short detecting voltage 4.5V（Typ.）－LED control voltage 0.8V（Typ.）
In addition, pay attention to the number of LED’s connection in series because it has the following limits. In case of the open
detection, 85% of OVP setting voltage becomes trigger, so the maximum value of step-up voltage under normal operation
becomes 30.6V=36V x 0.85 and 30.6V / VF > maximum N number.
・ Overvoltage protection circuit OVP
For the OVP terminal, apply the voltage divider of the step-up converter output. The setting value of OVP is determined by
LED’s total numbers in series connection and VF variation. Please also take OVPx0.85, which is the open detection trigger,
into consideration when determining OVP setting voltage. Once the OVP operates, the OVP is released when step-up voltage
drops to 77.5% of OVP setting voltage.
Suppose ROVP1（step-up voltage side）,ROVP2（GND side）and step-up voltage VOUT,
Then VOUT>=(ROVP1+ROVP2)/ROVP2 x 2.0V. The OVP operates at the time of ROVP1=330kΩ, ROVP2=22kΩ and VOUT=
over 32V.
6/16
・Oscillating frequency FOS of step-up DC/DC converter
Triangular wave oscillating frequency can be set by connecting a resistor to RT (26Pin). RT determines the charging & discharging currents
for internal condenser, and the frequency changes. Please refer to the following theoretical formula when setting the RT’s resistance. The
range of 62.6kΩ～523kΩ is recommended. The setting that deviates from the frequency range in the following diagram may cause the
switching to stop and has no guarantee of proper operation, so please be careful.
30×106[V/A/S] is a constant number（±16.6%）determined by the circuit inside, and α is the correction factor.
（RT :α = 50kΩ: 0.98 , 60 kΩ: 0.985, 70 kΩ: 0.99, 80 kΩ: 0.994, 90 kΩ: 0.996, 100kΩ: 1.0,
150kΩ: 1.01, 200kΩ: 1.02,300kΩ: 1.03 , 400kΩ: 1.04 , 500kΩ: 1.045）
30 × 106
RT [Ω]
fosc =
x α [kHz]
550K
450K
350K
250K
150K
50K
0
100
200
300
400
500
600
700
800
RT [kΩ]
Fig.15 RT versus switching frequency
・ External synchronization oscillating frequency FSYNC
Please do not switch over to the internal oscillation etc. halfway when clock is being inputted to SYNC terminal for the purpose
of external synchronization for step-up DC/DC converter. From having switched the SYNC terminal from H to L till the internal
oscillating circuit begins to operate, there is a delay time of about 30usec（Typ.）. For the clock inputted to SYNC terminal, only
the rising edge is effective. Moreover, if external input frequency is later than internal oscillating frequency, the internal
oscillating circuit begins to operate after the above-mentioned delay time, so please do not input something like that (the
above-mentioned input).
・Overcurrent protection circuit OCP
Please put (insert) the detecting resistor RCS between GND and the source of n-MOSFET for step-up DC/DC converter. In
addition, please insert the low pass filter (LPF) with 1～2MHz cutoff frequency between the CS terminal and the detecting
resistor in order to reduce the switching noise. If the time constant is too large, then the rising edge of CS terminal voltage is
delayed, and it gets late that OCP operates. (RLPF=100Ω and CLPF=1000pF etc. are effective at the time of FOSC=300kHz.)
The detecting current is as follows.
IOCP=VOLIMIT0.4V / RCS [A]
OCP is of pulse by pulse mode, and SWOUT is fixed to L for only 1 cycle determined by FOSC. In addition, there is a large
current line between RCS－GND, so please pay special attention and make an independent wiring to GND while board
designing.
VOUT
(AC)
SWOUT
CS
IL
(500mA)
R
CS
SW
LPF
Independent wiring to GND
Fig.16 Ripple current & voltage
・Soft start SS
For this IC, the SS terminal is not used, so please use the IC with the SS terminal open.
Moreover, the open/short detecting function is masked until SS terminal voltage reaches the VSS clamp voltage 2.5V（Typ.）.
7/16
●Selection of External Parts
1. Selection of Coil (L)
ILMAX
The coil’s value greatly affects the input ripple current. As shown in formula (1), the
ripple current decreases as the coil becomes larger or the switching frequency
increases.
ICC
△I
L
（VOUT-Vcc）×Vcc
ΔIL
=
[A]・・・（1）
L×VOUT×f
V
CC
When efficiency is represented as in (2), the input peak current is as shown in (3).
V
OUT×IOUT
η =
・・・(2)
L
I
L
Vcc×Icc
V
OUT
V
OUT×IOUT
ΔI
2
L
ΔIL
2
C
O
ILMAX = Icc +
=
+
[A]・・・（3）
Vcc×η
Fig.17 Output ripple current
※If current which exceeds the coil’s rated current value is run through the coil, the coil causes magnetic saturation and efficiency decreases.
Please keep a suitable margin so that the peak current does not exceed the coil’s rated current value, when selecting the current.
※Please select coil with low resistance components (DCR and ACR) in order to minimize loss and improve efficiency.
2. Setup of Output Condenser (Co)
The output condenser should be decided on after careful consideration of the stable
CC
V
zone of the output voltage and the necessary equivalent series resistance to smooth
the ripple voltage.
L
I
L
OUT
V
The output ripple voltage is decided as shown in formula (4).
ESR
I
OUT
I
1
f
△VOUT = ILMAX × RESR
+
×
×
[V] ・・・（4）
O
C
η
CO
(ΔIL: output ripple current, ESR: equivalent series resistance of Co, η: efficiency)
※When selecting the condenser rating, keep a suitable margin for the output voltage.
Fig.18 Output condenser
3. Selection of Input Condenser (Cin)
It is necessary to select a low-ESR input condenser that can adequately deal with large
ripple currents in order to prevent excess voltage.
CC
V
Cin
The ripple current IRMS is derived from formula (5).
L
I
L
OUT
V
(VOUT - VCC) ×
OUT
VOUT
I
RMS = IOUT
×
[A]・・・（5）
V
O
C
Also, because it depends greatly on the characteristics of the power supply used for
input, the wiring pattern of the substrate and the MOSFET gate-drain capacity, it is
highly recommended that usage temperature, load range and MOSFET conditions are
adequately confirmed.
Fig.19 Input condenser
8/16
4. About MOSFET for Load Switch and the Corresponding Soft Start
With regular booster applications, because no switch exists on the route from VCC to VO, there is the threat of output
short-circuit or destruction of the commutation diode. To avoid this, please insert a PMOSFET load switch between VCC
and the coil. PMOSFET that can withstand higher pressure than VCC between both the gate sources and drain sources
should be selected.
Also, if a load switch soft start is desired, please insert capacity between the gate source. Refer to figure 21 when deciding
on the soft start time. However, the soft start time changes depending on the gate capacity of PMOSFET.
PG PIN CAPACITOR vs. SOFT START TIME
L
DELAY [sec]
RISETIME [sec]
Vo
1.00E-01
1.00E-02
1.00E-03
1.00E-04
1.00E-05
SBDi
C
T.B.D.
FET for load switch
FET for switching
1.00E-10
1.00E-09
1.00E-08
CPG [F]
1.00E-07
1.00E-06
Fig.20 Load Switch Circuit Diagram
5. Selection of Switching MOSFET
Fig.21 PG Capacity vs. Soft Start Time
Although there is no problem as long as the absolute maximum rating is the rated current of L and at least C’s pressure
capacity and commutation diode’s VF, to actualize high-speed switching, one with small gate capacity (injected charge amount)
should be selected.
※Excess current protection setup value or higher recommended.
※High efficiency can be achieved if one with low ON resistance is selected.
6. Selection of Commutation Diode
Please select a Schottky barrier diode with greater current capability than L’s rated current and reverse-pressure capacity
greater than C’s pressure capacity, especially with low forward voltage VF.
9/16
●Phase Compensation Setup Rules
・Stability Conditions of Applications
The stability conditions related to negative feedback are as follows:
・When the gain is 1 (0dB) and the phase-lag is under 150 º (therefore with a phase margin of over 30º)
Also, a DC/DC converter application samples the switching frequency, so the GBW of the entire series is set to 1/10 below the switching
frequency. To summarize, the characteristics targeted by the application are as below:
・When the gain is 1 (0dB) and the phase-lag is under 150 º (therefore with a phase margin of over 30 º)
・GBW (frequency at gain 0dB) at that time is 1/10 below the switching frequency
Therefore, to improve response with GBW limits, the switching frequency must be higher.
A trick to secure stability with phase compensation is to cancel the second phase-lag (-180 º ) caused by the LC resonance with the
second phase-lead (put in two phase-leads).
Phase-lead is by the ESR component of the output condenser and the CR of the error amp output Comp terminal.
With a DC/DC converter application, because there is always an LC resonance circuit at the output, the phase-lag at that area is -180º.
When the output condenser is one with a large ESR (several Ω), such as a aluminum electrolysis condenser, there is a phase-lead of
+90º, and the phase-lag is -90º. When an output condenser with low ESR such as a ceramic condenser is used, an R for the ESR
component should be inserted.
LC Resonance
Vcc
With ESR
Vcc
1
fr =
[Hz]
Resonance point at
2π√LC
O
Resonance point phase-lag -180º at
1
fr =
[Hz]
2π√LC
O
O
V
Phase-lead at
O
V
1
fESR
=
[Hz]
O
2πRESR
C
ESR
O
R
O
C
C
Phase-lag -90°
Fig.22
Fig.23
Because of the changes in phase characteristics caused by ESR, one lead-phase should be inserted.
V
O
LED
FB
A
COMP
Rpc
Cpc
Fig.24
1
Phase-lead fz =
[Hz]
2πCpcRpc
To setup the frequency to insert the phase-lead, for the aim of canceling the LC resonance, ideally it should be set in the area
of the LC resonance frequency.
Because this setup was very basically designed and strict calculations have not been made,
adjustments with the actual equipment may be required. Also, these characteristics change
depending on factors such as different substrate layouts and load conditions, therefore when
designing for mass production, adequate confirmations with actual equipment must be made.
10/16
●Sequence
VCC>VREG
4.5V
VCC
EN
OK to input EN at VCC= 4.5V or greater
2.8V
2.9V
2.9V
VREG
Internal Signal
UVLO
TPWMON > TINON
TINON
VDAC
SYNC
TPWMOFF > TINOFF
TPWMON > 500[V/A
・s] x CREG [sec]
TPWMON
PWM
2.0V
1.6V
OVP
0.4V
OCP(CS)
175
150
℃
℃
Internal Signal
TSD
VREG off
when TSD on
Load SW
FAIL1
(
)
External Pull-Up
※Fix LEDEN1 and 2 before input.
Fig.25
11/16
●Power Dissipation Calculation
Pd(N) = ICC*VCC + Ciss*Vsw*fsw*Vsw + Rload*(Iload)^2 + [VLED*N+⊿Vf*(N-1)]*ILED
ICC: Maximum circuit current
VCC: Supply power voltage
Ciss: External FET capacity
Vsw: SW gate voltage
Fsw: SE frequency
Rload: LOAD SW ON resistance
Iload: LOAD SW maximum input current
VLED: LED control voltage
N: LED parallel numeral
△Vf: LED Vf fluctuation
ILED: LED output current
＜Sample Calculation＞
Pd(4) = 10mA × 30V + 500pF × 5V × 300kHz × 5V + 15Ω × (10mA)2 + [0.8V × 4 + △Vf × 3] × 100mA
If △Vf = 3.0V,
Pd(4) = 324mW + 1220mW = 1544mW
4
PowerDissipation
(1) θja=56.8℃/W (Substrate copper foil density 3%)
(3) 3.50W
2500
2000
1500
1000
500
(2) θja=39.1℃/W (Substrate copper foil density34%)
(3) θja=35.7℃/W (Substrate copper foil density60%)
3
2
ILED=5
0mA
(2) 3.20W
(1) 2.20W
ILED=1
00mA
ILED=1
50mA
1
0
0
0
0.5
1
1.5
2
2.5
3
3.5
LED Fluctuation
⊿
25
50
75
95 100
125
150
Ambient Temperature Ta[℃]
Fig.26
Note 1: The value of power dissipation is when mounted on 70mm X 70mm X 1.6mm glass epoxy substrate (1-layer
platform/copper thickness 18μm)
Note 2: The value changes with the copper foil density of the platform. However, this value represents observed value,
not guaranteed value.
Pd=2200mW (968mW): Substrate copper foil density 3%
Pd=3200mW (1408mW): Substrate copper foil density34%
Pd=3500mW (1540mW): Substrate copper foil density 60% Value within brackets represent power dissipation when Ta=95℃
●Efficiency of Switching Power Supply
Efficiency η is represented in the following formula:
V
OUT × IOUT
P
OUT
P
OUT
η=
× 100[%] =
× 100[%] =
× 100[%]
Vin × Iin
Pin
PD
(IC) + P
Dα
The main causes for power dissipation of the switching regulator P
lessening these causes.
Dα are as listed below, and efficiency can be improved by
＜Main Causes of Dissipation＞
1) Dissipation from ON resistance of coil and FET: PD(I2R)
2) Gate charge-discharge dissipation: PD(Gate)
3) Switch dissipation: PD(SW)
4) Condenser’s ESR dissipation: PD(ESR)
5) IC’s operational current dissipation: PD(IC)
1) PD(I2R) = IOUT2×(RCOIL×RON
)
(RCOIL[Ω]: coil resistance, RON[Ω]: ON resistance of FET, IOUT[A]: Output current)
2) PD(Gate) = CSW×fSW×VSW (CSW[F]: Gate capacity of FET, fSW[Hz]: Switching frequency, VSW[V]: Gate drive voltage of
FET)
3) PD(SW) =
V
in2×CRSS×IOUT×fSW
(CRSS[F]: Reciprocal transmission capacity of FET, IDrive[A]: Peak
IDrive
4) PD(ESR) = IRMS2×ESR (IRMS[A]: Ripple current of condenser, ESR[Ω]: Equivalent Series Resistance)
5) PD(IC) = Vin×ICC (ICC[A] : Circuit Current)
12/16
○The decoupling condensers CVCC and CREG should be placed as close as possible to the IC pin.
○There is a possibility that a large current is sent to CSGND and PGND, so each should be independently wired, and at the
same time impedance should be lowered.
○Take care that there is no noise riding on 8pin VDAC, 9pin ISET, 26pin RT and 28pin Comp.
○5pin PWM, 6pin SYNC and 12-17pin LED1-4 all switch, therefore be careful that the periphery pattern is unaffected.
○The areas with thick lines should be laid out as short as possible with wide patterns.
●PCB Board External Parts List
Setting place
RLD1
RLD2
RFL1
RFL2
RPC
Value
5.1kΩ
5.1kΩ
5.1kΩ
5.1kΩ
820Ω
100kΩ
330kΩ
22kΩ
0.1Ω
100kΩ
2.2uF
-
Product Name
MCR03Series5101
MCR03Series5101
MCR03Series5101
MCR03Series5101
MCR03Series8200
MCR03Series1003
MCR03Series3303
MCR03Series2202
MCR10SeriesR10
MCR03Series1003
T.B.D.
Manufacturer
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
ROHM
murata
-
RT
ROVP1
ROVP2
RCS
RSET
CPC
CSS
-
CVCC
CREG
Q1
10uF
10uF
-
GRM21BB31C106KE15
GRM21BB31C106KE15
RSS090P03FU6TB
SP8K22FU6TB
CDRH8D38NP-470NC
RB160L-60TE25
25YK220M0611
MCR03Series1000
T.B.D.
murata
murata
ROHM
ROHM
Sumida
ROHM
Rubycon
ROHM
murata
murata
Q2
-
L1
47uH
-
D1
CVOUT
RLPF
CLPF
CLD2
220uF
100Ω
1000pF
1uF
T.B.D.
※The above values are fixed numbers for confirmed operation when VCC=12V, LED 5-straight 4-parallel and ILED=50mA.
Therefore, because the optimal value varies depending on factors such as usage conditions, the fixed numbers should
be decided on after careful assessment.
13/16
●In/Output Equivalent Circuits (Terminal names surrounded by parentheses)
5. PWM, 6. SYNC,
2. LOADSW, 3. FAIL1, 20. FAIL2
4. VREG
10. LEDEN1, 11. LEDEN2
VREG
CL10V
VCC
10K
150k
VREG
746k
255k
150K
12. LED1, 14. LED2,
15. LED3, 17. LED4
8. VDAC
CL10V
9. ISET
CL10V
10K
1K
LED1
～
4
500
500
VDAC
ISET
5K
22. CS
CL10V
23. SWOUT
24. EN
CL10V
VREG
CL10V
SWOUT
EN
CS
172k
135k
10k
100
5K
5P
100k
25. OVP
CL10V
26. RT
27. SS
CL10V
CL10V
2k
50
SS
OVP
RT
1k
167
5K
100k
28. COMP
13, 16, 18, 19 N.C.
CL10V
VCC
VREG
CL10V
CL10V
2K
2K
N.C.
COMP
10V
N.C. is open.
※The value are all Typ. value.
14/16
z
Operation Notes
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage.
Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety
measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded
is anticipated.
2) GND potential
Ensure a minimum GND pin potential in all operating conditions.
3) Setting of heat
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4) Pin short and mistake fitting
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC.
Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result
in damage to the IC.
5) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction.
6) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge
capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when
transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the
inspection process.
7) Ground wiring patterns
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground
point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause
variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components.
8) Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are
formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements.
For example, when the resistors and transistors are connected to the pins as shown in Fig. 41, a parasitic diode or a transistor operates by
inverting the pin voltage and GND voltage.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's
architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these
reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements such as by the
application of voltages lower than the GND (P substrate) voltage to input and output pins.
Resistor
Transistor (NPN)
(Pin B)
B
E
(Pin A)
C
E
C
(Pin B)
B
GND
GND
N
P
Example of a Simple
P
P+
P+
P+
Parasitic
elements
P+
N
N
N
P
N
Monolithic IC Architecture
N
N
(Pin A)
P substrate
GND
Parasitic elements
GND
Parasitic
elements
Parasitic elements
GND
9) Overcurrent protection circuits
An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC damage that may result in the
event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected accidents. However, the IC
should not be used in applications characterized by the continuous operation or transitioning of the protection circuits. At the time of thermal
designing, keep in mind that the current capacity has negative characteristics to temperatures.
10) Thermal shutdown circuit (TSD)
This IC incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the specified power
dissipation range. However, in the event that the IC continues to be operated in excess of its power dissipation limits, the attendant rise in the
chip's junction temperature Tj will trigger the TSD circuit to turn off all output power elements. The circuit automatically resets once the
junction temperature Tj drops.
Operation of the TSD circuit presumes that the IC's absolute maximum ratings have been exceeded. Application designs should never make
use of the TSD circuit.
11) Testing on application boards
At the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure to discharge
electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before connecting it to or removing it from
a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure, and use similar caution when
transporting or storing the IC.
15/16
zSelecting a Model Name When Ordering
The contents described herein are correct as of October, 2005
The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD.
Any part of this application note must not be duplicated or copied without our permission.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding
upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any
warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such
infringement, or arising from or connected with or related to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other
proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer.
The products described herein utilize silicon as the main material.
The products described herein are not designed to be X ray proof.
Published by
Application Engineering Group
16/16
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