BD34705KS2_技术文档

Datasheet

Sound Processors for AV Receiver Systems

7.1ch Sound Processor

with Built-in Micro-step Volume

BD34705KS2

General description

Key Specifications

The BD34705KS2 is an 8ch independent volume system.

The system is designed to allow 7.1ch surround system

application. It is improvement that sound quality more

than the conventional products. Micro-step volume can

reduce the switching pop noise during volume attenuation,

so a high quality audio system could be achieved.

8ch triple input selectors for zone 3 and multi channel

input enable the connection with a number of sources.

 Total harmonic distortion:

 Maximum output voltage:

 Output noise voltage:

0.0004%(Typ.)

4.2Vrms(Typ.)

1.2μVrms(Typ.)

1.0μVrms(Typ.)

-105dB(Typ.)

 Residual output noise voltage:

 Cross-talk between channels:

 Cross-talk between selectors:

-105dB(Typ.)

Package

W(Typ.) x D(Typ.) x H(Max.)

14.00mm x 14.00mm x 1.50mm

SQFP-T64

Features

 8ch input selectors

(It is extendable to up to 14 by other functions and

exclusion)

 Micro-step volume can reduce the switching pop

noise during volume attenuation.

 Zone 3 is supported.

 Built-in 2ch Volume for ZONE output

 2-wire serial bus control, corresponding to 3.3/5V.

Applications

SQFP-T64

 Suitable for the AV receiver, home theater system,

etc.

Typical Application Circuit

Figure 1. Application Circuit

○Product structure：Silicon monolithic integrated circuit ○This product is not designed protection against radioactive rays

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Pin Configuration

Figure 2. Pin Configuration

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Description of terminal

Terminal

Symbol

Number

Terminal

Number

Function

Symbol

Function

1

2

33

34

DA

CL

Data and latch input terminal

Clock input terminal

GND

INL6

Analog ground terminal

Lch input terminal 6

Positive power supply

terminal

3

4

5

6

7

35

36

37

38

39

VCC

DGND

VEE1

NC

INR6

INL5

INR5

INL4

INR4

Rch input terminal 6

Lch input terminal 5

Rch input terminal 5

Lch input terminal 4

Rch input terminal 4

Digital ground terminal

Negative power supply

terminal 1

No connect

Negative power supply

terminal 2

VEE2

8

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

OUTFR

OUTFL

OUTSW

OUTC

FRch Output terminal

FLch Output terminal

SWch Output terminal

Cch Output terminal

SRch Output terminal

SLch Output terminal

INL3

INR3

INL2

Lch input terminal 3

Rch input terminal 3

Lch input terminal 2

Rch input terminal 2

Lch input terminal 1

Rch input terminal 1

Analog ground terminal

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

INR2

INL1

OUTSR

OUTSL

INR1

GND

SBLIN

SBRLIN

SLIN

SRIN

CIN

OUTSBR SBRch Output terminal

OUTSBL SBLch Output terminal

OUTHPR HPRch Output terminal

OUTHPL HPLch Output terminal

SBLch DSP input terminal

SBRch DSP input terminal

SLch DSP input terminal

SRch DSP input terminal

Cch DSP input terminal

SWch DSP input terminal

FLch DSP input terminal

FRch DSP input terminal

Analog ground terminal

Lch ADC Output terminal

Rch ADC Output terminal

Analog ground terminal

Chip select terminal

GND

SUBL

SUBR

RECL

RECR

GND

INL8

Analog ground terminal

Lch SUB Output terminal

Rch SUB Output terminal

Lch REC Output terminal

Rch REC Output terminal

Analog ground terminal

Lch input terminal 8

SWIN

FLIN

FRIN

GND

ADCL

ADCR

GND

CHIP

INR8

INL7

Rch input terminal 8

Lch input terminal 7

INR7

Rch input terminal 7

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Block Diagram

46

41

40

44

43

42

45

39

38

37

36

35

34

33

Main

Sub1

Sub2

47

32

48

49

31

30

50

51

52

29

28

Mode

selector

Mode

selector

Mode

selector

Mode

selector

Rec

7.1chOUT +32dB～

53

54

-95dB,-INF/0.5dB step

27

26

SBR

Volume

FR

Volume

SR

FL

Volume

SW

Volume

C

SL

SBL

Volume

55

Rec Selector

Sub

ADC

56

57

25

24

58

59

Sub Selector

60

61

62

63

SUBOUT

+6dB～-16dB/1dB step

-16dB～-56dB/2dB step

MUTE

23

22

21

20

HP-OUT

FRONT/MUTE

64

Logic

18

15

16

17

19

14

10

11

12

13

1

2

3

4

5

6

7

8

9

Figure 3. Block Diagram

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Absolute Maximum Ratings

Item

Symbol

VCC

VEE

Pd

Rating

Unit

V

(Note1)

+7.75

-7.75

1.50

Positive power supply

Negative power supply

Power dissipation

(Note1)

(Note2)

V

W

V

Vin

VEE-0.2 to VCC+0.2

Input voltage

(Note3)

Topr

Tstg

-40 to +85

°C

Operating temperature

Storage temperature

-55 to +150

(Note1)

(Note2)

(Note3)

The maximum voltage that can be applied based on GND.

Derating at 12.0mW/°C for operating above Ta≥25°C (mounted on 70×70×1.6mm ROHM standard board)

If it is within the operation voltage range, circuit functions operation is guaranteed within operation temp.

Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between

pins or an open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as

adding a fuse, in case the IC is operated over the absolute maximum ratings.

Operating Condition

Item

Symbol

Rating

Unit

(Note4,5)

VCC

VEE

+6.5 to +7.5

-6.5 to -7.5

V

Positive power supply

Negative power supply

(Note4)

(Note5)

Applying voltage based on GND.

Within the operating temperature range, basic circuit function and operation are guaranteed within this operation

voltage range. But please confirm the setting of the constants, temperature, etc. Please take note that

electrical characteristics other than defined values cannot be guaranteed, however original function will retain.

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Electrical characteristic

Unless otherwise specified, Ta=25°C, VCC=7V, VEE=-7V, f=1kHz, Vin=1Vrms, RL=10kΩ,

Stereo input selector(MAIN, SUB1, SUB2)=IN1, Mode selector(FL, FRch)=MAIN,

Mode selector(SW, C, SL, SRch)=MULTI, Mode selector(SBL, SBRch)=MULTI, SB OUTSEL=SB,

Input Att=0dB, Input gain=0dB, Volume=0dB.

Limit

Item

Symbol

Unit

Conditions

No signal

Min.

-

Typ.

32

Max.

45

Iqp

Iqn

mA

dB

%

Positive circuit current

Negative circuit current

Output voltage gain

Channel balance

No signal

-45

-1.5

-0.5

-

-32

-

Gv

0

1.5

0.5

0.02

8 to 15pin output

C Channel reference,

8 to 15pin output

CB

BW=400 to 30kHz

8 to 15pin output

THD=1%,

THD

0.0004

Total harmonic distortion

Vom

Vno

3.8

4.2

1.2

1

-

10

8

Vrms VOLUME=+10dB

8 to 15pin output

Maximum output voltage

Output noise voltage *

TOTAL

Rg=0Ω, BW=IHF-A

8 to 15pin output

-

µVrms

Volume=Mute,

µVrms Rg=0Ω, BW=IHF-A

8 to 15pin output

Residual output noise

voltage *

Vnor

Cross-talk between

channels *

Cross-talk between

selectors *

Rg=0Ω, BW=IHF-A

8, 9pin output

CT

CS

-

-105

-80

dB

Rg=0Ω, BW=IHF-A

8, 9pin output

dB

24 to 27, 29 to 32

Rin

ATTmax

THDR

Ron

32

47

-115

62

kΩ

dB

%

34 to 35, 47 to 54

pin input

Input impedance

VOLUME

-

-100

0.02

1080

Volume=Mute, BW=IHF-A

Maximum attenuation *

Total harmonic distortion

Output impedance

BW=400 to 30kHz,

RL=6.8kΩ

24 to 27pin output

REC

OUT

0.0005

HPOUT

520

800

Ω

16,17pin output

※VP-9690(Average detection value, effective value display) filter by Panasonic is used for * measurement.

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Typical Performance Curve(s) (Reference data)

50

40

30

20

10

0

34

32

30

28

26

24

22

20

18

16

14

12

10

8

-10

Operational

range

-20

6

4

2

0

-30

-40

-50

-2

0

1

2

3

4

5

6

7

8

10

100

1000

10000

100000

VCC(+)/VEE(-)[V]

Frequency[Hz]

Figure 4. Circuit Currents vs. Circuit Voltage

Figure 5. Volume Gain vs. Input Frequency

(32dB to 0 dB setting)

2

0

-2

-4

-6

-8

-30

-32

-34

-36

-38

-40

-42

-44

-46

-48

-50

-52

-54

-56

-58

-60

-62

-64

-66

-10

-12

-14

-16

-18

-20

-22

-24

-26

-28

-30

-32

-34

10

100

1000

10000

100000

10

100

1000

10000

100000

Frequency[Hz]

Figure 6. Volume Gain vs. Input Frequency

(0dB to -32 dB setting)

Figure 7. Volume Gain vs. Input Frequency

(-32dB to -64 dB setting)

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1.0000

0.1000

0.0100

0.0010

0.0001

-60

-62

-64

-66

-68

-70

-72

-74

-76

-78

-80

-82

-84

-86

-88

-90

-92

-94

-96

-98

10kHz

100Hz

1 kHz

10

100

1000

10000

100000

0.001

0.010

0.100

1.000

10.000

Frequency[Hz]

Input Voltage [Vrms]

Figure 8. Volume Gain vs. Input Frequency

(-64dB to -95 dB setting)

Figure 9. THD + N vs. Input Voltage

(Note) The measurement results of Figure 4 to Figure 8 used by 80kHz LPF.

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Specifications for Control Signal

(1) Timing of control signal

Data is read at the rising edge of clock.

Latch is read at the falling edge of clock. Data on the latest 16bit is taken inside the IC.

Ensure to set DA and CL to LOW after Latch.

1byte=16bit

90

％

90

％

90

％

90

％

CL

CLOCK

tsu

twc

(

)

10

％

10

％

10

％

thd

ts

th

tsd

thd

tsl

thl

DA

DATA

LATCH

90

％

90

％

90

％

90

％

90

％

twh

twl

twd

DATA

10

％

LATCH

10

％

10

％

Figure 10. The timing definition of the control signal

Limit

Typ.

Item

Symbol

Unit

Min.

1.0

0.5

Max.

Clock width

Data width

Latch width

Low hold width

twc

twd

twl

twh

tsd

thd

tsl

thl

ts

th

-

µsec

Data setup time (DATA→CLK)

Data hold time (CLK→DATA)

Latch setup time (CLK→LATCH)

Latch hold time

Latch Low setup time

Latch Low hold time

(2) Voltage of control signal (CL, DA, CHIP)

Limit

Typ.

Item

Conditions

Max.

(<VCC)

Unit

Min.

2.3

0

High input voltage

-

5.5

V

Vcc=+6.5 to +7.5V

Vee=-6.5 to -7.5V

Low input voltage

1.0

(3) Basic Structure of Control Data

←Input Direction

D15 D14 D13 D12 D11 D10

D9

Data

D8

D7

D6

D5

D4

D3

D2

D1

D0

Select Address

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(4) Table of Control Data

←Input Direction

Select

Address D15

No.

D14 D13 D12 D11 D10

D9

D8

D7

0

D6

D5

1

D4

0

D3

0

D2

D1

0

D0

0

REC

ON/OFF

SUB

ON/OFF

0

1

Input Selector (MAIN)

Input Selector (SUB1)

0

1

*

0

1

0

1

0

1

0

1

0

1

0

1

*

Input Selector (SUB2)

Mode Select

FL, FRch

Mode Select

C, SWch

Mode Select

SL, SRch

Mode Select

SBL, SBRch

2

3

4

6

7

0

ADC ATT

Chip

Select

Volume channel

Select

Volume

HPOUT MSEL MSEL MSEL MSEL

SEL

SB

SUB

0

FRONT C,SW

SUR

SURB OUTSEL MUTE

Mode Select

REC

Mode Select

SUB

1

Volume2

A→B

switch-time

B→A

switch-time

Base

0

System

Reset

0

Clock

BD3843FS (6ch Selector IC)

BD3841FS (9ch Selector IC)

BD3812F (2ch volume IC)

1

*

BD3471KS2, BD3473KS2 and BD3474KS2 could be controlled using same serial control line.

(In case of using the serial bus as common, please set chip select as“1”)

BD3843FS, BD3841FS and BD3812F could be controlled using same serial control line.

(In case of using the serial bus as common, please set chip select as“0”)

All data need to be initialized every time when turning on the power supply.

(Example)

← Input direction

Address

No.3

FRch

Address

No.3

FLch

Address

No.0

Address

No.1

Address

No.2

L

Address

No.3

Address

No.3

L

SBRch

SBLch

As for second time onwards, after turning on the power supply, sending data of any address could be changed.

(5) Chip Select Setting Table

CHIP terminal condition

0 (LOW)

D2

0

1 (HIGH)

1

BD34705KS2 can operate in combination with another by setting the CHIP terminal.

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Select Address No.0 Setting Table

Function & Setting D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

MUTE

IN1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

IN2

IN3

IN4

IN5

IN6

IN7

IN8

Rec

on/off

IN9

IN10

IN11

Sub

on/off

Chip

Select

IN12

IN13(REC)

IN14(SUB)

0

1

0

1

0

Prohibition

1

OFF

ON

0

1

Input Selector (MAIN)

OFF

ON

0

1

Rec

on/off

: Initial condition

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Select Address No.1 Setting Table

Function & Setting D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

MUTE

IN1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IN2

IN3

IN4

IN5

IN6

IN7

Input Selector (SUB2)

IN8

IN9

IN10

IN11

IN12

Chip

Select

0

1

Prohibition

1

MUTE

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Input Selector (SUB1)

Prohibition

1

: Initial condition

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Select Address No.2 Setting Table ※Select Address No.4 MSEL="0"(Front,C,SW,SR,SRB)

Function & Setting

MUTE

MAIN

D15 D14 D13 D12 D11 D10 D9 D8

D7

D6

D5

D4

D3

D2

D1

D0

0

1

0

1

0

1

Mode

Selector

C, SWch

MULTI

SUB1

Mode

Selector

SL, SRch

MUTE

MAIN

0

1

0

1

0

1

Mode

Selector

SBL,

MULTI

SUB1

SBRch

Chip

Select

0

ADC ATT

0

1

0

MUTE

MAIN

0

1

0

1

0

1

Mode

Selector

FL, FRch

MULTI

SUB1

Mode

Selector

C, SWch

MUTE

MULTI

SUB1

0

1

0

1

0

1

Mode

Selector

SL, SRch

MAIN

Select Address No.2 Setting Table ※Select Address No.4 MSEL="1"(Front,C,SW,SR,SRB)

Function & Setting

MUTE

D15 D14 D13 D12 D11 D10

D9 D8 D7

D6

D5

D4 D3

D2

D1 D0

0

Mode

Selector

C, SWch

SUB2

MUTE

0

1

Mode

Selector

SL, SRch

0

1

Mode

Selector

SBL,

SUB2

MUTE

SUB2

SBRch

Chip

Select

0

ADC ATT

0

1

0

1

Mode

Selector

FL, FRch

Mode

Selector

C, SWch

MUTE

SUB2

0

1

Mode

Selector

SL, SRch

Select Address No.2 Setting Table

Function & Setting

D15 D14 D13 D12 D11 D10 D9 D8

D7

D6

0

D5

0

D4

0

D3

D2

D1

D0

MUTE

0dB

0

1

-6dB

0

1

0

Mode

Selector

FL, FRch

Mode

Selector

C, SWch

Mode

Selector

SL, SRch SBL, SBRch

Mode

Selector

-6.5dB

0

1

Chip

Select

0

1

0

-7.5dB

1

0

-9dB

1

0

1

-12dB

1

0

Prohibition

1

: Initial condition

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Select Address No.3 Setting Table

Function & Setting

D15 D14 D13 D12 D11 D10

D9

D8

D7 D6 D5

D4

D3

D2

D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FL

FR

SW

C

Volume

SL

SR

SBL

SBR

MUTE

1

0

・

Prohibition

0

1

0

1

+32.0dB

+31.5dB

+31.0dB

+30.5dB

+30.0dB

+29.5dB

+29.0dB

+28.5dB

+28.0dB

+27.5dB

+27.0dB

+26.5dB

+26.0dB

+25.5dB

+25.0dB

+24.5dB

+24.0dB

+23.5dB

+23.0dB

+22.5dB

+22.0dB

+21.5dB

+21.0dB

+20.5dB

+20.0dB

+19.5dB

+19.0dB

+18.5dB

+18.0dB

+17.5dB

+17.0dB

+16.5dB

+16.0dB

+15.5dB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Chip

Select

0

1

Volume

Channel

Select

1

: Initial condition

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Select Address No.3 Setting Table

Function & Setting

D15 D14 D13 D12 D11 D10

D9

0

D8

1

D7 D6 D5

D4

0

D3

D2

D1

D0

+15.0dB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+14.5dB

0

1

+14.0dB

+13.5dB

+13.0dB

+12.5dB

+12.0dB

+11.5dB

+11.0dB

+10.5dB

+10.0dB

+9.5dB

+9.0dB

+8.5dB

+8.0dB

+7.5dB

+7.0dB

+6.5dB

+6.0dB

+5.5dB

+5.0dB

+4.5dB

+4.0dB

+3.5dB

+3.0dB

+2.5dB

+2.0dB

+1.5dB

+1.0dB

+0.5dB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Volume

Channel

Select

Chip

Select

0

1

Prohibition

-0dB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

-0.5dB

-1.0dB

-1.5dB

-2.0dB

-2.5dB

-3.0dB

-3.5dB

-4.0dB

-4.5dB

-5.0dB

-5.5dB

-6.0dB

-6.5dB

-7.0dB

-7.5dB

0

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Select Address No.3 Setting Table

Function & Setting

-8.0dB

D15 D14 D13 D12 D11 D10

D9

0

1

D8

1

0

D7 D6 D5

D4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D3

D2

D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

-8.5dB

-9.0dB

-9.5dB

-10.0dB

-10.5dB

-11.0dB

-11.5dB

-12.0dB

-12.5dB

-13.0dB

-13.5dB

-14.0dB

-14.5dB

-15.0dB

-15.5dB

-16.0dB

-16.5dB

-17.0dB

-17.5dB

-18.0dB

-18.5dB

-19.0dB

-19.5dB

-20.0dB

-20.5dB

-21.0dB

-21.5dB

-22.0dB

-22.5dB

Volume

Channel

Select

Chip

Select

0

1

-23.0dB

0

1

0

1

0

-23.5dB

-24.0dB

-24.5dB

-25.0dB

-25.5dB

-26.0dB

-26.5dB

-27.0dB

-27.5dB

-28.0dB

-28.5dB

-29.0dB

-29.5dB

-30.0dB

-30.5dB

-31.0dB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

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Select Address No.3 Setting Table

Function & Setting

-31.5dB

-32.0dB

-32.5dB

-33.0dB

-33.5dB

-34.0dB

-34.5dB

-35.0dB

-35.5dB

-36.0dB

-36.5dB

-37.0dB

-37.5dB

-38.0dB

-38.5dB

-39.0dB

-39.5dB

-40.0dB

-40.5dB

-41.0dB

-41.5dB

-42.0dB

-42.5dB

-43.0dB

-43.5dB

-44.0dB

-44.5dB

-45.0dB

-45.5dB

-46.0dB

D15 D14 D13 D12 D11 D10

D9

1

0

D8

1

0

1

D7 D6 D5

D4

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

D3

D2

D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Volume

Channel

Select

Chip

Select

0

1

-46.5dB

0

1

0

1

0

1

-47.0dB

-47.5dB

-48.0dB

-48.5dB

-49.0dB

-49.5dB

-50.0dB

-50.5dB

-51.0dB

-51.5dB

-52.0dB

-52.5dB

-53.0dB

-53.5dB

-54.0dB

-54.5dB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

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Select Address No.3 Setting Table

Function & Setting

-55.0dB

-55.5dB

-56.0dB

-56.5dB

-57.0dB

-57.5dB

-58.0dB

-58.5dB

-59.0dB

-59.5dB

-60.0dB

-60.5dB

-61.0dB

-61.5dB

-62.0dB

-62.5dB

-63.0dB

-63.5dB

-64.0dB

-64.5dB

-65.0dB

-65.5dB

-66.0dB

-66.5dB

-67.0dB

-67.5dB

-68.0dB

-68.5dB

-69.0dB

-69.5dB

D15 D14 D13 D12 D11 D10

D9

1

0

D8

0

1

0

D7 D6 D5

D4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D3

D2

D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Volume

Channel

Select

Chip

Select

0

1

-70.0dB

1

0

1

0

-70.5dB

-71.0dB

-71.5dB

-72.0dB

-72.5dB

-73.0dB

-73.5dB

-74.0dB

-74.5dB

-75.0dB

-75.5dB

-76.0dB

-76.5dB

-77.0dB

-77.5dB

-78.0dB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

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Select Address No.3 Setting Table

Function & Setting

-78.5dB

-79.0dB

-79.5dB

-80.0dB

-80.5dB

-81.0dB

-81.5dB

-82.0dB

-82.5dB

-83.0dB

-83.5dB

-84.0dB

-84.5dB

-85.0dB

-85.5dB

-86.0dB

-86.5dB

-87.0dB

-87.5dB

-88.0dB

-88.5dB

-89.0dB

-89.5dB

-90.0dB

-90.5dB

-91.0dB

-91.5dB

-92.0dB

-92.5dB

-93.0dB

D15 D14 D13 D12 D11 D10

D9

0

1

D8

1

0

1

D7 D6 D5

D4

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

D3

D2

D1

D0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Volume

Channel

Select

Chip

Select

0

1

-93.5dB

1

0

1

0

1

-94.0dB

-94.5dB

-95.0dB

1

0

1

0

1

0

1

0

1

・

Prohibition

1

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Select Address No.4 Setting Table ※ON/OFF of each MSEL is reflected by Address No. 2 mode selector

Function & Setting

D15 D14 D13 D12 D11 D10 D9

D8

D7 D6 D5 D4 D3

D2 D1 D0

MUTE

0

MSEL

FRONT

MSEL

C,SW

MSEL

FRONT

1

OFF

ON

0

SUR

MSEL

1

SURB

SB

OFF

ON

0

SELECT

SUB

MUTE

1

Chip

Select

0

1

0

OFF

ON

0

1

HPOUT

SEL

OFF

ON

0

1

MSEL

FRONT

MSEL

C,SW

SURB

FRONT

OFF

ON

0

1

MSEL

SUR

MSEL

SURB

0

1

SB

SELECT

Select Address No.6 Setting Table

Function & Setting

MAIN

D15 D14 D13 D12 D11 D10 D9

D8 D7 D6 D5

D4

D3

D2

D1 D0

0

1

0

1

0

1

Mode

Selector

SUB

SUB1

SUB2

MULTI

Volume2

MAIN

0

1

0

1

0

1

SUB1

SUB2

MULTI

MUTE

1

0

Prohibition

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Chip

Select

1

0

+6.0dB

+5.0dB

+4.0dB

+3.0dB

+2.0dB

+1.0dB

+0.0dB

-1.0dB

-2.0dB

-3.0dB

-4.0dB

-5.0dB

1

0

Mode

Selector

REC

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Select Address No.6 Setting Table

Function & Setting

-6.0dB

D15 D14 D13 D12 D11 D10

D9

0

1

D8

0

1

0

D7 D6 D5

D4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D3

D2

D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

-7.0dB

-8.0dB

-9.0dB

-10.0dB

-11.0dB

-12.0dB

-13.0dB

-14.0dB

-15.0dB

-16.0dB

-18.0dB

-20.0dB

-22.0dB

-24.0dB

-26.0dB

-28.0dB

-30.0dB

-32.0dB

-34.0dB

-36.0dB

-38.0dB

-40.0dB

-42.0dB

-44.0dB

-46.0dB

-48.0dB

-50.0dB

-52.0dB

-54.0dB

-56.0dB

0

Mode

Selector

SUB

Mode

Selector

REC

Chip

Select

1

0

Prohibition

1

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Select Address No.7 Setting Table

Function & Setting

11msec

D15 D14 D13 D12 D11 D10 D9 D8 D7

D6

D5 D4

D3

D2

D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

5msec

7msec

14msec

3msec

B→A

switching-time

2msec

Prohibition

Base

Clock

11msec

5msec

7msec

14msec

3msec

2msec

0

1

0

1

0

1

0

1

0

1

0

1

0

1

System

Reset

Chip

Select

0

1

A→B

Prohibition

switching-time

x1

0

1

×1/2

B→A

switching-time

Normal

0

1

Base

Clock

Reset

: Initial condition

Select Address No.7, Data = D15-D13：Below A → B switching time is adjustable.

Select Address No.7, Data = D12-D10：Below B → A switching time is adjustable.

※Switching time over 11.2msec is recommended for both A→B and B→A.

※Set to same switching time for both A→B, B→A is recommended if the switching times need to be changed.

[wait time]

=Twait

[A→B switching time]

=Tsft

[B→A switching time]

=Tsft

Current XdB

Send YdB

Change YdB

W

A → B

B → A

Switching Time (Tsoft)

Figure 11. Micro step volume switching time

If the base clock is set to x1/2, the switching time will be doubled.

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Micro step volume circuit

1. Micro step volume technology.

1-1. Micro step volume effects.

Micro step volume is ROHM original switching pop noise prevention technology. The audible signal is discontinuous

during the gain switching instantly which cause the noise to occur. This micro step volume will prevent this discontinuous

signal by completing the signal waveform and will significantly reduce the noise.

Control signal

If the gain instantly changes after the data is transmitted, the DC fluctuation

will occur as much as before and after the oscillation different. This

technology makes this fluctuation changes slow.

DC

fluctuation

Micro step

volume

waveform

Figure 12. Micro step volume waveform

This micro step volume will start the switching when received the signal sent from the micon.

At any constant time, the switching waveform is shown as above figure. This IC will optimally operates by internally

processes the data sent from the micon to prevent the switching shock.

However, sometimes the switching waveform is not like the intended form depends on the transmission timing.

Therefore, below is the example of the relationship between the transmission timing and actual switching time. Please

consider this relationship for the setting.

1-2. Micro step volume application target block

・Micro step volume application target blocks are 7.1ch volume and SUB volume.

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2．About data transmission of Micro step volume circuit

2-1. Switching time of Micro step volume

This switching time includes [Wait time], [A→B switching time] and [B→A switching time]. Every switching time needs

around 25msec. (Tsoft = Twait + 2 * Tsft, Twait=2.3msec, Tsft=11.2msec)

Please take note that Twait is wait time for starting switching and the setting is 2.3msec. (Twait considers the internal IC

tolerance, therefore this time need to be set within 1.3msec (Min.) to 4.6msec (Max.).

[wait time]

=Twait

[A→B switching time]

=Tsft

[B→A switching time]

=Tsft

Current XdB

Send YdB

Change YdB

W

A → B

B → A

Switching Time (Tsoft)

Figure 13. [A→B switching time] and [B→A switching time]

In addition, base clock can change the frequency using the internal oscillation device. For example, when base clock

x1/2 is selected, [Wait time], [A→B switching time] and [B→A switching time] are doubled.

2-2. Same block data transmission timing and switching operation.

■ Transmission example 1

The time chart from data transmission to switching start time is shown as below.

At first, below figure shows transmitted data with the same block which is separated with enough interval.

This enough interval refers to the tolerance margin time of Tsoft multiplied by 1.4.

Serial data

(FL 0dB)

(FL -∞dB)

Tsoft * 1.4 msec

W

A → B

B → A

W

A → B

B → A

Switching time

FL output

■

Transmission example 2

Next, below figure shows the example of when the transmission interval is not enough (smaller than above interval).

When the data transmitted during the first operation of the switching, the second data transmission will continue after

complete the first operation. In this case, there is no wait time (Twait) before the second transmission.

Serial data

(FL 0dB)

(FL -∞dB)

W

A → B

B → A

A → B

B → A

Switching time

FL output

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■ Transmission example 3

Next is the example for switching operation with smaller data transmission interval.

invalid data

①

W

②

③

④

Serial data

A → B

B → A

A → B

B → A

④

Switching time

Output

Initial

Initial → ①

① → ②

② → ④

Data ② is the data during the A→B operation, so this data is valid, and then during B→A operation, data ① promptly

switches to data②.

Data ③ and data ④ are data during B→A operation, therefore these data are valid for the next switching, but data ③ got

overwritten by data ④ so data ③ will become invalid. Only data ④ is valid.

There is no regulation on the transmission timing.

For data transmission to multi-channels, there is a caution. The combination of Lch and Rch for same block will make the

switching is possible to change at same timing. When the setting is data ① for FL (Lch) and data ② for FR (Rch), same

switching timing is possible if the data transmission is set as below figure.

FL

FR

① ②

Serial data

T

ꢀ＜ Twait

②-①

W

A → B

B → A

①

Switching time

Output FL

Initial

Initial → ①

Initial → ②

Output FR

Initial

②

Figure 14. The operation during multi-channels (Lch, Rch) data transmission (smaller than Twait interval).

Next, when data ② is not transmitted during the Twait, the switching operation is as following figure.

FR

FL

①

②

Serial data

T ꢀ＞ Twait

②-①

W

A → B

B → A

①

A → B

B → A

Switching time

Output FL

Initial

Initial → ①

Output FR

Initial → ②

②

Figure 15. The operation during multi-channels (Lch, Rch) data transmission (larger than Twait interval).

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2-3. Multi-blocks data transmission timing and switching operation.

In case of the data is transmitted to the multi-blocks, the processing is performed to each sequence which is

defined by the IC internally.

This sequence determines the Micro step volume starting order operation.

■Transmission example 1

In case of multi-channels operates as transmission order (during 3 channels transmission).

Serial data

(FL 0dB)

(SW 0dB)

(SL 0dB)

FL Switching time

A → B

SW Switching time

A → B

SL Switching time

W

B → A

A → B

B → A

Switching time

FL output

SW output

SL output

There is no constraint for the data transmission timing, however the timing of switching start becomes to switching after

the current timing is ended.

Please take note that, the timing of switching start is not depending on data setting order but only based on the regulated

order by Figure16. (Transmission example 2)

State2

SW

State4

SBL

State5

SUBL

State1

FL

State3

SL

Lch

Rch

FR

C

SR

SBR

SUBR

Figure 16. Volume switching stage

※Blocks in the same stage is possible to start the switching at the same timing.

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■Transmission example 2

In case of the transmission order is different with actual switching order.

例：①FL -6dB

②FL -20dB

③SL -6dB

④SW -6dB

①

② ③ ④

Serial data

FL Switching time

SW Switch time

SL Switching time

FL Switching time

W

A → B

B → A

A → B

B → A

A → B

B → A

A → B

B → A

②

Switching time

Output FL

Initial Initial → ①

①

① → ②

Output SW

Output SL

Initial

Initial → ④

④

Initial → ③

③

During FL switching, in case of FL/SW/SL continuously received, SW and SL switching are the priority.

If you want the switching starts as the data transmission order, please transmit the next data after current switching is

ended.

■Transmission example 3

For same data transmission, the IC will internally judge that there is no difference with the current data setting and

therefore gain switching operation will not start.

Continuing the same data transmission and transmit the other block data.

Serial data

(FL 0dB)

(SW 0dB)

same data

FL Switching time

SW Switching time

W

A → B

B → A

A → B

B → A

Switching time

2-4. How to reduce pop noise

Pop noise level is different base on the Micro step internal state A and B output DC offset difference.

To reduce the pop noise level, set for longer switching time might solve this problem.

Change the setting for [A→B switching time] and [B→A switching time], and confirm pop the noise level.

At this time, if [A→B switching time] and [A→B switching time] setting is different, the pop noise reduction effect will

decrease. Therefore, it is recommended to set these switching with same time.

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Application Circuit Diagram

INR1

45

INL1

44

INR2

43

INL2

42

INR3

41

INL3

40

INR4

39

INL4

38

INR5

37

INL5

36

INR6

35

INL6

34

46

33

Main

Sub1

STEREO

INPUT

MULTI

INPUT

STEREO

INPUT

MULTI

INPUT

Sub2

47

SBLIN

INL9

INR9

32

INR7

INL7

CIN2

SWIN2

SBRIN

48

49

31

30

INL10

INR10

SLIN

SRIN

INR8

INL8

FRIN2

FLIN2

50

51

52

29

28

Mode

selector

Mode

selector

Mode

selector

Mode

selector

INL11

INR11

CIN

SWIN

STEREO STEREO

OUTPUT INPUT

Rec

7.1chOUT +32dB～

53

54

-95dB,-INF/0.5dB step

INL12

INR12

FLIN

FRIN

RECR

INR13

27

26

10μ

RECL

INL13

SBR

Volume

FR

Volume

SR

FL

Volume

SW

Volume

C

SL

SBL

Volume

55

Rec Selector

Sub

ADC

ADCL

56

57

10μ

INR14

INL14

25

24

SUBR

SUBL

10μ

ADCR

58

59

Sub Selector

60

61

62

63

SUBOUT

+6dB～-16dB/1dB step

-16dB～-56dB/2dB step

MUTE

23

22

21

20

HP-OUT

FRONT/MUTE

64

Logic

CHIP

15

16

17

18

19

14

1

2

3

4

5

6

7

8

9

10

11

12

13

10μ

OUTFR

10μ

OUTHPR

10μ

OUTSW

VEE2

DA

CL

DGND

2200p

OUTSBR

OUTSR

OUTSL

470μ

OUTFL

OUTC

2200p

470u

OUTSBL

OUTHPL

VCC

VEE1

Figure 17. Application Circuit Diagram

Notes on wiring

①GND has to be wired from reference point and it should be thick.

②Wiring pattern of CL and DA shall be away from the analog unit and cross-talk is not acceptable.

③If possible, lines of CL and DA are not parallel. If they are adjacent to each other, the lines should be shielded.

④Please concentrate on wiring pattern of the input terminal for input selector to the crosstalk.

It is recommended that it is shielded during wiring period.

⑤Please connect the decoupling capacitor of the power supply in the shortest distance as much as possible to

VCC, GND and VEE.

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Power Dissipation

Thermal design for the IC

Temperature has great influence to the IC characteristics, and exceeding the absolute maximum ratings may degrade and

damage the IC. A proper consideration must be given from two points, immediate damage and long-term reliability of

operation.

Reference data

SQFP-T64

Measurement condition: ROHM Standard board

Board Size：70×70×1.6(㎣)

Material：A FR4 grass epoxy board

2.0

1.0

(3% or less of copper foil area)

1.50W

θja = 83.3°C/W

0.0

85

0

25

50

75

100

125

150

Ambient Temperature Ta(°C)

Figure 18. Temperature Derating Curve

Note) Values mentioned above are based on actual measurement, and not guaranteed.

Power dissipation value varies depending to the board on which the IC is mounted.

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I/O equivalence circuit(s)

Terminal

Number

Terminal

Name

Terminal

Voltage (V)

Equivalent Circuit

Terminal Description

Vcc

Analog ground terminals.

18～23

28

33

46

GND

0

55

58～63

Vee

Positive power supply terminal

Negative power supply terminal

3

5

7

VCC

VEE1

VEE2

+7

-7

Digital ground terminal.

Vcc

4

DGND

0

Vee

Vcc

Input terminals for a clock and data.

1

2

64

DA

CL

CHIP

-

Vee

Output terminals for analog sound signal.

8

9

OUTFRL

OUTFL

OUTSW

OUTC

OUTSR

OUTSL

OUTSBR

OUTSBL

ADCL

Vcc

10

11

12

13

14

15

56

57

0

Vee

ADCR

Output terminals for analog sound signal.

(SUB/REC)

Vcc

24

25

26

27

SUBL

SUBR

RECL

RECR

0

47k

Vee

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BD34705KS2

Terminal

Number

Terminal

Name

Terminal

Voltage (V)

Equivalent Circuit

Terminal Description

Input terminals for stereo sound signal.

Input impedance is 47kΩ(Typ.).

30

29

32

31

35

34

37

36

39

38

41

40

43

42

45

44

INR8

INL8

INR7

INL7

INR6

INL6

INR5

INL5

INR4

INL4

INR3

INL3

INR2

INL2

INR1

INL1

Vcc

47k

0

Vee

Vcc

Input terminals for an analog multi sound

signal.

Input impedance is 47kΩ(Typ.).

48

47

50

49

51

52

54

53

SBRIN

SBLIN

SRIN

SLIN

CIN

SWIN

FRIN

FLIN

47k

0

Vee

Output terminal for FRONT pre-output.

The impedance of output switch is

0.8kΩ(typ.).

Vcc

16

17

OUTHPR

OUTHPL

0

Vee

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Operational Notes

1.

2.

Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply terminals.

Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the

digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog

block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and

aging on the capacitance value when using electrolytic capacitors.

3.

4.

Vee Voltage

Ensure that no pins are at a voltage below that of the VEE pin at any time, even during transient condition.

Ground Wiring Pattern

GND pins which are digital ground(4pin) and analog ground(18-23,28,33,46,55,58-63pin) are not connected inside

LSI. These ground pins traces should be routed separately but connected to a single ground at the reference point of

the application board. Also ensure that the ground traces of external components do not cause variations on the

ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5.

Thermal Consideration

Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in

deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when

the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum

rating, increase the board size and copper area to prevent exceeding the Pd rating.

6.

7.

Recommended Operating Conditions

These conditions represent a range within which the expected characteristics of the IC can be approximately

obtained. The electrical characteristics are guaranteed under the conditions of each parameter.

Rush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush

current may flow instantaneously due to the internal powering sequence and delays, especially if the IC

has more than one power supply. Therefore, give special consideration to power coupling capacitance,

power wiring, width of ground wiring, and routing of connections.

8.

9.

Operation Under Strong Electromagnetic Field

Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.

Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to IC pin may subject the IC to stress.

Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned

off completely before connecting or removing it from the test setup during the inspection process. To prevent damage

from static discharge, ground the IC during assembly and use similar precautions during transport and storage.

10. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)

and unintentional solder bridge deposited in between pins during assembly to name a few.

11. Unused Input Terminals

Because the input impedance of the terminal becomes 47kΩ when the signal input terminal makes a terminal open,

the plunge noise from outside sometimes becomes a problem. Please connect the no using input pin to GND. And

please open the no using output pin.

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Operational Notes – continued 1

12. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When Vee > Pin A and Vee > Pin B, the P-N junction operates as a parasitic diode.

When Vee > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the Vee voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor( NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

Vee Vee

P Substrate

Vee

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 19. Example of monolithic IC structure

13. Ceramic Capacitor

When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

14. About power ON/OFF

1. At power ON/OFF, a pop sound will be generated and, therefore, use MUTE on the set.

2. When turning on power supplies, VEE and VCC should be powered on simultaneously or VEE first; then

followed by VCC.(t_delayshould be VEE=<VCC on power ON, VCC=<VEE on power OFF) If the VCC side is

started up first, an excessive current may pass VCC through Vee.

3.This IC include power ON reset circuit. To be effective this function, t_riseshould be more than 20μsec.

tdelay

trise

VCC

VEE

trise

Figure 20. Timing sequence of power on/off operation

15. About function switching

When switching Input Selector, Mode selector or Input Gain, use MUTE on Volume.

16. Volume gain switching

In case of the boost of the volume when changing to the high gain which exceeds +20dB especially, the switching

pop noise sometimes becomes big. In this case, we recommend changing every 1 dB step without changing a gain at

once. Also, the pop noise sometimes can reduce by making micro-step volume switching time long, too.

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Operational Notes – continued 2

17. Output load characteristic

The usages of load for output are below (reference). Please use the load more than 10 kΩ(TYP).

Output terminal

Terminal

No.

8

Terminal

No.

12

Terminal

Name

OUTSR

OUTSL

OUTSBR

OUTSBL

Terminal

No.

25

Terminal

Name

SUBR

SUBL

RECR

RECL

Terminal

Name

ADCL

ADCR

Name

OUTFR

OUTFL

OUTSW

OUTC

No.

56

57

-

9

10

11

13

14

15

24

27

26

-

5

4

3

2

1

Vcc=+7V

Vee=-7V

THD+N=1%

BW=400～30kHz

0

100

1000

10000

100000

Load Resistance Ω

Figure 21. Output load characteristic at Vcc=+7V, Vee=-7V(Reference)

Ordering Information

B D 3 4 7 0 5 K S 2

-

Package

KS2: SQFP-T64

Packaging and forming specification

none: Tray

Part Number

E2: Embossed tape and reel

Marking Diagram(TOP VIEW)

SQFP-T64 (TOP VIEW)

Part Number Marking

LOT Number

BD34705KS2

1PIN MARK

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Physical Dimension, Tape and Reel Information

Package Name

SQFP-T64

BD34705KS2

Lot No.

Container

Quantity

Tray (with dry pack)

1000pcs

Direction of feed Direction of product is fixed in a tray

1pin

Order quantity needs to be multiple of the minimum quantity.

∗

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改訂履歴

Date

Revision

001

変更内容

31.Mar.2015

New Release

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Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of

flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning

residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual

ambient temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.001

Daattaasshheeeett

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

QR code printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.001

Daattaasshheeeett

General Precaution

1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.

ROHM shall not be in an y way responsible or liable for failure, malfunction or accident arising from the use of a ny

ROHM’s Products against warning, caution or note contained in this document.

2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior

notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s

representative.

3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all

information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or

liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or

concerning such information.

Notice – WE

Rev.001


型号：	BD34705KS2
厂家：	ROHM
描述：	适用于实现7.1ch环绕声系统的8ch独立音量。与以往产品相比，大幅改善了音质。具备μ-step功能，实现了增益切换时的爆破音较少的音量。内置最多可支持Zone3的单端8路输入选择器、多路输入选择器，可连接大多数信号源。ROHM Musical Device "MUS-IC""MUS-IC" Web Page
文件：	总39页 (文件大小：1426K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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