MTD6N20E [ROCHESTER]
6A, 200V, 0.7ohm, N-CHANNEL, Si, POWER, MOSFET, DPAK-3;
| 型号： | MTD6N20E |
| 厂家： | 
Rochester Electronics |
| 描述： | 6A, 200V, 0.7ohm, N-CHANNEL, Si, POWER, MOSFET, DPAK-3 局域网 开关 脉冲 晶体管 |
| 文件： | 总10页 (文件大小：768K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MTD6N20E
Preferred Device
Power MOSFET
6 Amps, 200 Volts
N−Channel DPAK
This advanced Power MOSFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain−to−source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor controls,
these devices are particularly well suited for bridge circuits where
diode speed and commutating safe operating areas are critical and
offer additional safety margin against unexpected voltage transients.
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6 AMPERES, 200 VOLTS
RDS(on) = 460 mW
N−Channel
D
Features
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
G
• I
and V
Specified at Elevated Temperature
DSS
DS(on)
S
• Pb−Free Package is Available*
MARKING
DIAGRAMS
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol Value
Unit
Vdc
Vdc
Drain−to−Source Voltage
V
200
200
4 Drain
DSS
DGR
Drain−to−Gate Voltage (R = 1.0 MW)
V
GS
4
DPAK
CASE 369C
STYLE 2
Gate−to−Source Voltage
− Continuous
V
20
40
Vdc
Vpk
GS
2
1
V
GSM
− Non−repetitive (t ≤ 10 ms)
p
3
Drain Current
− Continuous
− Continuous @ 100°C
− Single Pulse (t ≤ 10 ms)
2
1
Gate
3
I
I
6.0
3.8
18
Adc
Apk
D
D
Drain
Source
I
DM
p
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ T = 25°C (Note 2)
P
50
0.4
1.75
W
W/°C
W
4
D
4 Drain
A
DPAK
CASE 369D
STYLE 2
Operating and Storage Temperature Range
T , T
J
−55 to
150
°C
stg
1
2
Single Pulse Drain−to−Source Avalanche
E
54
mJ
AS
3
Energy − Starting T = 25°C
J
(V = 80 Vdc, V = 10 Vdc,
DD
GS
I = 6.0 Apk, L = 3.0 mH, R = 25 W)
L
G
1
2
3
Gate Drain Source
6N20E Device Code
Thermal Resistance − Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
R
R
R
2.50
100
71.4
°C/W
°C
q
JC
JA
JA
Y
= Year
q
q
WW
G
= Work Week
= Pb−Free Package
Maximum Temperature for Soldering
T
260
L
Purposes, 1/8″ from case for 10 secs
ORDERING INFORMATION
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
2. When surface mounted to an FR4 board using the 0.5 sq. in. drain pad size.
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
August, 2005 − Rev. 3
MTD6N20E/D
MTD6N20E
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
V
(BR)DSS
200
−
−
689
−
−
Vdc
mV/°C
(V = 0 Vdc, I = 0.25 mAdc)
GS
D
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
I
mAdc
DSS
GSS
−
−
−
−
10
100
(V = 200 Vdc, V = 0 Vdc)
DS
GS
(V = 200 Vdc, V = 0 Vdc, T = 125°C)
DS
GS
J
Gate−Body Leakage Current (V
=
ꢀ20 Vdc, V = 0)
−
−
100
nAdc
GS
DS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
V
GS(th)
2.0
−
3.0
7.1
4.0
−
Vdc
mV/°C
(V = V , I = 250 mAdc)
DS
GS
D
Temperature Coefficient (Negative)
Static Drain−Source On−Resistance (V = 10 Vdc, I = 3.0 Adc)
R
V
−
0.46
0.700
Ohm
Vdc
GS
D
DS(on)
Drain−Source On−Voltage (V = 10 Vdc)
GS
DS(on)
−
−
2.9
−
5.0
4.4
(I = 6.0 Adc)
(I = 3.0 Adc, T = 125°C)
D
D
J
Forward Transconductance (V = 15 Vdc, I = 3.0 Adc)
g
FS
1.5
−
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
−
−
−
342
92
480
130
55
(V = 25 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
C
rss
27
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
t
−
−
−
−
−
−
−
−
8.8
29
17.6
58
44
40.8
21
−
ns
d(on)
(V = 100 Vdc, I = 6.0 Adc,
Rise Time
t
DD
D
r
V
= 10 Vdc,
GS
Turn−Off Delay Time
Fall Time
t
22
R
G
= 9.1 W)
d(off)
t
20
f
Gate Charge
(See Figure 8)
Q
T
Q
1
Q
2
Q
3
13.7
2.7
7.1
5.9
nC
(V = 160 Vdc, I = 6.0 Adc,
DS
D
V
= 10 Vdc)
GS
−
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 3)
(I = 6.0 Adc, V = 0 Vdc)
V
SD
Vdc
ns
S
GS
(I = 6.0 Adc, V = 0 Vdc,
−
−
0.99
0.9
1.2
−
S
GS
T = 125°C)
J
Reverse Recovery Time
(See Figure 14)
t
−
−
−
−
138
93
−
−
−
−
rr
t
a
(I = 6.0 Adc, V = 0 Vdc,
S
GS
dI /dt = 100 A/ms)
S
t
45
b
Reverse Recovery Stored Charge
Q
0.74
mC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
−
−
4.5
7.5
−
−
nH
nH
D
Internal Source Inductance
L
S
(Measured from the source lead 0.25″ from package to source bond pad)
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
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2
MTD6N20E
TYPICAL ELECTRICAL CHARACTERISTICS
12
10
8
12
V
= 10 V
9 V
8 V
T = −ꢀ55°C
T = 25°C
J
V
≥ 10 V
DS
GS
J
10
8
25°C
100°C
7 V
6
6
6 V
5 V
4
4
2
0
2
0
0
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
1.2
1.0
0.8
0.6
0.4
0.70
0.65
0.60
0.55
0.50
0.45
0.40
T = 25°C
V
= 10 V
J
GS
T = 100°C
J
25°C
V
= 10 V
15 V
GS
−ꢀ55°C
0.2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.5
2.0
1.5
1.0
0.5
0
100
10
1
V = 10 V
GS
I = 3 A
V
= 0 V
GS
T = 125°C
J
D
100°C
25°C
− 50
− 25
0
25
50
75
100
125
150
0
50
100
150
200
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
MTD6N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
900
750
600
450
300
150
0
V
= 0 V
V
= 0 V
GS
DS
T = 25°C
J
C
C
iss
C
iss
rss
C
oss
C
rss
10
5
0
5
10
15
20
25
V
V
DS
GS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
MTD6N20E
12
10
8
1000
100
10
90
75
V
I = 6 A
= 100 V
DD
Q
T
D
V
= 10 V
GS
V
GS
T = 25°C
J
Q
Q
2
1
60
45
30
15
0
6
t
r
t
f
t
d(off)
4
t
d(on)
I = 6 A
D
T = 25°C
J
2
V
Q
DS
3
0
1
0
2
4
6
8
10
12
14
1
10
R , GATE RESISTANCE (OHMS)
100
Q , TOTAL CHARGE (nC)
T
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
6
V
= 0 V
GS
T = 25°C
J
5
4
3
2
1
0
0.5
0.6
0.7
0.8
0.9
1.0
V
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
temperature and a case temperature (T ) of 25°C. Peak
C
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t ,t ) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
r f
energy at currents below rated continuous I can safely be
exceed (T
− T )/(R ).
D
J(MAX)
C qJC
assumed to equal the values indicated.
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
MTD6N20E
SAFE OPERATING AREA
100
10
60
50
I = 6 A
D
V
= 20 V
SINGLE PULSE
GS
T = 25°C
C
10 ms
40
30
20
10
0
100 ms
1.0
0.1
1 ms
10 ms
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
1.0
10
100
1000
25
50
75
100
125
150
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
0.2
0.1
0.05
0.1
P
(pk)
R
(t) = r(t) R
q
JC
q
JC
0.02
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.01
t
1
1
SINGLE PULSE
t
2
T
− T = P
C
R (t)
q
JC
J(pk)
(pk)
DUTY CYCLE, D = t /t
1 2
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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6
MTD6N20E
ORDERING INFORMATION
†
Device
MTD6N20E
Package
Shipping
DPAK
75 Units / Rail
75 Units / Rail
MTD6N20E1
DPAK
Straight Lead
MTD6N20ET4
DPAK
2500 Tape & Reel
2500 Tape & Reel
MTD6N20ET4G
DPAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MTD6N20E
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
SEATING
PLANE
−T−
C
B
R
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
E
V
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
4
2
Z
A
K
S
4.58 BSC
1
3
0.87
0.46
2.60
1.01
0.58
2.89
U
K
L
2.29 BSC
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
F
J
0.020
0.035 0.050
0.155 −−−
−−−
L
H
D 2 PL
STYLE 2:
PIN 1. GATE
2. DRAIN
M
G
0.13 (0.005)
T
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
3.0
0.244
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MTD6N20E
PACKAGE DIMENSIONS
DPAK
CASE 369D−01
ISSUE B
NOTES:
C
B
R
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
V
S
E
INCHES
DIM MIN MAX
MILLIMETERS
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.35
6.73
2.38
0.88
0.58
1.14
4
2
Z
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
A
K
1
3
−T−
SEATING
PLANE
2.29 BSC
0.87
0.46
8.89
4.45
0.63
0.89
3.93
1.01
0.58
9.65
5.45
1.01
1.27
−−−
J
F
H
0.155
−−−
D 3 PL
STYLE 2:
PIN 1. GATE
G
M
T
0.13 (0.005)
2. DRAIN
3. SOURCE
4. DRAIN
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MTD6N20E/D
相关型号：
MTD6N20ET5G
6A, 200V, 0.7ohm, N-CHANNEL, Si, POWER, MOSFET, ROHS COMPLIANT, PLASTIC, CASE 369C-01, DPAK-3
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