MTD6P10ET4G [ONSEMI]
6A, 100V, 0.66ohm, P-CHANNEL, Si, POWER, MOSFET, LEAD FREE, CASE 369C-01, DPAK-3;
| 型号： | MTD6P10ET4G |
| 厂家： | 
ONSEMI |
| 描述： | 6A, 100V, 0.66ohm, P-CHANNEL, Si, POWER, MOSFET, LEAD FREE, CASE 369C-01, DPAK-3 局域网 开关 脉冲 晶体管 |
| 文件： | 总8页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MTD6P10E
Preferred Device
Power MOSFET
6 Amps, 100 Volts
P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
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V
R
TYP
I MAX
D
(BR)DSS
DS(on)
100 V
660 mW
6.0 A
P−Channel
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
D
• Diode is Characterized for Use in Bridge Circuits
• I
and V
Specified at Elevated Temperature
G
DSS
DS(on)
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
S
Rating
Symbol
Value
Unit
MARKING DIAGRAM
Drain−to−Source Voltage
V
DSS
100
Vdc
& PIN ASSIGNMENTS
Drain−to−Gate Voltage (R = 1.0 MΩ)
V
DGR
100
Vdc
GS
4
4
Drain
Gate−to−Source Voltage
− Continuous
V
± 15
± 20
Vdc
Vpk
2
1
GS
− Non−repetitive (t ≤ 10 ms)
V
GSM
3
p
CASE 369C
DPAK
STYLE 2
Drain Current
− Continuous
− Continuous @ 100°C
− Single Pulse (t ≤ 10 µs)
I
I
6.0
3.9
18
Adc
Apk
D
D
1
2
3
I
DM
p
Gate
Drain Source
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ T = 25°C
P
D
50
0.4
1.75
Watts
W/°C
Watts
6P10E
Y
= Device Code
= Year
A
WW
T
= Work Week
= MOSFET
(Note 2.)
Operating and Storage Temperature
Range
T , T
−55 to
150
°C
J
stg
ORDERING INFORMATION
Single Pulse Drain−to−Source Avalanche
E
AS
180
mJ
†
Energy − Starting T = 25°C
J
Device
Package
DPAK
Shipping
(V = 25 Vdc, V = 10 Vdc,
DD
GS
I = 6.0 Apk, L = 10 mH, R = 25 Ω)
MTD6P10E
75 Units/Rail
L
G
Thermal Resistance
− Junction to Case
− Junction to Ambient (Note 1.)
− Junction to Ambient (Note 2.)
°C/W
°C
MTD6P10ET4
DPAK
2500 Tape & Reel
R
R
R
2.50
100
71.4
θ
JC
JA
JA
θ
θ
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Maximum Temperature for Soldering
Purposes, 1/8″ from case for 10
seconds
T
260
L
Preferred devices are recommended choices for future use
and best overall value.
1. When surface mounted to an FR4 board using the minimum
recommended pad size.
2. When surface mounted to an FR−4 board using the 0.5 sq.in. drain pad size.
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
November, 2003 − Rev. 2
MTD6P10E/D
MTD6P10E
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
V
(BR)DSS
(V = 0 Vdc, I = 0.250 µAdc)
Temperature Coefficient (Positive)
100
−
−
124
−
−
Vdc
mV/°C
GS
D
Zero Gate Voltage Drain Current
I
µAdc
DSS
GSS
(V = 100 Vdc, V = 0 Vdc)
−
−
−
−
10
100
DS
GS
(V = 100 Vdc, V = 0 Vdc, T = 125°C)
DS
GS
J
Gate−Body Leakage Current (V = ±15 Vdc, V = 0)
I
−
−
100
nAdc
GS
DS
ON CHARACTERISTICS (Note 1.)
Gate Threshold Voltage
(V = V , I = 250 µAdc)
V
GS(th)
2.0
−
2.9
4.0
4.0
−
Vdc
mV/°C
DS
GS
D
Temperature Coefficient (Negative)
Static Drain−Source On−Resistance (V = 10 Vdc, I = 3.0 Adc)
R
V
−
0.56
0.66
Ohm
Vdc
GS
D
DS(on)
Drain−Source On−Voltage (V = 10 Vdc)
GS
DS(on)
(I = 6.0 Adc)
(I = 3.0 Adc, T = 125°C)
D
−
−
3.6
−
4.8
4.2
D
J
Forward Transconductance (V = 15 Vdc, I = 3.0 Adc)
g
FS
1.5
3.0
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
550
154
27
840
240
56
iss
(V = 25 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (Note 2.)
Turn−On Delay Time
t
−
−
−
−
−
−
−
−
12
29
25
60
40
20
22
−
ns
d(on)
(V = 50 Vdc, I = 6.0 Adc,
DD
D
Rise Time
t
r
V
GS
= 10 Vdc,
Turn−Off Delay Time
Fall Time
t
18
d(off)
R
= 9.1 Ω)
G
t
f
9
Gate Charge
(See Figure 8)
Q
T
Q
1
Q
2
Q
3
15.3
4.1
7.1
6.8
nC
(V = 80 Vdc, I = 6.0 Adc,
DS
D
V
GS
= 10 Vdc)
−
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 1.)
(I = 6.0 Adc, V = 0 Vdc)
V
SD
Vdc
ns
S
GS
(I = 6.0 Adc, V = 0 Vdc,
−
−
1.8
1.5
5.0
−
S
GS
T = 125°C)
J
Reverse Recovery Time
(See Figure 14)
t
rr
−
−
−
−
112
92
−
−
−
−
t
a
(I = 6.0 Adc, V = 0 Vdc,
S
GS
t
b
20
dI /dt = 100 A/µs)
S
Reverse Recovery Stored
Charge
Q
0.603
µC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
−
−
4.5
7.5
−
−
nH
nH
D
Internal Source Inductance
L
S
(Measured from the source lead 0.25″ from package to source bond pad)
1. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
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2
MTD6P10E
TYPICAL ELECTRICAL CHARACTERISTICS
12
10
8
12
V
GS
= 10 V
T = −ꢀ55°C
T = 25°C
J
V
DS
≥ 10 V
J
9 V
8 V
25°C
10
8
100°C
6
6
7 V
4
4
6 V
5 V
2
0
2
0
0
2
4
6
8
10
12
14
16 18
20
2
3
4
5
6
7
8
9
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
1.0
0.9
0.8
0.7
0.6
T = 25°C
V
GS
= 10 V
J
T = 100°C
J
V
GS
= 10 V
25°C
15 V
6
0.5
0.4
−ꢀ55°C
0.4
0.3
0
2
4
6
8
10
12
0
2
4
8
10
12
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.8
1.6
100
V
= 10 V
V
GS
= 0 V
GS
I
D
= 3 A
1.4
1.2
1.0
0.8
0.6
0.4
T = 125°C
J
10
− 120
− 50
− 25
0
25
50
75
100
125
150
− 100
V
− 80
− 60
− 40
− 20
0
T , JUNCTION TEMPERATURE (°C)
J
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
MTD6P10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
The capacitance (C ) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
iss
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
1600
1400
1200
1000
800
600
400
200
0
V
GS
= 0 V
V
= 0 V
DS
T = 25°C
J
C
iss
C
rss
C
iss
C
oss
C
rss
10
5
0
5
10
15
20
25
V
GS
V
DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
MTD6P10E
12
10
8
1000
100
10
90
75
V
= 50 V
DD
Q
T
I
D
= 6 A
V
GS
V
= 10 V
GS
T = 25°C
Q
Q
2
1
J
60
45
30
15
0
6
t
r
t
d(off)
t
4
d(on)
I
= 6 A
D
t
f
T = 25°C
J
2
V
DS
Q
3
0
1
0
2
4
6
8
10
12
14
16
1
10
R , GATE RESISTANCE (OHMS)
100
Q , TOTAL CHARGE (nC)
T
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
6
V
= 0 V
GS
T = 25°C
5
4
3
2
J
1
0
0.50
0.75
1.0
1.25
1.50
1.75
2.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
temperature and a case temperature (T ) of 25°C. Peak
C
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t ,t ) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
r f
exceed (T
− T )/(R ).
energy at currents below rated continuous I can safely be
J(MAX)
C
θJC
D
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
assumed to equal the values indicated.
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5
MTD6P10E
SAFE OPERATING AREA
100
10
200
160
I
D
= 6 A
V
= 10 V
GS
SINGLE PULSE
= 25°C
T
C
120
80
100 µs
1 ms
10 ms
1.0
0.1
dc
40
0
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
1.0
10
100
25
50
75
100
125
150
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
0.2
0.1
0.05
0.1
P
(pk)
R
(t) = r(t) R
θ
JC
θ
JC
0.02
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.01
t
1
READ TIME AT t
SINGLE PULSE
1
t
2
T
− T = P
C
R (t)
θ
JC
J(pk)
(pk)
DUTY CYCLE, D = t /t
1 2
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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6
MTD6P10E
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
SEATING
PLANE
−T−
C
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
4
2
Z
A
K
S
1
3
4.58 BSC
U
0.87
0.46
2.60
1.01
0.58
2.89
K
L
2.29 BSC
F
J
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
L
H
0.020
0.035 0.050
0.155 −−−
−−−
D 2 PL
M
STYLE 2:
PIN 1. GATE
2. DRAIN
G
0.13 (0.005)
T
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
3.0
0.244
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MTD6P10E
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MTD6P10E/D
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