MAX5876EGK_技术文档

19-3634; Rev 0; 5/05

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

General Description

Features

The MAX5876 is an advanced 12-bit, 250Msps, dual

digital-to-analog converter (DAC). This DAC meets the

demanding performance requirements of signal synthesis

applications found in wireless base stations and other

communications applications. Operating from +3.3V and

+1.8V supplies, this dual DAC offers exceptional dynamic

performance such as 75dBc spurious-free dynamic range

ꢀ 250Msps Output Update Rate

ꢀ Noise Spectral Density = -154dBFS/Hz

at f = 16MHz

OUT

ꢀ Excellent SFDR and IMD

SFDR = 75dBc at f

SFDR = 71dBc at f

= 16MHz (to Nyquist)

= 80MHz (to Nyquist)

OUT

(SFDR) at f

= 16MHz and supports update rates of

OUT

IMD = -87dBc at f

IMD = -73dBc at f

= 10MHz

= 80MHz

OUT

250Msps, with a power dissipation of only 287mW.

The MAX5876 utilizes a current-steering architecture

that supports a 2mA to 20mA full-scale output current

ꢀ ACLR = 75dB at f

= 61MHz

OUT

range, and allows a 0.1V

to 1V

differential output

ꢀ 2mA to 20mA Full-Scale Output Current

ꢀ LVDS-Compatible Digital and Clock Inputs

ꢀ On-Chip +1.20V Bandgap Reference

P-P

voltage swing. The device features an integrated +1.2V

bandgap reference and control amplifier to ensure

high-accuracy and low-noise performance. A separate

reference input (REFIO) allows for the use of an exter-

nal reference source for optimum flexibility and

improved gain accuracy.

ꢀ Low 287mW Power Dissipation

ꢀ Compact 68-Pin QFN-EP Package (10mm x 10mm)

ꢀ Evaluation Kit Available (MAX5878EVKIT)

The clock inputs of the MAX5876 accept both LVDS

and LVPECL-compatible voltage levels. The device fea-

tures an interleaved data input that allows a single

LVDS bus to support both DACs. The MAX5876 is avail-

able in a 68-pin QFN package with an exposed pad

(EP) and is specified for the extended temperature

range (-40°C to +85°C).

Ordering Information

PIN-

PACKAGE

PART

TEMP RANGE

PKG CODE

MAX5876EGK -40°C to +85°C 68 QFN-EP**

**EP = Exposed pad.

G6800-4

Refer to the MAX5877 and MAX5878 data sheets for

pin-compatible 14-bit and 16-bit versions of the

MAX5876, respectively. Refer to the MAX5873 data

sheet for a CMOS-compatible version of the MAX5876.

Pin Configuration

TOP VIEW

Applications

Base Stations: Single-Carrier UMTS, CDMA, GSM

68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

Communications: Fixed Broadband Wireless Access,

Point-to-Point Microwave

Direct Digital Synthesis (DDS)

Cable Modem Termination Systems (CMTS)

Automated Test Equipment (ATE)

Instrumentation

B0N

N.C.

1

2

3

4

5

6

7

8

9

51 B8P

50 B9N

49 B9P

48 B10N

47 B10P

46 B11N

45 B11P

44 SELIQN

43 SELIQP

42 XORP

41 XORN

40 PD

MAX5876

GND 10

11

Selector Guide

DV

AV

DD3.3

GND 12

GND 13

RESOLUTION

(BITS)

UPDATE

RATE (Msps)

LOGIC

INPUTS

39 TORB

38 CLKP

37 CLKN

36 GND

PART

14

GND 15

DD3.3

MAX5873

MAX5874

MAX5875

MAX5876

MAX5877

MAX5878

12

14

16

12

14

16

200

250

CMOS

LVDS

REFIO 16

FSADJ 17

35 AV

CLK

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

QFN

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

ABSOLUTE MAXIMUM RATINGS

AV

, DV

to GND, DACREF...................-0.3V to +2.16V

Continuous Power Dissipation (T = +70°C)

68-Pin QFN-EP

DD1.8

DD3.3

DD1.8

DD3.3

A

, AV

to GND, DACREF........-0.3V to +3.9V

CLK

REFIO, FSADJ to

GND, DACREF..................................-0.3V to (AV

OUTIP, OUTIN, OUTQP,

OUTQN to GND, DACREF...................-1V to (AV

CLKP, CLKN to GND, DACREF..............-0.3V to (AV

(derate 41.7mW/°C above +70°C) (Note 1)............3333.3mW

+ 0.3V)

Thermal Resistance θ (Note 1)...................................+24°C/W

DD3.3

JA

Operating Temperature Range ......................... -40°C to +85°C

Junction Temperature .................................................... +150°C

Storage Temperature Range ........................... -60°C to +150°C

Lead Temperature (soldering, 10s) ............................... +300°C

+ 0.3V)

DD3.3

CLK

B11P/B11N–B0P/B0N, XORN, XORP, SELIQN,

SELIQP to GND, DACREF ...................-0.3V to (DV

TORB, PD to GND, DACREF...............-0.3V to (DV

+ 0.3V)

DD1.8

DD3.3

Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(AV

= DV

= AV

= +3.3V, AV

= DV

= +1.8V, GND = 0, f

= 2 x f

, external reference V

= +1.25V, out-

DD3.3

CLK

DD1.8

CLK

DAC

REFIO

put load 50Ω double-terminated, transformer-coupled output, I

= 20mA, T = T

to T , unless otherwise noted. Typical values

MAX

OUTFS

A

MIN

are at T = +25°C.) (Note 2)

A

PARAMETER

STATIC PERFORMANCE

Resolution

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

12

Bits

LSB

Integral Nonlinearity

Differential Nonlinearity

Offset Error

INL

DNL

OS

Measured differentially

0.2

0.1

Measured differentially

LSB

-0.015

-4.1

0.001 +0.015

10

%FS

Offset-Drift Tempco

Full-Scale Gain Error

ppm/°C

%FS

GE

External reference

Internal reference

External reference

(Note 3)

-0.6

100

50

+4.1

FS

Gain-Drift Tempco

ppm/°C

Full-Scale Output Current

Output Compliance

Output Resistance

I

2

20

mA

V

OUTFS

Single-ended

-0.5

+1.1

R

C

1

5

MΩ

pF

OUT

Output Capacitance

DYNAMIC PERFORMANCE

Clock Frequency

OUT

f

2

1

500

250

MHz

CLK

Output Update Rate

f

= f / 2

CLK

Msps

DAC

= 150MHz

= 250MHz

f

= 16MHz, -12dBFS

= 80MHz, -12dBFS

-154

-153

OUT

dBFS/

Hz

Noise Spectral Density

2

_______________________________________________________________________________________

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= AV

= +3.3V, AV

= DV

= +1.8V, GND = 0, f

= 2 x f

, external reference V

= +1.25V, out-

DD3.3

CLK

DD1.8

CLK

DAC

REFIO

put load 50Ω double-terminated, transformer-coupled output, I

= 20mA, T = T

to T , unless otherwise noted. Typical values

MAX

OUTFS

A

MIN

are at T = +25°C.) (Note 2)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

98

MAX

UNITS

f

= 1MHz, 0dBFS

= 1MHz, -6dBFS

OUT

88

f

= 100MHz

= 1MHz, -12dBFS

= 10MHz, -12dBFS

= 30MHz, -12dBFS

= 10MHz, -12dBFS

81

DAC

77

75

f

T

= 16MHz, -12dBFS,

OUT

67

66

75

Spurious-Free Dynamic Range

to Nyquist

≥ +25^oC

SFDR

A

dBc

f

= 200MHz

= 250MHz

DAC

f

= 16MHz, -12dBFS

= 50MHz, -12dBFS

= 80MHz, -12dBFS

= 10MHz, -12dBFS

= 50MHz, -12dBFS

= 80MHz, -12dBFS

= 100MHz, -12dBFS

75

73

71

77

73

70

68

OUT

DAC

Spurious-Free Dynamic Range,

25MHz Bandwidth

SFDR

f

= 150MHz

= 100MHz

= 200MHz

= 150MHz

=

f

= 16MHz, -12dBFS

80

-87

-73

-91

dBc

DAC

OUT

f

= 9MHz, -7dBFS;

= 10MHz, -7dBFS

OUT1

OUT2

Two-Tone IMD

TTIMD

f

= 79MHz, -7dBFS;

= 80MHz, -7dBFS

OUT1

OUT2

Four-Tone IMD, 1MHz

Frequency Spacing, GSM Model

FTIMD

ACLR

f

= 16MHz, -12dBFS

= 61.44MHz

OUT

Adjacent Channel Leakage Power

Ratio 3.84MHz Bandwidth,

W-CDMA Model

f

75

dB

184.32MHz

Output Bandwidth

BW

(Note 4)

240

MHz

-1dB

INTER-DAC CHARACTERISTICS

f

= DC - 80MHz

= DC

0.2

+0.01

20

OUT

Gain Matching

∆Gain

dB

-0.24

+0.24

OUT

Gain-Matching Tempco

Phase Matching

∆Gain/°C

∆Phase

ppm/°C

f

= 60MHz

0.25

Degrees

OUT

DAC

Degrees/

°C

Phase-Matching Tempco

∆Phase/°C f

0.002

90

Channel-to-Channel Crosstalk

REFERENCE

f

= 200Msps, f

= 50MHz, 0dBFS

dB

OUT

Internal Reference Voltage Range

V

1.14

1.2

1.26

V

REFIO

_______________________________________________________________________________________

3

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= AV

= +3.3V, AV

= DV

= +1.8V, GND = 0, f

= 2 x f

, external reference V

= +1.25V, out-

DD3.3

CLK

DD1.8

CLK

DAC

REFIO

put load 50Ω double-terminated, transformer-coupled output, I

= 20mA, T = T

to T , unless otherwise noted. Typical values

MAX

OUTFS

A

MIN

are at T = +25°C.) (Note 2)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Reference Input Compliance

Range

V

0.125

1.260

V

REFIOCR

Reference Input Resistance

Reference Voltage Drift

R

10

25

kΩ

REFIO

TCO

ppm/°C

REF

ANALOG OUTPUT TIMING (See Figure 4)

Output Fall Time

t

90% to 10% (Note 5)

0.7

1.1

1

ns

FALL

Output Rise Time

Output Propagation Delay

Glitch Impulse

t

10% to 90% (Note 5)

RISE

t

Excluding data latency (Note 5)

Measured differentially

ns

PD

pV•s

I

= 2mA

30

OUTFS

Output Noise

n

pA/√Hz

OUT

= 20mA

TIMING CHARACTERISTICS

Data to Clock Setup Time

Data to Clock Hold Time

t

Referenced to rising edge of clock (Note 6)

Latency to I output

-1.2

2.0

ns

SETUP

t

HOLD

9

Clock

Cycles

Data Latency

Latency to Q output

8

Minimum Clock Pulse-Width High

Minimum Clock Pulse-Width Low

t

CLKP, CLKN

0.9

ns

CH

t

CLKP, CLKN

CL

LVDS LOGIC INPUTS (B11P/B11N–B0P/B0N, XORN, XORP, SELIQN, SELIQP)

Differential Input-Logic High

Differential Input-Logic Low

Common-Mode Voltage Range

Differential Input Resistance

Input Capacitance

V

100

mV

V

IH

V

-100

IL

V

1.125

1.375

CMR

R

(Note 7)

110

2.5

Ω

IN

C

pF

CMOS LOGIC INPUTS (PD, TORB)

0.7 x

Input-Logic High

V

IH

DV

DD3.3

0.3 x

Input-Logic Low

V

IL

DV

DD3.3

Input Leakage Current

I

-20

1

+20

µA

MΩ

pF

IN

PD, TORB Internal Pulldown

Resistance

V

= V

= 3.3V

TORB

1.5

2.5

PD

Input Capacitance

C

IN

CLOCK INPUTS (CLKP, CLKN)

Sine wave

>1.5

>0.5

Differential Input

Voltage Swing

V

P-P

Square wave

4

_______________________________________________________________________________________

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= AV

= +3.3V, AV

= DV

= +1.8V, GND = 0, f

= 2 x f

, external reference V

= +1.25V, out-

DD3.3

CLK

DD1.8

CLK

DAC

REFIO

put load 50Ω double-terminated, transformer-coupled output, I

= 20mA, T = T

to T , unless otherwise noted. Typical values

MAX

OUTFS

A

MIN

are at T = +25°C.) (Note 2)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Differential Input Slew Rate

SR

(Note 8)

>100

V/µs

CLK

External Common-Mode Voltage

Range

AV

/ 2

CLK

0.3

V

COM

Input Resistance

R

C

5

kΩ

CLK

Input Capacitance

POWER SUPPLIES

2.5

pF

CLK

AV

DV

3.135

1.710

3.135

1.710

3.135

3.3

1.8

3.3

1.8

3.3

52

1

3.465

1.890

3.465

1.890

3.465

56

DD3.3

DD1.8

DD3.3

DD1.8

Analog Supply Voltage Range

V

Digital Supply Voltage Range

Clock Supply Voltage Range

AV

V

CLK

f

= 250Msps, f

= 16MHz

mA

µA

DAC

OUT

= DV

I

AVDD3.3 +

I

AVCLK

Power-down

= 250Msps, f

Analog Supply Current

Digital Supply Current

f

31

1

36

1

mA

µA

DAC

I

AVDD1.8

DVDD3.3

DVDD1.8

Power-down

= 250Msps, f

f

0.15

1

mA

µA

DAC

Power-down

= 250Msps, f

f

33

4

40

324

mA

µA

DAC

Power-down

= 250Msps, f

f

287

16

mW

µW

DAC

Power Dissipation

P

DISS

Power-down

AV = AV

(Notes 8, 9)

= +3.3V 5%

DD3.3

CLK

Power-Supply Rejection Ratio

PSRR

-0.1

+0.1

%FS/V

Note 2: Specifications at T ≥ +25°C are guaranteed by production testing. Specifications at T < +25°C are guaranteed by design.

A

Note 3: Nominal full-scale current I

= 32 x I

.

OUTFS

REF

Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5876.

Note 5: Parameter measured single-ended into a 50Ω termination resistor.

Note 6: Not production tested. Guaranteed by design.

Note 7: No termination resistance between XORP and XORN.

Note 8: A differential clock input slew rate of >100V/µs is required to achieve the specified dynamic performance.

Note 9: Parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage.

_______________________________________________________________________________________

5

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

Typical Operating Characteristics

(AV

= DV

= AV

= +3.3V, AV

= DV

= +1.8V, external reference, V

= +1.25V, R = 50Ω double-terminated,

DD3.3

CLK

DD1.8

REFIO

L

I

= 20mA, T = +25°C, unless otherwise noted.)

OUTFS

A

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

= 50Msps)

FREQUENCY (f

= 100Msps)

FREQUENCY (f = 150Msps)

DAC

100

80

60

40

20

0

100

80

60

40

20

0

100

-6dBFS

80

60

40

20

0

-12dBFS

0dBFS

-12dBFS

0

5

10

15

(MHz)

20

25

0

10

20

30

(MHz)

40

50

0

15

30

45

(MHz)

60

75

f

OUT

SINGLE-TONE SFDR vs. OUTPUT

TWO-TONE IMD vs. OUTPUT FREQUENCY

(1MHz CARRIER SPACING, f = 100Msps)

FREQUENCY (f

= 200Msps)

FREQUENCY (f

= 250Msps)

DAC

100

80

60

40

20

0

100

80

60

40

20

0

-70

-6dBFS

-75

0dBFS

-80

-12dBFS

-85

-90

-95

-6dBFS

20

-100

0

20

40

60

(MHz)

80

100

0

25

50

75

(MHz)

100

125

5

10

15

25

30

35

40

f

f (MHz)

OUT

6

_______________________________________________________________________________________

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

Typical Operating Characteristics (continued)

(AV

= DV

= AV

= +3.3V, AV

= DV

= +1.8V, external reference, V

= +1.25V, R = 50Ω double-terminated,

DD3.3

CLK

DD1.8

REFIO

L

I

= 20mA, T = +25°C, unless otherwise noted.)

OUTFS

A

TWO-TONE INTERMODULATION

SFDR vs. FULL-SCALE OUTPUT CURRENT

DISTORTION (f

= 100Msps)

DAC

(f

DAC

= 250Msps)

0

-20

-60

100

80

60

40

20

0

BW = 12MHz

f

= 28.7793MHz

A

= -6dBFS

T1

T2

OUT

20mA

= 30.0098MHz

-65

-70

-75

-80

-85

-90

-95

-100

f

T1

T2

-6dBFS

10mA

-40

5mA

-60

2 x f - f

T1 T2

T2 T1

-80

-12dBFS

-100

24

26

28

30

32

34

36

0

10 20 30 40 50 60 70 80

(MHz)

0

25

50

75

(MHz)

100

125

f

(MHz)

OUT

f

OUT

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE

SFDR vs. TEMPERATURE

(f = 250Msps)

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE

DAC

0.4

0.3

0.2

0.1

85

80

75

70

65

0.3

0.2

0.1

0

A

= -6dBFS

OUT

T

= +25°C

A

T

= -40°C

A

0

-0.1

-0.2

T

= +85°C

A

-0.1

-0.2

-0.3

-0.4

0

1024

2048

3072

4096

0

25

50

75

100

125

0

1024

2048

3072

4096

DIGITAL INPUT CODE

f

(MHz)

DIGITAL INPUT CODE

OUT

_______________________________________________________________________________________

7

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

Typical Operating Characteristics (continued)

(AV

= DV

= AV

= +3.3V, AV

= DV

= +1.8V, external reference, V

= +1.25V, R = 50Ω double-terminated,

DD3.3

CLK

DD1.8

REFIO

L

I

= 20mA, T = +25°C, unless otherwise noted.)

OUTFS

A

4-TONE POWER RATIO PLOT

POWER DISSIPATION vs. DAC UPDATE

RATE (f = 10MHz)

POWER DISSIPATION vs. SUPPLY VOLTAGE

(f = 100Msps, f = 10MHz)

(f

= 150MHz)

DAC

OUT

DAC

= 0dBFS

OUT

280

260

240

220

200

180

160

200

195

190

185

180

0

-20

-40

-60

-80

BW = 12MHz

A

f

A

= 0dBFS

f

T2

OUT

T3

f

T1

EXTERNAL REFERENCE

f

T4

f

T1

f

T2

f

T3

f

T4

= 29.6997MHz

= 30.7251MHz

= 31.6040MHz

= 32.4829MHz

INTERNAL REFERENCE

3.300

-100

3.465

26

28

30

32

(MHz)

34

36

38

0

50

100

150

(Msps)

200

250

3.135

f

SUPPLY VOLTAGE (V)

f

OUT

DAC

ACLR FOR W-CDMA MODULATION,

SINGLE-CARRIER ACLR

ACLR FOR W-CDMA MODULATION

TWO-CARRIER ACLR

-20

-30

-20

-30

-40

-50

-60

-70

f

= 245.76Msps

= 30.72MHz

DAC

f

= 184.32Mbps

CARRIER

ACLR = +77dB

DAC

CENTER

= 30.72MHz

ACLR = +74dB

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

1MHz

92.16MHz

3.05MHz/div

9.216MHz/div

ACLR FOR W-CDMA MODULATION,

TWO-CARRIER ACLR

W-CDMA BASEBAND ACLR

(f = 245.76Msps)

DAC

81

80

79

78

77

76

75

74

73

f

= 184.32Msps

DAC

ADJACENT

ALTERNATE

-30

-40

-50

-60

-70

-80

-90

-100

f

= 30.72MHz

CENTER

ACLR = +73dB

79.8

79.5

81.4

78.2

78.0

77.3

77.1

75.8

-110

-120

3.05MHz/div

1

2

3

4

NUMBER OF CHANNELS

8

_______________________________________________________________________________________

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

Pin Description

1

NAME

B0N

FUNCTION

Complementary Data Bit 0 (LSB)

2–9

N.C.

No Connection. Leave floating or connect to GND.

10, 12, 13, 15,

20, 23, 26, 27,

30, 33, 36

GND

Ground

Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF

capacitor to GND.

11

DV

DD3.3

14, 21, 22, 31,

32

Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with

a 0.1µF capacitor to GND.

AV

DD3.3

Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1µF

capacitor to GND. REFIO can be driven with an external reference source. See Table 1.

16

17

REFIO

FSADJ

Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-

scale output current, connect a 2kΩ resistor between FSADJ and DACREF. See Table 1.

Current-Set Resistor Return Path. Internally connected to GND. Do not use as an external

ground connection.

18

DACREF

Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a

0.1µF capacitor to GND.

19, 34

AV

DD1.8

24

25

28

29

OUTQN

OUTQP

OUTIN

OUTIP

Complementary Q-DAC Output. Negative terminal for current output.

Q-DAC Output. Positive terminal for current output.

Complementary I-DAC Output. Negative terminal for current output.

I-DAC Output. Positive terminal for current output.

Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF

capacitor to GND.

35

37

38

AV

CLK

Complementary Converter Clock Input. Negative input terminal for LVDS/LVPECL-compatible

CLKN

CLKP

differential converter clock. Internally biased to AV

/ 2.

CLK

Converter Clock Input. Positive input terminal for LVDS/LVPECL-compatible differential converter

clock. Internally biased to AV / 2.

CLK

Two’s-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two’s-

complement input format. Set TORB to a CMOS-logic-low level to indicate an offset binary input

format. TORB has an internal pulldown resistor.

39

40

41

TORB

PD

Power-Down Input. Set PD to a CMOS-logic-high level to force the DAC into power-down mode.

Set PD to a CMOS-logic-low level for normal operation. PD has an internal pulldown resistor.

Complementary LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow

the data stream to pass unchanged to the DAC input. Set XORN low and XORP high to invert the

XORN

DAC input data. If unused, connect XORN to DV

.

DD1.8

LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow the data stream to

pass unchanged to the DAC input. Set XORN low and XORP high to invert the DAC input data. If

unused, connect XORP to GND.

42

XORP

_______________________________________________________________________________________

9

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

Pin Description (continued)

NAME

FUNCTION

LVDS DAC Select Input. Set SELIQN low and SELIQP high to direct data to the I-DAC outputs.

Set SELIQP low and SELIQN high to direct data to the Q-DAC outputs.

43

SELIQP

Complementary LVDS DAC Select Input. Set SELIQN low and SELIQP high to direct data to the

I-DAC outputs. Set SELIQP low and SELIQN high to direct data to the Q-DAC outputs.

44

SELIQN

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

B11P

B11N

B10P

B10N

B9P

Data Bit 11 (MSB)

Complementary Data Bit 11 (MSB)

Data Bit 10

Complementary Data Bit 10

Data Bit 9

B9N

B8P

Complementary Data Bit 9

Data Bit 8

B8N

B7P

Complementary Data Bit 8

Data Bit 7

B7N

B6P

Complementary Data Bit 7

Data Bit 6

B6N

B5P

Complementary Data Bit 6

Data Bit 5

B5N

B4P

Complementary Data Bit 5

Data Bit 4

B4N

Complementary Data Bit 4

Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a 0.1µF

capacitor to GND.

61

DV

DD1.8

62

63

64

65

66

67

68

—

B3P

B3N

B2P

B2N

B1P

B1N

B0P

EP

Data Bit 3

Complementary Data Bit 3

Data Bit 2

Complementary Data Bit 2

Data Bit 1

Complementary Data Bit 1

Data Bit 0 (LSB)

Exposed Pad. Must be connected to GND through a low-impedance path.

10 ______________________________________________________________________________________

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

+1.2V bandgap reference, control amplifier, and user-

Detailed Description

selectable external resistor determine the data convert-

Architecture

The MAX5876 high-performance, 12-bit, dual current-

steering DAC (Figure 1) operates with DAC update rates

up to 250Msps. The converter consists of input registers

and a demultiplexer for single-port operation, followed by

a current-steering array. During operation, the input data

registers demultiplex the single-port data bus. The cur-

rent-steering array generates differential full-scale cur-

rents in the 2mA to 20mA range. An internal

current-switching network, in combination with external

50Ω termination resistors, converts the differential output

currents into dual differential output voltages with a 0.1V

to 1V peak-to-peak output voltage range. An integrated

er’s full-scale output range.

Reference Architecture and Operation

The MAX5876 supports operation with the internal

+1.2V bandgap reference or an external reference volt-

age source. REFIO serves as the input for an external,

low-impedance reference source. REFIO also serves as

a reference output when the DAC operates in internal

reference mode. For stable operation with the internal

reference, decouple REFIO to GND with a 1µF capaci-

tor. Due to its limited output drive capability, buffer

REFIO with an external amplifier when driving large

external loads.

DV

DD3.3

DV

DD1.8

AV

DD1.8

AV

DD3.3

OUTIP

OUTIN

TORB

XOR/

LATCH

DAC

SELIQP

SELIQN

DECODE

LVDS

RECEIVER

DATA11–

DATA0

LATCH

XORP

XORN

OUTQP

OUTQN

XOR/

DECODE

AV

CLK

CLKP

CLKN

DACREF

REFIO

CLK

INTERFACE

+1.2V

REFERENCE

FSADJ

MAX5876

POWER-DOWN

BLOCK

PD

GND

Figure 1. MAX5876 High-Performance, 12-Bit, Dual Current-Steering DAC

______________________________________________________________________________________ 11

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

The MAX5876’s reference circuit (Figure 2) employs a

Clock Inputs (CLKP, CLKN)

The MAX5876 features flexible differential clock inputs

(CLKP, CLKN) operating from a separate supply

control amplifier to regulate the full-scale current

I

for the differential current outputs of the DAC.

OUTFS

Calculate the full-scale output current as follows:

(AV

) to achieve optimum jitter performance. Drive

CLK

the differential clock inputs from a single-ended or a

differential clock source. For single-ended operation,

drive CLKP with a logic source and bypass CLKN to

GND with a 0.1µF capacitor.





V

R

1

REFIO

I

= 32 ×

×

1 −

OUTFS









12

2

SET

where I

DAC. R

is the full-scale output current of the

(located between FSADJ and DACREF)

determines the amplifier’s full-scale output current for

the DAC. See Table 1 for a matrix of different I

OUTFS

SET

CLKP and CLKN are internally biased to AV

/ 2. This

CLK

facilitates the AC-coupling of clock sources directly to

the device without external resistors to define the DC

level. The dynamic input resistance from CLKP and

CLKN to ground is 5kΩ.

OUTFS

and R

selections.

SET

Analog Outputs (OUTIP, OUTIN, OUTQP,

OUTQN)

Each MAX5876 DAC outputs two complementary cur-

rents (OUTIP/N, OUTQP/N) that operate in a single-

ended or differential configuration. A load resistor

converts these two output currents into complementary

single-ended output voltages. A transformer or a differ-

ential amplifier configuration converts the differential

voltage existing between OUTIP (OUTQP) and OUTIN

(OUTQN) to a single-ended voltage. If not using a

transformer, the recommended termination from the

output is a 25Ω termination resistor to ground and a

50Ω resistor between the outputs.

To generate a single-ended output, select OUTIP (or

OUTQP) as the output and connect OUTIN (or OUTQN)

to GND. SFDR degrades with single-ended operation

or increased output swing. Figure 3 displays a simpli-

fied diagram of the internal output structure of the

MAX5876.

Table 1. I

Matrix Based on a Typical +1.200V

Reference Voltage

and R

Selection

SET

OUTFS

R

(kΩ)

SET

FULL-SCALE

CURRENT I

(mA)

OUTFS

CALCULATED

1% EIA STD

2

19.2

7.68

3.84

2.56

1.92

19.1

7.5

5

10

15

20

3.83

2.55

1.91

+1.2V

REFERENCE

AV

DD

CURRENT

SOURCES

10kΩ

CURRENT

SWITCHES

REFIO

1µF

OUTIP

FSADJ

CURRENT-SOURCE

ARRAY DAC

I

REF

R

SET

I

OUT

OUTIN

DACREF

I

= V

/ R

REF

REFIO SET

OUTIN OUTIP

GND

Figure 2. Reference Architecture, Internal Reference

Configuration

Figure 3. Simplified Analog Output Structure

12 ______________________________________________________________________________________

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

CLKP-CLKN

I0

Q0

I1

Q1

I2

Q2

I3

Q3

DATA

IN

SELIQP

SELIQN

t

H

S

I0 - 3

I0 - 4

I0 - 2

I0 - 5

OUTI

I0 - 6

Q0 - 6

Q0 - 5

OUTQ

Q0 - 4

Q0 - 3

Q0 - 2

t

PD

Figure 4. Timing Diagram

Figure 5. XORP and XORN are not internally terminated.

These LVDS inputs (B11P/N–B0P/N) allow for a low differ-

ential voltage swing with low constant power consump-

tion. A 1.25V common-mode level and 250mV differential

input swing can be applied to the B11P/N–B0P/N,

XORP/N, and SELIQP/N inputs.

Data Timing Relationship

Figure 4 displays the timing relationship between digital

LVDS data, clock, and output signals. The MAX5876

features a 2.0ns hold, a -1.2ns setup, and a 1.1ns prop-

agation delay time. A nine (eight)-clock-cycle latency

exists between CLKP/CLKN and OUTIP/OUTIN

(OUTQP/OUTQN).

The MAX5876 includes LVDS-compatible exclusive-OR

inputs (XORP, XORN). Input data (all bits) is compared

with the bits applied to XORP and XORN through exclu-

sive-OR gates. Setting XORP high and XORN low inverts

the input data. Setting XORP low and XORN high leaves

the input data noninverted. By applying a previously

encoded pseudo-random bit stream to the data input

and applying decoding to XORP/XORN, the digital input

data can be decorrelated from the DAC output, allowing

for the troubleshooting of possible spurious or harmonic

distortion degradation due to digital feedthrough on the

PC board. If XOR functionality is not required, connect

LVDS-Compatible Digital Inputs

(B11P/B11N–B0P/B0N, XORP, XORN,

SELIQP, SELIQN)

The MAX5876 latches B11P/N–B0P/N, XORP/N, and

SELIQP/N data on the rising edge of the clock. A logic-

high signal on SELIQP and a logic-low signal on

SELIQN directs data onto the I-DAC inputs. A logic-low

signal on SELIQP and a logic-high signal on SELIQN

directs data onto the Q-DAC inputs.

The MAX5876 features LVDS receivers on the bus input

interface with internal 110Ω termination resistors. See

XORP to GND and XORN to DV

.

DD1.8

______________________________________________________________________________________ 13

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

Table 2. DAC Output Code Table

DIGITAL INPUT CODE

OUT_P

OUT_N

OFFSET BINARY

0000 0000 0000

0111 1111 1111

1111 1111 1111

TWO’S COMPLEMENT

1000 0000 0000

0

I

OUTFS

0000 0000 0000

I

/ 2

I

/ 2

OUTFS

0

0111 1111 1111

I

OUTFS

CMOS-Compatible Digital Inputs

Applications Information

Input Data Format Select (TORB)

The TORB input selects between two’s-complement or

offset binary digital input data. Set TORB to a CMOS-

logic-high level to indicate a two’s-complement input for-

mat. Set TORB to a CMOS-logic-low level to indicate an

offset binary input format.

CLK Interface

The MAX5876 features a flexible differential clock input

(CLKP, CLKN) with a separate supply (AV

) to

CLK

achieve optimum jitter performance. Use an ultra-low

jitter clock to achieve the required noise density. Clock

jitter must be less than 0.5ps

for meeting the speci-

RMS

fied noise density. For that reason, the CLKP/CLKN

input source must be designed carefully. The differen-

tial clock (CLKN and CLKP) input can be driven from a

single-ended or a differential clock source. Differential

clock drive is required to achieve the best dynamic

performance from the DAC. For single-ended opera-

tion, drive CLKP with a low noise source and bypass

CLKN to GND with a 0.1µF capacitor.

Power-Down Operation (PD)

The MAX5876 also features an active-high power-down

mode that reduces the DAC’s digital current consump-

tion from 33mA to less than 5µA and the analog current

consumption from 83mA to less than 2µA. Set PD high

to power down the MAX5876. Set PD low for normal

operation.

When powered down, the MAX5876 reduces the overall

power consumption to less than 16µW. The MAX5876

requires 10ms to wake up from power-down and enter

a fully operational state. The PD integrated pulldown

resistor activates the MAX5876 if PD is left floating.

Figure 6 shows a convenient and quick way to apply a

differential signal created from a single-ended source

(e.g., HP 8662A signal generator) and a wideband trans-

former. Alternatively, these inputs can be driven from a

CMOS-compatible clock source; however, it is recom-

mended to use sinewave or AC-coupled differential

ECL/PECL or LVDS drive for best dynamic performance.

WIDEBAND RF TRANSFORMER

0.1µF

PERFORMS SINGLE-ENDED-TO-

CLKP

DIFFERENTIAL CONVERSION

25Ω

B11P–B0P,

D

Q

TO DAC

1:1

SINGLE-ENDED

CLOCK SOURCE

(e.g., HP 8662A)

SELIQP

TO

DECODE

LOGIC

110Ω

25Ω

0.1µF

B11N–B0N,

SELIQN

CLKN

MAX5876

CLOCK

GND

Figure 5. Simplified LVDS-Compatible Digital Input Structure

Figure 6. Differential Clock-Signal Generation

14 ______________________________________________________________________________________

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

Differential-to-Single-Ended Conversion

Using a Wideband RF Transformer

Grounding, Bypassing, and Power-

Supply Considerations

Use a pair of transformers (Figure 7) or a differential

amplifier configuration to convert the differential voltage

existing between OUTIP/OUTQP and OUTIN/OUTQN to

a single-ended voltage. Optimize the dynamic perfor-

mance by using a differential transformer-coupled out-

put and limit the output power to <0dBm full scale. Pay

close attention to the transformer core saturation char-

acteristics when selecting a transformer for the

MAX5876. Transformer core saturation can introduce

strong 2nd-order harmonic distortion especially at low

output frequencies and high signal amplitudes. For best

results, center tap the transformer to ground. When not

using a transformer, terminate each DAC output to

ground with a 25Ω resistor. Additionally, place a 50Ω

resistor between the outputs (Figure 8).

Grounding and power-supply decoupling can strongly

influence the MAX5876 performance. Unwanted digital

crosstalk couples through the input, reference, power

supply, and ground connections, and affects dynamic

performance. High-speed, high-frequency applications

require closely followed proper grounding and power-

supply decoupling. These techniques reduce EMI and

internal crosstalk that can significantly affect the

MAX5876 dynamic performance.

Use a multilayer printed circuit (PC) board with sepa-

rate ground and power-supply planes. Run high-speed

signals on lines directly above the ground plane. Keep

digital signals as far away from sensitive analog inputs

and outputs, reference input sense lines, and clock

inputs as practical. Use a controlled-impedance, sym-

metric, differential design of clock input and the analog

output lines to minimize 2nd-order harmonic distortion

components, thus optimizing the DAC’s dynamic per-

formance. Keep digital signal paths short and run

lengths matched to avoid propagation delay and data

skew mismatches.

For a single-ended unipolar output, select OUTIP

(OUTQP) as the output and ground OUTIN (OUTQN).

Driving the MAX5876 single-ended is not recommended

since additional noise and distortion will be added.

The distortion performance of the DAC depends on the

load impedance. The MAX5876 is optimized for 50Ω

differential double termination. It can be used with a

transformer output as shown in Figure 7 or just one 25Ω

resistor from each output to ground and one 50Ω resis-

tor between the outputs (Figure 8). This produces a full-

scale output power of up to -2dBm, depending on the

output current setting. Higher termination impedance

can be used at the cost of degraded distortion perfor-

mance and increased output noise voltage.

The MAX5876 requires five separate power-supply inputs

for analog (AV

and AV

), digital (DV

and

DD1.8

), and clock (AV

DD3.3

DD1.8

DV

) circuitry. All power-supply

DD3.3

CLK

pins must be connected to their proper supply. Decouple

each AV , DV , and AV input pin with a separate

DD

CLK

0.1µF capacitor as close to the device as possible with

the shortest possible connection to the ground plane

(Figure 9). Minimize the analog and digital load capaci-

tances for optimized operation. Decouple all three power-

supply voltages at the point they enter the PC board with

50Ω

V

OUT

, SINGLE-ENDED

T2, 1:1

OUTIP/OUTQP

OUTIN/OUTQN

DATA11–DATA0

100Ω

50Ω

MAX5876

12

T1, 1:1

GND

WIDEBAND RF TRANSFORMER T2 PERFORMS THE

DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION

Figure 7. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer

______________________________________________________________________________________ 15

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

tantalum or electrolytic capacitors. Ferrite beads with

additional decoupling capacitors forming a pi-network

could also improve performance.

spread heat. Use as many vias as possible to the ground

plane to minimize inductance.

Static Performance Parameter Definitions

The analog and digital power-supply inputs AV

,

DD3.3

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an

actual transfer function from either a best straight-line fit

(closest approximation to the actual transfer curve) or a

line drawn between the end points of the transfer func-

tion, once offset and gain errors have been nullified.

For a DAC, the deviations are measured at every indi-

vidual step.

AV

, and DV

allow a +3.135V to +3.465V sup-

CLK

DD3.3

ply voltage range. The analog and digital power-supply

inputs AV and DV allow a +1.71V to +1.89V

DD1.8

supply voltage range.

The MAX5876 is packaged in a 68-pin QFN-EP pack-

age, providing greater design flexibility, and optimized

DAC AC performance. The EP enables the use of nec-

essary grounding techniques to ensure highest perfor-

mance operation. Thermal efficiency is not the key

factor, since the MAX5876 features low-power opera-

tion. The exposed pad ensures a minimum inductance

ground connection between the DAC and the PC

board’s ground layer.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an

actual step height and the ideal value of 1 LSB. A DNL

error specification of less than 1 LSB guarantees a

monotonic transfer function.

Offset Error

The offset error is the difference between the ideal and

the actual offset current. For a DAC, the offset point is

the average value at the output for the two midscale

digital input codes with respect to the full scale of the

DAC. This error affects all codes by the same amount.

The data converter die attaches to an EP lead frame with

the back of this frame exposed at the package bottom

surface, facing the PC board side of the package. This

allows for a solid attachment of the package to the PC

board with standard infrared reflow (IR) soldering tech-

niques. A specially created land pattern on the PC board,

matching the size of the EP (6mm x 6mm), ensures the

proper attachment and grounding of the DAC (refer to the

MAX5878 EV kit data sheet). Designing vias into the land

area and implementing large ground planes in the PC

board design allow for the highest performance operation

of the DAC. Use an array of at least 4 x 4 vias (≤0.3mm

diameter per via hole and 1.2mm pitch between via

holes) for this 68-pin QFN-EP package. Connect the

MAX5876 exposed paddle to GND. Vias connect the

land pattern to internal or external copper planes to

Gain Error

A gain error is the difference between the ideal and the

actual full-scale output voltage on the transfer curve,

BYPASSING—DAC LEVEL

AV

DD1.8

AV

DD3.3

AV

CLK

0.1µF

OUTIP/OUTQP

DATA11–DATA0

MAX5876

25Ω

12

OUTIP/OUTQP

OUTIN/OUTQN

DATA11–DATA0

OUTP

OUTN

50Ω

25Ω

MAX5876

0.1µF

12

OUTIN/OUTQN

GND

DV

DD1.8

DV

DD3.3

*BYPASS EACH POWER-SUPPLY PIN INDIVIDUALLY.

Figure 9. Recommended Power-Supply Decoupling and

Bypassing Circuitry

Figure 8. Differential Output Configuration

16 ______________________________________________________________________________________

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

after nullifying the offset error. This error alters the slope

of the transfer function and corresponds to the same

percentage error in each step.

Two-/Four-Tone Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in dBc (or dBFS)

of the worst 3rd-order (or higher) IMD product(s) to either

output tone; 2nd-order IMD products usually fall at fre-

quencies that digital filtering easily removes. Therefore,

they are not as critical as 3rd-order IMDs. The two-tone

IMD performance of the MAX5876 is tested with the two

individual output tone levels set to at least -6dBFS and

the four-tone performance was tested according to the

GSM model at an output frequency of 16MHz and ampli-

tude of -12dBFS.

Dynamic Performance Parameter Definitions

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital sam-

ples, the theoretical maximum SNR is the ratio of the full-

scale analog output (RMS value) to the RMS quantization

error (residual error). The ideal, theoretical minimum can

be derived from the DAC’s resolution (N bits):

SNR = 6.02 x N + 1.76

dB

Adjacent Channel Leakage Power Ratio (ACLR)

Commonly used in combination with wideband code-

division multiple-access (W-CDMA), ACLR reflects the

leakage power ratio in dB between the measured

power within a channel relative to its adjacent channel.

ACLR provides a quantifiable method of determining

out-of-band spectral energy and its influence on an

adjacent channel when a bandwidth-limited RF signal

passes through a nonlinear device.

However, noise sources such as thermal noise, reference

noise, clock jitter, etc., affect the ideal reading; therefore,

SNR is computed by taking the ratio of the RMS signal to

the RMS noise, which includes all spectral components

minus the fundamental, the first four harmonics, and the

DC offset.

Noise Spectral Density

The DAC output noise floor is the sum of the quantiza-

tion noise and the output amplifier noise (thermal and

shot noise). Noise spectral density is the noise power in

1Hz bandwidth, specified in dBFS/Hz.

Settling Time

The settling time is the amount of time required from the

start of a transition until the DAC output settles its new

output value to within the converter’s specified accuracy.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of RMS amplitude of the carrier fre-

quency (maximum signal components) to the RMS

value of their next-largest distortion component. SFDR

is usually measured in dBc and with respect to the car-

rier frequency amplitude or in dBFS with respect to the

DAC’s full-scale range. Depending on its test condition,

SFDR is observed within a predefined window or to

Nyquist.

Glitch Impulse

A glitch is generated when a DAC switches between

two codes. The largest glitch is usually generated

around the midscale transition, when the input pattern

transitions from 011...111 to 100...000. The glitch

impulse is found by integrating the voltage of the glitch

at the midscale transition over time. The glitch impulse

is usually specified in pV•s.

______________________________________________________________________________________ 17

12-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)

PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM

1

21-0122

C

2

PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM

1

21-0122

C

2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX5876EGK
厂家：	Rochester Electronics
描述：	PARALLEL, WORD INPUT LOADING, 12-BIT DAC, QCC68, 10 X10 MM, MO-220, QFN-68 输入元件转换器
文件：	总19页 (文件大小：1070K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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