MAX498CWI-T [ROCHESTER]
QUAD 1-CHANNEL, AUDIO/VIDEO SWITCH, PDSO28, 0.300 INCH, SOP-28;
| 型号： | MAX498CWI-T |
| 厂家： | 
Rochester Electronics |
| 描述： | QUAD 1-CHANNEL, AUDIO/VIDEO SWITCH, PDSO28, 0.300 INCH, SOP-28 光电二极管 |
| 文件： | 总17页 (文件大小：837K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1143; Rev 0; 10/96
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
8/MAX49
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MAX498/MAX499 are high-speed, quad/triple, sin-
gle-pole/double-throw video switches with on-board
closed-loop buffer amplifiers. The buffer amplifiers fea-
♦ High Speed:
250MHz Small-Signal -3dB Bandwidth
135MHz Full-Power -3dB Bandwidth
ture +6dB gain (A
= 2V/V), 250MHz -3dB band-
VCL
♦ 70MHz 0.1dB Gain Flatness
width, 70MHz 0.1dB gain flatness, and 1250V/µs slew
rate. Fast switching time (3ns) and fast settling time
(12ns for a 4V s te p ) ma ke the s e d e vic e s e xc e lle nt
choices for a wide variety of video applications. The low
differential gain/phase errors (0.03%/0.06°) and wide
bandwidth make them ideal for both composite-video
and RGB applications. The amplifiers are capable of
d e live ring ± 2.5V into b a c k-te rmina te d 50Ω or 75Ω
cables, and they deliver ±2V to a 75Ω load, allowing
multiple cables to be driven from a single output.
♦ 1250V/µs Slew Rate
♦ 12ns to 0.1% Settling Time
♦ 0.03°/0.06% Differential Phase/Gain Error
♦ 2pF Input Capacitance
♦ 3ns Channel-Switching Time
♦ 120mVp-p Channel-Switching Transient
♦ Three-State Output Allows Large Switch Arrays
For implementation of large switch arrays, a low-power
disable mode places the amplifier outputs in a high-
imp e d a nc e s ta te . Cha nne l s e le c tion a nd outp ut
e na b le /d is a b le a re c ontrolle d b y four TTL/CMOS-
compatible logic inputs. Each video input is isolated by
an AC-ground pin, which minimizes channel-to-channel
capacitance and reduces crosstalk to 90dB at 10MHz.
♦ Directly Drives 50Ω or 75Ω Back-Terminated
Cables
______________Ord e rin g In fo rm a t io n
The four-channel MAX498 dissipates 390mW (typical)
from ±5VDC power supplies with all output buffers
enabled. Power consumption is reduced to 130mW with
all buffers disabled. The corresponding dissipation for
the thre e -c ha nne l MAX499 is 300mW e na b le d a nd
100mW disabled.
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
28 SO
MAX498CWI
MAX499CWG
24 SO
________________________Ap p lic a t io n s
_________________P in Co n fig u ra t io n s
Video Switching and Routing
Broadcast-Quality Composite-Video Multiplexing
Workstations
TOP VIEW
24 GND
IN1A
GND
IN2A
GND
1
2
3
4
5
6
7
8
9
23
22
21
20
LE
Video Editing
EN
A0
Broadcast and High-Definition TV Systems
Multimedia Products
MAX499
IN3A
CS
Medical Imaging
V
CC
OUT1
19
18
17
16
15
14
V
EE
V
CC
IN1B
GND
V
EE
OUT2
N.C.
IN2B 10
GND 11
OUT3
IN3B
13 N.C.
12
SO
MAX498 appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V to V )................................................+12V
Continuous Power Dissipation (T = +70°C)
A
CC
EE
Voltage on IN__ to GND ..................(V - 0.3V) to (V + 0.3V)
Voltage on Digital Inputs
24-Pin SO (derate 11.76mW/°C above +70°C).............941mW
28-Pin SO (derate 12.5mW/°C above +70°C)......................1W
Operating Temperature Range .................................0°C to +70°
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
EE
CC
(LE, EN, A0, CS).........................................-0.3V to (V + 0.3V)
CC
Voltage on OUT_ (disabled) ..................................................±4V
Output Short-Circuit Duration
to -4V ≤ OUT_ ≤ +4V ..................................................Continuous
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V = +5V, V = -5V, V _ _ = 0V, R = 150Ω, LE = EN = CS = 0V, T = 0°C to +70°C, unless otherwise noted. Typical values are at
CC
EE
IN
L
A
T
A
= +25°C.)
8/MAX49
PARAMETER
SYMBOL
CONDITIONS
MIN
±1.25
1.985
1.965
TYP
MAX
UNITS
Input Voltage Range
V
IN
±1.70
V
R
R
= 150Ω, -1.25V ≤ V ≤ +1.25V
2.030
2.030
±9
L
L
IN
Voltage Gain
A
V
V/V
= 75Ω, -1.0V ≤ V ≤ +1.0V
IN
Input Offset Voltage
V
OS
±2
±50
±1
mV
µV/°C
µA
kΩ
pF
Input Offset Voltage Drift
Input Bias Current
TCV
OS
I
B
±7
Input Resistance
R
C
-1.25V ≤ V ≤ +1.25V
200
±27
700
2
IN
IN
IN
Input Capacitance
Channel on or off
Output Short-Circuit Current
Output Current
I
-3.5V ≤ OUT_ ≤ +3.5V (Note 1)
120
±40
0.15
3.0
1.2
mA
mA
Ω
OUT(SC)
-2.0V ≤ V
≤ +2.0V, R = 75Ω
I
OUT_
L
OUT_
On Output Resistance
On Output Impedance
Off Output Resistance
Operating Supply-Voltage Range
Positive Power-Supply Rejection
R
OUT
f = 10MHz
-2.50V ≤ V
Ω
≤ +2.50V
1.0
±4.50
55
kΩ
V
OUT
±5.50
PSR+
PSR-
4.50V ≤ V ≤ 5.50V, V = -5.0V
72
72
dB
CC
EE
Negative Power-Supply
Rejection
-5.50V ≤ V ≤ -4.5V, V = +5.0V
55
dB
EE
CC
Logic Low Voltage
Logic High Voltage
Logic Input Current
V
0.8
V
V
INLL
V
INLH
2
130
52
41
17
14
50
39
15
12
I
0V ≤ V ≤ V
CC
-10
µA
INL
INL
MAX498
MAX499
MAX498
MAX499
MAX498
MAX499
MAX498
MAX499
40
31
14
11
38
29
12
9
EN = 0
Positive Supply Current
Negative Supply Current
I
mA
mA
CC
EN = 1
EN = 0
EN = 1
I
EE
Note 1: Limited by package power dissipation.
_______________________________________________________________________________________
2
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
8/MAX49
AC ELECTRICAL CHARACTERISTICS
(V = +5V, V = -5V, V
= 0V, R = 100Ω, LE = EN = CS = 0V, T = +25°C, unless otherwise noted.)
CC
EE
IN__
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
250
70
MAX
UNITS
MHz
MHz
MHz
V/µs
ns
Small-Signal, -3dB Bandwidth
±0.1dB Gain Flatness
Full-Power, -3dB Bandwidth
Slew Rate
BW
V
≤ 100mVp-p
≤ 100mVp-p
-3dB
IN
V
IN
FPBW
SR
V
OUT
= ±2V
135
1250
12
V
OUT
= 4V step
Settling Time
t
s
0.1%, V
= 4V step
OUT
Input Voltage Noise Density
Input Current Noise Density
Total Harmonic Distortion
Spurious-Free Dynamic Range
Adjacent-Channel Crosstalk
All-Hostile Crosstalk
Off-Isolation
f = 100kHz
f = 100kHz
f = 10MHz
7.8
2.6
-50
-66
90
nV/√Hz
pA/√Hz
dB
THD
SFDR
f
C
= 3MHz
dBc
f = 10MHz (Note 2)
dB
f = 10MHz (Note 3)
62
dB
81
dB
EN = 1, f = 10MHz (Note 4)
f = 3.58MHz (Note 5), R = 150Ω
Differential Gain
Diff Gain
0.03
0.06
%
L
f = 3.58MHz (Note 5), R = 150Ω
Differential Phase
Diff Phase
degrees
L
TIMING CHARACTERISTICS
(V = +5V, V = -5V, V
= 0V, R = 150Ω, LE = EN = CS = 0V, T = 0°C to +70°C. Typical values are at T = +25°C, unless
CC
EE
IN_ _
L
A
A
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
t
LE = high (Note 6)
8
A0/EN to CS Setup Time
A0/EN to CS Hold Time
CS Pulse Width
SU
t
LE = high (Note 6)
(Note 6)
4
ns
H
t
CS
15
ns
Channel-Switching
Propagation Delay
t
(Note 7)
(Note 8)
20
ns
ns
PD
Channel-Switching Time
t
3
70
50
10
150
16
24
SW
Positive
Negative
Positive
Negative
Channel-Switching Transient
V
INA
= V
= 0V
= 0V
mV
INB
Enable/Disable Switching
Transient
V
INA
= V
mV
INB
Amplifier-Disable Time
Amplifier-Enable Time
t
(Note 9)
(Note 10)
ns
ns
OFF
t
ON
Note 2: Test-channel input grounded through a 50Ω resistor. Adjacent channel driven to a 2Vp-p output with a 10MHz sine wave
(Figure 9).
Note 3: Same as Note 2, except all channels but the test channel are driven to a 2Vp-p output with a 10MHz sine wave (Figure 9).
Note 4: Test-channel input connected to a 2V
sine wave at 10MHz. The test channel’s output is measured with the outputs
p-p
disabled (Figure 9).
Note 5: Input test signal is a 3.58MHz sine wave of 40IRE amplitude, superimposed on a 0IRE to 100IRE linear ramp (Figure 10).
Note 6: Guaranteed by design.
Note 7:
Note 8:
V
V
INA
= +1V, V
= -1V, delay from CS to 10% of V
= -1V, delay from CS to 10% of V
INA
INB OUT.
= +1V, V
INB OUT.
Note 9: Delay from EN to 90% of V
OUT.
Note 10: Delay from EN to 10% of V
OUT.
_______________________________________________________________________________________
3
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V, V = -5V, R = 100Ω, T = +25°C, unless otherwise noted.)
CC
EE
L
A
SMALL-SIGNAL GAIN
vs. FREQUENCY
GAIN FLATNESS
vs. FREQUENCY
LARGE-SIGNAL GAIN
vs. FREQUENCY
8
7
6
5
6.2
6.1
6.0
5.9
8
7
V
IN
= 20mVp-p
V
IN
= 20mVp-p
V
OUT
= 2Vp-p
6
5
4
3
2
1
0
4
3
5.8
5.7
5.6
5.5
5.4
5.3
2
1
8/MAX49
0
-1
1M
10M
100M
1G
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
OUTPUT IMPEDANCE
vs. FREQUENCY
LARGE-SIGNAL GAIN
vs. FREQUENCY
LARGE-SIGNAL GAIN
vs. FREQUENCY
1000
8
7
0.14
0.10
R
V
OUT
= 50Ω
= 2Vp-p
L
V
OUT
= 2Vp-p
100
10
1
OUT0–OUT1
OUT0–OUT3
6
5
4
3
2
1
0
0.06
0.02
-0.02
-0.06
0.1
OUT0–OUT2
0.01
-0.10
10k
100k
1M
10M
100M
1M
10M
100M
500M
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
OFF-ISOLATION
vs. FREQUENCY
POWER-SUPPLY REJECTION
vs. FREQUENCY
CROSSTALK
vs. FREQUENCY
-20
-15
20
0
V
OUT
= 2Vp-p
-30
-25
-35
-45
-55
-65
-75
-85
-95
-40
-50
-20
-40
PSR-
ALL HOSTILE
-60
-60
ADJACENT
-70
-80
PSR+
-80
-100
-120
-140
-90
-100
1M
10M
100M
1G
30k 0.1M
1M
10M
100M
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
4
_______________________________________________________________________________________
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
8/MAX49
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V, V = -5V, R = 100Ω, T = +25°C, unless otherwise noted.)
CC
EE
L
A
MAX498
SUPPLY CURRENT
vs. TEMPERATURE
DISABLED SUPPLY CURRENT
vs. TEMPERATURE
GAIN vs. TEMPERATURE
50
2.0200
2.0175
2.0150
15
14
EN = HIGH (OUTPUTS DISABLED)
45
40
35
30
13
12
V
IN
= +1V
I
CC
I
CC
V
IN
= -1V
11
I
EE
I
EE
10
9
2.0125
2.0100
8
-55 -35 -15
5
25
45
65
85
-55 -35 -15
5
25
45
65 85
-55 -35 -15
5
25 45
65
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE
vs. TEMPERATURE
INPUT BIAS CURRENT
vs. TEMPERATURE
12
10
8
10
8
6
6
4
4
2
2
0
0
-2
-4
-6
-8
-2
-4
-6
-8
-10
-12
-10
-55 -35 -15
5
25 45
65
85
-55 -35 -15
5
25 45
65
85
TEMPERATURE (°C)
TEMPERATURE (°C)
LARGE-SIGNAL
LARGE-SIGNAL
LARGE-SIGNAL
PULSE RESPONSE (C = 47pF)
L
PULSE RESPONSE
PULSE RESPONSE (C = 100pF)
L
+1
0
+1
0
+1
0
IN
IN
IN
-1
-1
-1
+2
0
+2
0
+2
0
OUT
OUT
OUT
-2
-2
-2
TIME (10ns/div)
TIME (10ns/div)
TIME (10ns/div)
_______________________________________________________________________________________
5
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V, V = -5V, R = 100Ω, T = +25°C, unless otherwise noted.)
CC
EE
L
A
SMALL-SIGNAL
PULSE RESPONSE (C = 100pF)
L
SMALL-SIGNAL
PULSE RESPONSE
SMALL-SIGNAL
PULSE RESPONSE (C = 47pF)
L
+100
+100
0
+100
0
IN
0
IN
IN
-100
-100
-100
+200
0
+200
0
+200
0
OUT
OUT
OUT
-200
-200
-200
TIME (10ns/div)
TIME (10ns/div)
X
TIME (10ns/div)
ENABLE/DISABLE
SWITCHING
CHANNEL-SWITCHING
TRANSIENT
CHANNEL SWITCHING
+5
0
A0
+2
+2
OUT
OUT_
A0
0
-2
0
+100m
+5
+5
OUT_
0
ENABLE
-100m
0
0
TIME (10ns/div)
TIME (50ns/div)
TIME (10ns/div)
IN_A = -1V
IN_B = +1V
ENABLE/DISABLE
BANDWIDTH
SWITCHING TRANSIENT
vs. INPUT VOLTAGE
300
280
260
240
+5
0
ENABLE
+100m
220
200
180
160
140
120
OUT_
0
-100m
TIME 50ns/div
0.01
0.1
1
10
INPUT VOLTAGE (Vp-p)
6
_______________________________________________________________________________________
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
8/MAX49
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
MAX498 MAX499
1, 3, 5,
2, 4, 9,
11, 13,
11, 24
19
Analog Ground. All ground pins are internally connected. Connect all ground pins externally to
ground to minimize impedance.
GND
2
4
6
1
3
5
IN1A
IN2A
IN3A
Signal Input 1, Channel A
Signal Input 2, Channel A
Signal Input 3, Channel A
Positive Power-Supply Voltage. Connect V to +5V. V pins are internally connected.
CC
CC
7, 22
8
6, 18
—
V
Connect both pins externally to +5V to minimize supply impedance. Bypass each pin to
ground with a 0.1µF ceramic capacitor.
CC
IN0B
Signal Input 0, Channel B
Negative Power-Supply Voltage. Connect V to -5V. V pins are internally connected.
EE
EE
9, 21
7, 17
V
EE
Connect both pins to -5V externally to minimize supply impedance. Bypass each pin to
ground with a 0.1µF ceramic capacitor.
10
12
8
10
IN1B
IN2B
IN3B
N.C.
Signal Input 1, Channel B
Signal Input 2, Channel B
14
12
Signal Input 3, Channel B
15, 17
16
13, 15
14
No Connect. Not internally connected; connect to GND.
OUT3
OUT2
OUT1
OUT0
Output 3
Output 2
Output 1
Output 0
18
16
20
19
23
—
Chip-Select Input. When CS is low, the A0 and EN latches are transparent. The data present at A0
is latched when CS goes high. LE’s status determines whether EN is latched along with A0, or if the
EN latch remains transparent independently of CS.
24
25
26
20
21
22
CS
A0
EN
Address Input. A0 = 0 selects channel A, and A0 = 1 selects channel B if CS is low. A0 is
latched on CS’s low-to-high transition.
Output Buffer-Enable Input. EN = 0 enables the output buffer amplifiers, and EN = 1 disables
the output buffers if CS is low. EN is latched during CS’s low-to-high transition if LE is high. EN
is not latched if LE is low.
Latch-Enable Input. With LE = 1, EN is latched along with A0 when CS goes high. When LE = 0,
the EN latch is transparent independently of CS’s state.
27
28
23
—
LE
IN0A
Signal Input 0, Channel A
_______________________________________________________________________________________
7
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
1
2
3
28
27
26
25
24
23
22
21
GND
IN1A
GND
IN0A
LE
EN
4
5
IN2A
GND
A0
CS
8/MAX49
MAX498
6
OUT0
IN3A
7
8
+5V
DC
+5V
DC
V
CC
V
CC
10µF
0.1µF
0.1µF
0.1µF
IN0B
V
EE
-5V
DC
9
20
19
18
-5V
DC
OUT1
GND
OUT2
N.C.
V
EE
10µF
0.1µF
10
11
12
13
IN1B
GND
17
16
15
IN2B
GND
OUT3
N.C.
14
IN3B
EIGHT-IN/FOUR-OUT
VIDEO MUX AMP
NOTE: ALL RESISTORS ARE 50Ω OR 75Ω
Figure 1a. MAX498 Typical Application Circuit
_______________________________________________________________________________________
8
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
8/MAX49
24
23
22
21
20
1
2
3
IN1A
GND
GND
LE
EN
IN2A
GND
IN3A
4
5
A0
CS
MAX499
6
19
+5V
DC
OUT1
V
CC
10µF
0.1µF
0.1µF
7
8
18
17
+5V
DC
+5V
DC
V
V
EE
CC
10µF
0.1µF
0.1µF
IN1B
GND
V
EE
-5V
DC
16
15
14
9
10
11
12
OUT2
N.C.
IN2B
GND
OUT3
N.C.
13
IN3B
SIX-IN/THREE-OUT
VIDEO MUX AMP
NOTE: ALL RESISTORS ARE 50Ω OR 75Ω
Figure 1b. MAX499 Typical Application Circuit
_______________________________________________________________________________________
9
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
______________ De t a ile d De s c rip t io n
The MAX498/MAX499 are quad/triple video switches
with high-speed, closed-loop, voltage-feedback ampli-
fiers set to a 2V/V gain. Figure 1 shows typical applica-
tion circuits. The amplifiers use a unique two-stage,
IN0A
MAX498
MAX499
GM_A
S1
CHANNEL 0
voltage-feedback architecture that combines the bene-
fits of c onve ntiona l volta g e -fe e d b a c k a nd c urre nt-
X1
OUT0
C
C
feedback topologies to achieve wide bandwidths and
high slew rates while maintaining precision.
R
0
IN0B
Figure 2 is a simplified block diagram of the MAX498/
MAX499. All four amplifier/switch blocks are identical to
that shown for Ch_0. A common control logic block
a c c e p ts e xte rna l log ic inp uts A0, EN, CS, a nd LE,
and controls the status of switches S1, S2, and S3 of
each amplifier in parallel, as described in the Digital
Interface section.
GM_B
S2
X1
S3
R
FB
R
G
8/MAX49
S3 is open in the enabled state, and if Ch_A is select-
ed, S1 is connected to IN_A and S2 is connected to
GND. If Ch_B is selected, S1 is connected to GND and
S2 is connected to IN_B. Connecting the deselected
GM_ block to GND ensures minimum feedthrough.
CHANNEL 1
CHANNEL 2
CHANNEL 3
S3 is closed in the disabled state, and both S1 and S2
are connected to GND. Disconnecting both inputs and
connecting the amplifier’s inputs to GND significantly
improves off-isolation.
S1
S2
S3
A0
EN
CS
LE
__________Ap p lic a t io n s In fo rm a t io n
CONTROL LOGIC
P o w e r Dis s ip a t io n
The MAX498/MAX499’s maximum output current is limit-
ed by the package ’s maximum allowable power dissi-
pation. The maximum junction temperature should not
exceed +150°C. Power dissipation increases with load,
and this increase can be approximated by one of the
following equations:
Figure 2. Block Diagram
To t a l No is e
The MAX498/MAX499’s low 2.6pA/√Hz input current
noise and 7.8nV/√Hz voltage noise provide for lower
total noise compared to typical current-mode feedback
amplifiers, which usually have significantly higher input
current noise. The input current noise multiplied by the
feedback resistor is the dominant noise source of cur-
rent-mode feedback amplifiers.
For V
> 0V: |V - VOUT| I
OUT
CC
LOAD
OR
For V
< 0V: |V - VOUT| I
.
OUT
EE
LOAD
These devices can drive 100Ω loads connected to
each of the outputs over the entire rated output swing
and temperature range. While the output is short-circuit
protected to 120mA, this does not necessarily guaran-
tee that under all conditions, the maximum junction
temperature will not be exceeded. Do not exceed the
derating values given in the Absolute Maximum Ratings
section.
Diffe re n t ia l Ga in a n d P h a s e Erro rs
Differential gain and phase errors are critical specifica-
tions for a buffer in composite (NTSC, PAL, SECAM) video
applications, because these errors correspond directly to
color changes in the displayed picture of composite video
systems. The MAX498/MAX499’s low differential gain and
phase errors (0.03%/0.06°) make them ideal in broadcast-
quality, composite video applications.
10 ______________________________________________________________________________________
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
8/MAX49
FULL POWER-DOWN
FULL POWER-DOWN
14
12
10
8
14
12
10
8
R
ISO
= 0Ω
R
ISO
= 6.8Ω
100pF
47pF
100pF
150pF
47pF
6
6
0pF
0pF
4
4
2
2
0
0
-2
-4
-6
-2
-4
-6
1M
10M
100M
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 3a. Small-Signal Gain vs. Frequency and Load
Figure 3b. Small-Signal Gain vs. Frequency and Load
Capacitor (R = 100Ω, R
= 0Ω)
Capacitor (R = 100Ω, R
= 6.8Ω)
L
ISO
L
ISO
+1
+100
V
IN
V
IN
-1
-100
+2
+200
V
OUT
V
OUT
-200
-2
TIME (10ns/div)
TIME (10ns/div)
Figure 4b. Small-Signal Pulse Response with C = 100pF and
Figure 4a. Large-Signal Pulse Response with C = 100pF and
L
L
R
= 5.1Ω
R
= 5.1Ω
ISO
ISO
Co a x ia l Ca b le Drive rs
Ca p a c it ive -Lo a d Drivin g
Hig h-s p e e d p e rforma nc e , e xc e lle nt outp ut c urre nt
capability, and an internally fixed gain of +2 make the
MAX498/MAX499 ideal for driving back-terminated 50Ω
or 75Ω coaxial cables to ±2.5V.
In most amplifier circuits, driving large capacitive loads
increases the likelihood of oscillation. This is especially
true for circuits with high loop gains, such as voltage
followers. The amplifier’s output resistance and the
capacitive load form an RC filter that adds a pole to the
loop response. If the pole frequency is low enough (as
when driving a large capacitive load), the circuit-phase
margin is degraded and oscillation may occur.
In a typical application, the MAX498/MAX499 drive a
back-terminated cable (Figure 1). The back-termination
resistor, at the output, matches the impedance of the
cable’s driven end to the cable’s impedance, eliminating
signal reflections. This resistor, along with the load-
termination resistor, forms a voltage divider with the load
impedance, which attenuates the signal at the cable’s
output by one-half. The MAX498/MAX499 operate with
an internal +2V/V closed-loop gain to provide unity gain
at the cable’s output.
The MAX498/MAX499 d rive c a p a c itive loa d s up to
100pF without sustained oscillation, although some
peaking may occur (Figures 3a and 3b). When driving
larger capacitive loads, or to reduce peaking, add an
) between the output and the
capacitive load (Figures 4a, 4b, and 5).
isolation resistor (R
ISO
______________________________________________________________________________________ 11
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
MAX186/MAX188
FULL POWER-DOWN
vs. SUPPLY VOLTAGE
8
7
-82
-84
-86
6
5
-88
-90
-92
-94
4
3
2
-96
-98
47
100 150
200
270
390
510
10
100
1k
10k
CAPACITANCE (pF)
FREQUENCY (Hz)
8/MAX49
Figure 6. Total Harmonic Distortion (Audio) vs. Frequency
Figure 5. Isolation Resistor vs. Capacitive Load
S w it c h in g Au d io S ig n a ls
(Au d io -Dis t o rt io n Me a s u re m e n t )
When switching audio signals, distortion is the prime
consideration in performance. Figure 6 shows total
harmonic distortion vs. frequency, in the audio range,
for the MAX498/MAX499.
Dig it a l In t e rfa c e
The MAX498/MAX499 multiplexer architecture ensures
that no input channels are ever connected together.
Select a channel by changing A0’s state (A0 = 0 for
channel A, and A0 = 1 for channel B) and pulsing CS low
(see Tables 1a and 1b). Figure 7 shows the logic timing
diagram.
La rg e S w it c h Arra ys
Large crosspoint switch arrays are possible with the
MAX498/MAX499 using the enable function EN. When
the amplifiers are disabled, output impedance is typi-
cally 1.2kΩ, due to the feedback and gain resistors.
This limits the number of outputs that can be paralleled
without a buffer. Since each output can drive 100Ω,
eight outputs can typically be connected together. If
additional outputs must be connected in parallel, a
MAX4178 (single), MAX496 (quad), or equivalent unity-
gain buffer can be used.
—–
When the enable input (EN) is driven to a TTL low state, it
—–
enables the MAX498/MAX499 amplifier outputs. When EN
is driven high, it disables the amplifier outputs. When
disabled, the MAX498/MAX499 exhibit a 1.2kΩ dis-
abled output resistance due to their internal feedback
resistors.
—–
LE determines whether EN is latched by CS or operates
independently. When the latch-enable input (LE) is con-
—–
nected to V+, CS becomes the latch control for the EN
—–
input register. If CS is low, both the EN and A0 latches
—–
are transparent; once CS returns high, both A0 and EN
Whether enabled or disabled, each input represents
more than 200kΩ of resistance. Capacitance is the
prime consideration limiting the number of inputs that
can be connected to a single output. Since each output
can drive 100pF of capacitance without an isolation
are latched.
—–
When LE is connected to ground, the EN latch is trans-
p a re nt a nd ind e p e nd e nt of CS. This a llows a ll
MAX498/MAX499 devices to be shut down simultane-
ously, regardless of CS’s input state. Simply connect
resistor, 50 inputs (C = 2pF, typical) can be driven
IN
—–
LE to g round a nd c onne c t a ll EN inp uts tog e the r
by a single output. However, peaking will occur as
inputs are added (Figure 3), which reduces the 0.1dB
bandwidth.
(Figure 8a). Hard wire LE to V+ or ground (rather than
driving LE with a gate) to prevent crosstalk from the
digital inputs to IN0A.
12 ______________________________________________________________________________________
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w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
8/MAX49
Another option for output disable is to connect LE to V+,
Table 1a. Amplifier and Channel
Selection with LE = V+
parallel the outputs of several MAX498/MAX499s, and use
—–
EN to individually disable all devices but the one in use
CS
EN
A0
FUNCTION
(Figure 8b).
Enables amplifier outputs. Selects
channel A.
Enables amplifier outputs. Selects
channel B.
When the outputs are disabled, off-isolation from the
analog inputs to the amplifier outputs is typically 81dB
at 10MHz.
0
0
0
0
0
1
Gro u n d in g a n d La yo u t
The MAX498/MAX499 bandwidths are in the RF fre -
quency range. Depending on the size of the PC board
used and the frequency of operation, it may be neces-
sary to use Micro-strip or Stripline techniques.
0
1
1
X
X
Disables amplifiers. Outputs high-Z.
X
Latches A0, EN. Outputs unchanged.
To realize the full AC performance of these high-speed
buffers, pay careful attention to power-supply bypassing
and board layout. The PC board should have at least two
layers (wire-wrap boards are too inductive, and bread
boards are too capacitive), with one side a signal layer
and the other a large, low-impedance ground plane. With
multilayer boards, locate the ground plane on the layer
that is not dedicated to a specific signal trace. The ground
plane should be as free from voids as possible. Connect
all ground pins to the ground plane.
Table 1b. Amplifier and Channel
Selection with LE = GND
CE
EN
A0
FUNCTION
Enables amplifier outputs. Selects
channel A.
0
0
0
Enables amplifier outputs. Latches A0
1
0
X
to output A or B, according to A0’s
state at CS’s last edge.
—–
Connect both positive power-supply pins together and
bypass with a 0.10µF ceramic capacitor at each power-
supply pin, as close to the device as possible. Repeat
for the negative power-supply pins. The capacitor lead
lengths should be as short as possible to minimize lead
inductance; surface-mount chip capacitors are ideal. A
large-value (10µF or greater) tantalum or electrolytic
bypass capacitor on each supply may be required for
high-current loads. The location of this capacitor is not
critical.
Disables amplifiers. Outputs high-Z.
A0 latch = channel A.
Enables amplifier outputs. Selects
channel B.
X
0
1
0
X
1
The MAX498/MAX499’s analog input pins are isolated
with ground pins to minimize parasitic coupling, which can
degrade crosstalk and/or amplifier stability. Keep signal
paths as short as possible to minimize inductance. Ensure
that all input channel traces are the same length, to main-
tain the phase relationship between the four channels. To
further reduce crosstalk, connect the coaxial-cable shield
to the ground side of the 75Ω terminating resistor at the
ground plane, and terminate all unused inputs to ground
and outputs with a 100Ω or 150Ω resistor to ground.
______________________________________________________________________________________ 13
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w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
tCS
CS
tSU
tH
A0
tSU
tH
EN
tOFF
tON
tPD
OUTPUTS
8/MAX49
tSW
LE = V+
Figure 7. Logic Timing Diagram
EN
AO
CS
LE
+5V
MAX498
MAX499
MAX498
MAX499
LE
SHUTDOWN
EN
EN
AO
LE
CS
MAX498
MAX499
+5V
MAX498
MAX499
LE
EN
NOTE: ISOLATION RESISTORS
(IF REQUIRED) NOT SHOWN.
(a)
(b)
–—–
–—–
Figure 8. (a) Simultaneous Shutdown of all MAX498/MAX499s; (b) Enable (EN) Register Latched by CS
14 ______________________________________________________________________________________
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
8/MAX49
MAX498/MAX499
MAX498/MAX499
50Ω
50Ω
100Ω
100Ω
V
IN
= 4Vp-p,
f = 10MHz,
R = 75Ω
50Ω
50Ω
50Ω
100Ω
100Ω
100Ω
100Ω
100Ω
50Ω
S
50Ω
50Ω
V
= 4Vp-p,
IN
100Ω
f = 10MHz,
R = 75Ω
S
a) ADJACENT CHANNEL
b) ALL HOSTILE
Figure 9. Test Circuits for Measuring Crosstalk: a) Adjacent Channel; b) All Hostile
75Ω CABLE
75Ω
MAX499
75Ω CABLE
75Ω CABLE
75Ω
DUT
75Ω
SOURCE:
TEKTRONIX
75Ω
MEASUREMENT:
TEKTRONIX VM700
1910 DIGITAL GENERATOR
VIDEO MEASUREMENT
SET
Figure 10. Differential Phase and Gain Error Test Circuit
______________________________________________________________________________________ 15
Qu a d /Trip le , S P DT, RGB S w it c h e s
w it h 2 5 0 MHz Vid e o Bu ffe r Am p lifie rs
____P in Co n fig u ra t io n s (c o n t in u e d )
___________________Ch ip In fo rm a t io n
SUBSTRATE CONNECTED TO: V
TRANSISTOR COUNT: 813
EE
TOP VIEW
IN0A
28
GND
IN1A
GND
IN2A
GND
IN3A
1
2
3
4
27 LE
26
EN
A0
25
24
23
22
21
MAX498
5
6
CS
OUT0
V
CC
V
CC
7
8
9
IN0B
V
EE
20 OUT1
V
EE
8/MAX49
GND
19
18
IN1B 10
OUT2
11
12
GND
IN2B
17 N.C.
16 OUT3
15 N.C.
GND 13
IN3B
14
SO
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
MIN
0.093
MAX
0.104
0.012
0.019
0.013
0.299
MIN
2.35
0.10
0.35
0.23
7.40
MAX
2.65
0.30
0.49
0.32
7.60
D
A
A1 0.004
0°- 8°
B
C
E
e
0.014
0.009
0.291
A
0.101mm
0.004in.
1.27
0.050
e
B
A1
H
L
0.394
0.016
0.419
0.050
10.00
0.40
10.65
1.27
C
L
INCHES
MILLIMETERS
MAX
PINS
DIM
MIN MAX MIN
E
H
Wide SO
SMALL-OUTLINE
PACKAGE
0.398 0.413 10.10 10.50
0.447 0.463 11.35 11.75
0.496 0.512 12.60 13.00
0.598 0.614 15.20 15.60
D
D
D
D
D
16
18
20
24
28
(0.300 in.)
0.697 0.713 17.70 18.10
21-0042A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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