FIN1032M [ROCHESTER]
QUAD LINE RECEIVER, PDSO16, 0.150 INCH, MS-012, SOIC-16;
| 型号： | FIN1032M |
| 厂家： | 
Rochester Electronics |
| 描述： | QUAD LINE RECEIVER, PDSO16, 0.150 INCH, MS-012, SOIC-16 光电二极管 接口集成电路 |
| 文件： | 总7页 (文件大小：928K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2001
Revised December 2001
FIN1032
3.3V LVDS 4-Bit High Speed Differential Receiver
General Description
Features
This quad receiver is designed for high speed interconnect
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The receiver translates LVDS levels, with a typical dif-
ferential input threshold of 100mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even
at high frequencies. This device is ideal for high speed
transfer of clock and data.
■ Greater than 400Mbs data rate
■ 3.3V power supply operation
■ 0.4ns maximum differential pulse skew
■ 2.5ns maximum propagation delay
■ Low power dissipation
■ Power OFF protection
The FIN1032 can be paired with its companion driver, the
FIN1031, or any other Fairchild LVDS driver.
■ Fail safe protection for open-circuit, shorted and termi-
nated conditions
■ Meets or exceeds the TIA/EIA-644 LVDS standard
■ Pin compatible with equivalent RS-422 and LVPECL
devices
■ 16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number Package Number
Package Description
FIN1032M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
FIN1032MTC
MTC16
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Function Table
Connection Diagram
Inputs
Outputs
ROUT
RIN+
ROUT−
EN
H
H
H
X
EN
X
X
X
L
H
L
L
H
L
H
Fail Safe Condition
H
H
L
H
L
L
X
L
H
X
L
Fail Safe Condition
X
H
Z
L
H
H = HIGH Logic Level
Z = High Impedance
L = LOW Logic Level
Fail Safe = Open, Shorted, Terminated
X = Don’t Care
Pin Descriptions
Pin Name
OUT1, ROUT2, ROUT3, ROUT4
RIN1+, RIN2+, RIN3+, RIN4+
RIN1−, RIN2−, RIN3−, RIN4−
EN
Description
LVTTL Data Outputs
Non-Inverting LVDS Inputs
Inverting LVDS Inputs
Driver Enable Pin
R
EN
VCC
GND
Inverting Driver Enable Pin
Power Supply
Ground
© 2001 Fairchild Semiconductor Corporation
DS500508
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +4.6 V
−0.5V to +4.6 V
−0.5V to 6 V
16 mA
DC Input Voltage (VIN
)
Supply Voltage (VCC
)
3.0 V to 3.6 V
DC Input Voltage (VOUT
)
Magnitude of Differential Voltage
(|VID|)
DC Output Current (IO)
100 mV to VCC
0.05 V to 2.35V
0 to VCC
Storage Temperature Range (TSTG
Max Junction Temperature (TJ)
Lead Temperature (TL)
)
−65°C to +150°C
150°C
Common-Mode Input Voltage (VIC
)
Input Voltage (VIN
)
Operating Temperature (TA)
−40°C to +85°C
(Soldering, 10 seconds)
260°C
≥ 10,000 V
≥ 500 V
Note 1: The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
ESD (Human Body Model)
ESD (Machine Model)
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Min
Typ
Max
Symbol
VTH
Parameter
Test Conditions
Units
(Note 2)
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input Current
See Figure 1 and Table 1
See Figure 1 and Table 1
100
mV
mV
µA
VTL
−100
IIN
V
IN = 0V or VCC
±20
±20
II(OFF)
Power-OFF Input Current
V
CC = 0V, VIN = 0V or 3.6V
µA
VIH
Input High Voltage (EN or EN)
2.0
VCC
0.8
V
V
VIL
Input Low Voltage (EN or EN)
Output HIGH Voltage
GND
CC −0.2
2.4
VOH
I
I
I
I
I
OH = −100 µA
OH = −8 mA
OH = 100 µA
OL = 8 mA
V
V
V
VOL
Output LOW Voltage
Input Clamp Voltage
0.2
0.5
VIK
IOZ
IOS
IK = −18 mA
−1.5
−15
V
Disabled Output Leakage Current
Output Short Circuit Test
EN = 0.8 and EN = 2V, VOUT = 3.6V or 0V
Receiver Enabled, VOUT = 0V
±20
−100
5
µA
mA
mA
mA
µA
(one output shorted at a time)
ICCZ
ICC
Disabled Power Supply Current
Power Supply Current
Receiver Disabled
Receiver Enabled, (RIN+ = 1V and RIN− = 1.4V)
or (RIN+ = 1.4V and RIN− = 1V)
15
IPU/PD
Output Power Up/Power Down
High Z Leakage Current
Input Capacitance
V
CC = 0V to 1.5V
±20
CIN
3.5
6
pF
pF
COUT
Output Capacitance
Note 2: All typical values are at TA = 25°C and with VCC = 3.3V.
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2
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Min
Typ
Max
Symbol
tPLH
Parameter
Test Conditions
Units
(Note 3)
Propagation Delay LOW-to-HIGH
Propagation Delay HIGH-to-LOW
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
1.0
1.0
2.5
2.5
1.2
1.2
0.4
ns
ns
ns
ns
ns
tPHL
tTLH
|VID| = 400 mV, CL = 10 pF,
0.7
0.7
tTHL
R
L = 1kΩ
tSK(P)
tSK(LH)
tSK(HL)
tSK(PP)
fMAX
Pulse Skew |tPLH - tPHL|
See Figure 1 and Figure 2
Channel-to-Channel Skew
0.3
1.0
ns
ns
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Operating Frequency
(Note 6)
R
L = 1kΩ, CL = 10 pF,
200
325
MHz
see Figure 1 and Figure 2
tZH
tZL
tHZ
tLZ
LVTTL Output Enable Time from Z to HIGH
LVTTL Output Enable Time from Z to LOW
LVTTL Output Disable Time from HIGH to Z
LVTTL Output Disable Time from LOW to Z
5.0
5.0
5.0
5.0
ns
ns
ns
ns
R
L = 1kΩ, CL = 10 pF,
See Figure 3 and Figure 4
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.
Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: fMAX Criteria: Input tR = tF < 1 ns, VID = 300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, VOL < 0.5V, VOH > 2.4V.
All channels switching in phase.
Note A: All input pulses have frequency = 10MHz, tR or tF = 1ns
Note B: CL includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
Resulting Differential Input
Resulting Common Mode Input
Voltage (mA)
VID
Voltage (V)
VIC
VIA
VIB
1.25
1.15
2.4
2.3
0.1
0
1.15
1.25
2.3
2.4
0
100
−100
100
1.2
1.2
2.35
2.35
0.05
0.05
1.2
−100
100
0.1
0.9
1.5
1.8
2.4
0
−100
600
1.5
0.9
2.4
1.8
0.6
0
−600
600
1.2
2.1
−600
600
2.1
0.3
0.6
−600
0.3
3
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FIGURE 2. LVDS Input to LVTTL Output AC Waveforms
Test Circuit for LVTTL Outputs
FIGURE 3. AC Loading Circuit for LVTTL Outputs
Voltage Waveforms Enable and Disable Times
Note A: CL includes probes and jig capacitance
Note B: All LVTTL input pulses have the following characteristics: Frequency = 10 MHz tR or tF ≤ 2 ns
FIGURE 4. LVTTL Outputs Test Circuit and AC Waveforms
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4
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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