FAN7311GX_技术文档

December 2007

FAN7311

LCD Backlight Inverter Drive IC

Features

Description

High-Efficiency Single-Stage Power Conversion

Wide Input Voltage Range: 5V to 25.5V

Backlight Lamp Ballast and Soft Dimming

Reduced Number of Required External Components

Precision Voltage Reference Trimmed to 2%

ZVS Full-Bridge Topology

The FAN7311 provides all the control functions for a

series parallel resonant converter as well as a pulse

width modulation (PWM) controller to develop a supply

voltage. Typical operating frequency range is between

30kHz and 250kHz, depending on the cold cathode fluo-

rescent lamp (CCFL) and the transformer's characteris-

tics. FAN7311 uses a new patented phase-shift control.

Soft-Start Capability

PWM Control at Fixed Frequency

Analog and Burst Dimming Function

Programmable Striking Frequency

Open-Lamp Protection

20-SOIC

20-SSOP

Open-Lamp Regulation

20-Pin SSOP/SOIC/DIP

1

Applications

LCD TV

20-DIP

LCD Monitor

1

Ordering Information

Part Number

FAN7311G

Package

20-SSOP

20-SOIC

20-DIP

Operating Temperature Range

Packing Method

Rail

FAN7311GX

FAN7311M

FAN7311MX

FAN7311N

Tape & Reel

Rail

-25°C to 85°C

Tape & Reel

Rail

All packages are lead free per JEDEC: J-STD-020B standard.

Protected by U.S. Patent: 5,652,479; 7,158,390.

FAN7311 Rev. 1.0.7

www.fairchildsemi.com

Internal Block Diagram

RT

CT

OUTA

OSCILLATOR

Output

Driver

max. 2V

OUTB

PGND

OUTC

min. 0.5V

Output

Control

Logic

-

+

6μA

S_S

RT1

Output

Driver

OUTD

M_RT1

OLP

Striking

Logic

S_S

1.4μA

EA_OUT

ADIM

UVLO

OLP

OLR

+

-

SET

CLR

V_OLP+α

V_OLP

Q

S

R

+

-

Error Amp.

Q

UVLO

2.5V 1.5V

EA_IN

2.5V

+

-

S_olr

S_olr105μA

S_burst85μA

2V

2.5V_REF

Voltage

Reference

&

Internal

Bias

REF

ENA

V_IN

V_a+α

max. 2V

min. 0.5V

+

-

BCT

BDIM

AGND

-

S_burst

1.4V

+

V_IN

+

-

UVLO

UVLO 5V

FAN7311 Rev.06

Figure 1. Functional Block Diagram of FAN7311

FAN7311 Rev. 1.0.7

www.fairchildsemi.com

2

Pin Assignments

RT1

OUTB OUTA

V_IN

17

PGND OUTC OUTD CT

16 15 14 13

RT

12

BCT

11

20

19

18

FAN7311

1

2

3

4

5

6

7

8

9

10

OLP

OLR

ENA

S_S

GND

REF

ADIM BDIM EA_IN EA_OUT

FAN7311 Rev. 05

Figure 2. Pin Configuration (Top View)

Pin Definitions

Pin #

Name

OLP

Description

Pin #

11

Name

BCT

Description

Burst Dimming Timing Capacitor

Timing Resistor

1

2

Open-Lamp Protection

Open-Lamp Regulation

Enable Input

OLR

12

RT

3

ENA

13

CT

Timing Capacitor

4

S_S

Soft-Start

14

OUTD

OUTC

PGND

NMOSFET Drive Output D

PMOSFET Drive Output C

Power Ground

5

GND

Analog Ground

15

6

REF

2.5V Reference Voltage

Analog Dimming Input

Burst Dimming Input

Error Amplifier Input

Error Amplifier Output

16

7

ADIM

BDIM

EA_IN

EA_OUT

17

V

Supply Voltage

IN

8

18

OUTA

OUTB

RT1

PMOSFET Drive Output A

NMOSFET Drive Output B

Striking Frequency Resistor

9

19

10

20

FAN7311 Rev. 1.0.7

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3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-

ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-

tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The

absolute maximum ratings are stress ratings only.

Symbol

Characteristics

Min.

5.0

Max.

25.5

+85

+150

112

Unit

V

Supply Voltage

IN

T

Operating Temperature Range

Junction Temperature

-25

°C

A

T

°C

J

T

Storage Temperature Range

-65

°C

STG

20-SSOP

20-SOIC

20-SSOP

20-SOIC

(1)

θ

Thermal Resistance Junction-to-Ambient (still air)

°C/W

W

JA

90

1.1

P

Power Dissipation

D

1.4

Notes:

1. Thermal resistance test board size: 76.2 • 114.3 • 1.6mm (1S0P). JEDEC standard: JESD51-2, JESD51-3.

FAN7311 Rev. 1.0.7

www.fairchildsemi.com

4

Electrical Characteristics

For typical values, T =25°C and V =12V. For minimum and maximum values, T is the operating ambient tempera-

A

IN

A

ture range with -25°C ≤ T ≤ 85°C and 5V ≤ V ≤ 25.5V, unless otherwise specified. Specifications from -25°C to 85°C

A

IN

are guaranteed by design based on final characterization results.

Symbol Characteristics Test Condition

REFERENCE SECTION (Recommend X7R Capacitor)

Min.

Typ.

Max.

Unit

ΔV

Line Regulation

5 ≤ V ≤ 25.5V

2

25

mV

V

ref

IN

V25

2.5V Regulation Voltage

2.45

2.50

2.55

OSCILLATOR SECTION (MAIN)

T = 25°C, CT = 270pF,

RT = 18kΩ

A

110.4

108

115.0

119.6

122

f

Oscillation Frequency

kHz

osc

CT = 270pF, RT = 18kΩ

115

2.0

0.5

V

CT High Voltage

CT Low Voltage

V

cth

V

ctl

OSCILLATOR SECTION (BURST)

T = 25°C, C = 10nF,

RT=18kΩ

A

tb

209.25 225.00 240.75

f

Oscillation Frequency

Hz

oscb

C

= 10nF, RT=18kΩ

206.25 225.00 241.75

tb

V

BCT High Voltage

BCT Low Voltage

2

V

bcth

V

0.5

bctl

ERROR AMP SECTION

Open-Loop Gain

Unit Gain Bandwidth

(3)

A

80

dB

MHz

V

v

(3)

G

1.5

BW

V

Feedback Output High Voltage

Output Sink Current

EA_IN = 0V

2.00

2.27

2.54

-1

eh

sin

sur

l

EA_OUT = 1.5V

mA

µA

V

l

Output Source Current

1

I

EA_IN Driving Current on OLR

EA_IN Driving Current on Burst Dimming

75

61

105

85

135

109

olr

I

burst

V

Feedback High Voltage on Burst Dimming R(EA_IN) = 60kΩ

V +0.1 V +0.4 V +0.7

a a a

fbh

SOFT-START SECTION

I

Soft-Start Current

S_S=1V

4

6

4

8

µA

V

SS

(3)

V

Soft-Start Clamping Voltage

ssh

PROTECTION SECTION

V

Open-Lamp Protection Voltage 0

Open-Lamp Protection Voltage 1

Open-Lamp Regulation Voltage

Open-Lamp Protection Charging Current

Start at open lamp

2.2

1.3

2.5

1.5

2.8

1.7

V

olp0

V

Normal -> open lamp

olp1

V

1.75

0.7

2.00

1.4

2.25

2.1

V

olr

I

µA

olp

UNDER-VOLTAGE LOCKOUT SECTION

V

Start Threshold Voltage

Start-up Current

5

V

th

I

V

= V -0.2

130

1.5

180

4.0

370

µA

mA

µA

st

IN

th

I

Operating Supply Current

Stand-by Current

= 12V

op

I

200

sb

Note:

3. These parameters, although guaranteed, are not 100% tested in production.

www.fairchildsemi.com

FAN7311 Rev. 1.0.7

5

Electrical Characteristics (Continued)

For typical values, T =25°C and V =12V. For min. and max. values, T is the operating ambient temperature range

A

IN

A

with -25°C ≤ T ≤ 85°C and 5V ≤ V ≤ 25.5V, unless otherwise specified. Specifications from -25°C to 85°C are guar-

A

IN

anteed by design based on final characterization results.

Symbol

Characteristics

Test Condition

Min.

Typ.

Max.

Unit

ON/OFF SECTION

V

On State Input Voltage

Off Stage Input Voltage

OUTPUT SECTION

2

5

V

on

V

0.7

off

V

PMOS Gate High Voltage

PMOS Gate Low Voltage

NMOS Gate Drive Voltage

V

= 12V

V

IN

V

pdhv

IN

V

V -10.5 V -8.5 V -6.5

phlv

ndhv

IN

V

6.5

8.5

10.5

V

0

V

PMOS Gate Voltage With UVLO Activated V = V -0.2

V -0.3

V

puv

nuv

IN

th

IN

V

NMOS Gate Voltage With UVLO Activated V = V -0.2

0.3

500

V

IN

th

(4)

t

Rising Time

V

= 12V, C =2nF

200

ns

r

L

(4)

t

Falling Time

= 12V, C =2nF

f

L

MAXIMUN / MINIMUM OVERLAP

Minimum Overlap Between Diagonal

Switches

f

= 100kHz

0

%

(4)

osc

Maximum Overlap Between Diagonal

f

100

(4)

Switches

DELAY TIME

PDR_A/NDR_B

(4)

RT = 18kΩ

450

ns

PDR_C/NDR_D

Note:

4. These parameters, although guaranteed, are not 100% tested in production.

www.fairchildsemi.com

FAN7311 Rev. 1.0.7

6

Function Description

UVLO: The under-voltage lockout circuit guarantees sta-

ble operation of the IC’s control circuit by stopping and

starting it as a function of the V value. The UVLO cir-

IN

cuit turns on the control circuit when V exceeds 5V.

IN

When V is lower than 5V, the IC’s standby current is

IN

less than 200µA.

ENA: Applying voltage higher than 2V to the ENA pin

enables operation of the IC. Applying voltage lower than

0.7V to the ENA pin disables operation of the inverter.

Soft-Start: The soft-start function requires that the S_S

pin is connected through a capacitor to GND. A soft-start

circuit ensures a gradual increase in the input and output

power. The capacitor connected to the S_S pin deter-

mines the rate at which the duty ratio rises. It is charged

by a 6µA current source.

Figure 4. Main Oscillator Waveform

Burst Oscillator & Burst Dimming: The timing capaci-

tors (BCTs) are charged by the reference current source,

which is formed by the timing resistor (RT). The timing

resistor’s voltage is regulated at 1.25V. The sawtooth

waveform charges up to 2V. Once this voltage is

reached, the capacitors begin discharging down to 0.5V.

Next, the timing capacitors start charging again and a

new switching cycle begins. The burst dimming fre-

quency can be programmed by adjusting the RT and

BCT values. The burst dimming frequency can be calcu-

lated as shown in Equation 2.

3.75

(2)

f^burst=

96 ⋅ RT ⋅CT

Figure 3. Soft-Start During Initial Operation

To avoid visible flicker, the burst dimming frequency

should be greater than 120Hz.

Main Oscillator: The timing capacitors (CTs) are

charged by the reference current source, which is

formed by the timing resistor (RT). The timing resistor’s

voltage is regulated at 1.25V. The sawtooth waveform

charges up to 2V. Once this voltage is reached, the

capacitors begin discharging down to 0.5V. Next, the tim-

ing capacitors start charging again and a new switching

cycle begins. The main frequency can be programmed

by adjusting the RT and CT values. The main frequency

can be calculated as shown below.

By comparing the input of BDIM pin with the 0.5~2V tri-

angular wave of the burst oscillator, the PWM pulses for

burst dimming. The PWM pulse controls EA_OUT’s volt-

age by summing 85µA into the EA_IN pin.

19

(1)

fop =

32 ⋅ RT ⋅CT

FAN7311 Rev. 1.0.7

www.fairchildsemi.com

7

Figure 5. Burst Oscillator Waveform

Figure 7. OLR Voltage During Striking Mode

Output Drives: The four output drives are designed so

that switches A and B, C and D never turn on simulta-

neously. The OUTA-OUTB pair is intended to drive one

half-bridge in the external power stage. The OUTC-

OUTD pair drives the other half-bridge.

VIN

8.5V

VIN

8.5V

Figure 6. Burst Dimming

Open-Lamp Regulation and Open-Lamp Protection:

It is necessary to suspend power stage operation if an

open lamp occurs, because the power stage has high

gain. When a voltage higher than 2V is applied to the

OLR pin, the part enters regulation mode and controls

the EA_OUT voltage. This limits the lamp voltage by

summing 105µA into the feedback node. At the same

time, the OLP capacitor, connected to the OLP pin, is

charged by the 1.4µA internal current source. Once it

reaches 2.5V, the IC shuts down and all output is high.

8.5V

Figure 8. Phase-Shift Control Waveforms

FAN7311 Rev. 1.0.7

www.fairchildsemi.com

8

Timing Diagram

The FAN7311 uses the improved phase-shift control full-bridge to drive CCFL. As a result, the temperature difference

between the left and the right leg is almost zero. The detail timing is shown below.

EA_OUT

CT

SYNC

T

T1

POUT A

NOUT B

POUT C

NOUT D

FAN7311 Rev.04

Figure 9. Phase-Shift Control Waveforms

FAN7311 Rev. 1.0.7

www.fairchildsemi.com

9

Typical Application Circuits

Application

Lamps

Input Voltage

19-inch LCD Monitor

4

13V

1. Schematic

F1

FUSE

C22

C25

C27

220μF

25V

1μF

M1

CN5

0.1μF

82kΩ

C26

R6

IC1

FAN7311

0

1

2

3

4

5

6

7

8

9

10

SN

GN

SP

DN

DP

12V

RT

OLP

RT1

OUTB

OUTA

VIN

OUTB

OUTA

OLR

R25

10kΩ

C7

10μF

ON/OFF

LTM190EX

ENA

GP

R24

C1 0.22μF

C6 1μF

TX1

10kΩ

C28

10nF

FDS8958A

1

0

S_S

0

HOT

12505WR-10

C8

10μF

CN1

CCFL

0

GND

REF

PGND

OUTC

OUTD

CT

0

M2

2

COLD

J1

C2 1μF

R7 0Ω

REF

1

2

DIM(0~3.3V)

0

HOT

SN

GN

SP

DN

0

CN2

CCFL

R2

56kΩ

ADIM

BDIM

EA_IN

EA_OUT

C10

15pF

C11

15pF

DN

DP

COLD

C5

R5

C4

220pF

27kΩ

4.7nF

0

R4

22kΩ

R27

10kΩ

OLP1

OLP2

C21

10nF

R3

RT

GP

DP

18kΩ

C3 4.7n

FDS8958A

BCT

D6

D7

OLR

0

BAV99

R26

1kΩ

C14

10nF

R13

1kΩ

C30

10nF

R16

1kΩ

R17

1kΩ

RT

D4

BAV70

FB

R8

R15

10kΩ

0

100kΩ

R9

9.1kΩ

FB

TX2

1

2

HOT

0

OLR

CN3

CCFL

R14

COLD

100kΩ

1

2

HOT

REF

OLP1

OLP2

CN4

0

CCFL

R1

330kΩ

R22

R23

COLD

OLP

10kΩ

C12

15pF

C13

15pF

Q1

OLP3

OLP4

C9

KST2222

1μF

C19

2.2nF

C20

2.2nF

D11

BAW56

OLP3

OLP4

D3

BAV70

D8

D9

OLR

D1

BAW56

BAV99

R20

10kΩ

R21

10kΩ

C29

10nF

R11

1kΩ

R18

1kΩ

R19

1kΩ

R12

1kΩ

C15

10nF

0

D10

BAW56

FB

C18

2.2n

C17

2.2n

0

FAN7311 Rev. 04

Figure 10. Typical Application Circuit

2. Transformer Schematic Diagram

- Supported by Namyang electronics (http://www.namyangelec.co.kr)

FAN7311 Rev. 04

Figure 11. Transformer Schematic

3. Core & Bobbin

Core: EFD2124

Material: PL7

Bobbin: EFE2124

4. Winding Specification

Pin No.

5 --> 2

Wire

Turns

19

Inductance Leakage Inductance

Remarks

1KHz, 1V

1 UEW 0.45 φ

1 UEW 0.04 φ

115 µH

1.5 H

21.5µH

280mH

7 --> 9

2300

FAN7311 Rev. 1.0.7

www.fairchildsemi.com

10

5. BOM of the Application Circuit

Part Ref.

Value

Description / Vendor

Part Ref.

C5

Value

220pF

1µF

Description / Vendor

50V 1608 J

50V 2012 K

16V 3216

Fuse

F1

24V 3A

Fuse

C6

Resistor (SMD)

330kΩ

C7

10µF

1µF

R1

R2

1608 J

1608 F

1608 J

1608 F

1608 J

C8

16V 3216

56kΩ

18kΩ

22kΩ

27kΩ

82kΩ

100kΩ

9.1kΩ

1kΩ

C9

16V 1608 K

3KV 3216

R3

C10

C11

C12

C13

C14

C15

C17

C18

C19

C20

C21

C25

C26

C27

C28

C29

C30

15pF

10nF

2.2nF

10nF

1µF

R4

3KV 3216

R5

3KV 3216

R6

3KV 3216

R8

50V 1608 K

50V 1608 Z

50V 2012 K

16V 1608 K

50V 2012 K

50V 1608 Z

50V 1608 K

R9

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

1kΩ

100kΩ

10kΩ

1kΩ

0.1µF

1µF

1kΩ

10nF

10kΩ

1kΩ

Diode / TR (SMD)

D1

D3

BAW56

BAV70

BAV99

BAW56

KST2222

Fairchild Semiconductor

D4

D6

10kΩ

Capacitor (SMD)

0.22µF

1µF

D7

D8

C1

C2

C3

C4

16V 1608 K

50V 2012 K

50V 1608 K

D9

D10

D11

Q1

4.7nF

Electrolytic capacitor

220µF

Wafer (SMD)

C22

25V

CN1

CN2

CN3

CN4

CN5

35001WR-02A

12505WR-10

MOSFET (SMD)

M1

M2

FDS8958A

Fairchild Semiconductor

Transformer (SMD)

TX1

TX2

EFD2124

Supported by Namyang electronics (http://www.namyangelec.co.kr)

EFD2124

FAN7311 Rev. 1.0.7

www.fairchildsemi.com

11

Mechanical Dimensions

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Figure 12. 20-Lead Shrink Small Outline Package (SSOP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in

any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor

representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fair-

child’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

FAN7311 Rev. 1.0.7

www.fairchildsemi.com

12

Mechanical Dimensions (Continued)

.

13.00

12.60

A

11.43

20

11

B

9.50

10.65 7.60

10.00 7.40

2.25

1

10

0.65

0.51

1.27

PIN ONE

INDICATOR

1.27

0.35

M

0.25

C B A

LAND PATTERN RECOMMENDATION

SEE DETAIL A

2.65 MAX

0.33

0.20

C

0.10

C

0.30

0.10

SEATING PLANE

0.75

0.25

X 45°

NOTES: UNLESS OTHERWISE SPECIFIED

(R0.10)

A) THIS PACKAGE CONFORMS TO JEDEC

MS-013, VARIATION AC, ISSUE E

B) ALL DIMENSIONS ARE IN MILLIMETERS.

GAGE PLANE

0.25

8°

0°

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) CONFORMS TO ASME Y14.5M-1994

1.27

0.40

SEATING PLANE

E) LANDPATTERN STANDARD: SOIC127P1030X265-20L

F) DRAWING FILENAME: MKT-M20BREV3

(1.40)

DETAIL A

SCALE: 2:1

Figure 13. 20-Lead Small Outline Integrated Circuit (SOIC)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in

any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor

representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fair-

child’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

FAN7311 Rev. 1.0.7

www.fairchildsemi.com

13

Mechanical Dimensions (Continued)

24.892-26.924

PIN #1

6.223-6.477

7.620

1.524

3.175-3.429

2.921-3.810

2.540

5.334 MAX

0.381 MIN

0-15

9.017 TYP

0.457

N_AO_.T_COE_NS_F:_{ORMS TO JEDEC REGISTRATION MS-001,}

VARIATIONS AD

B. ALL DIMENSIONS ARE IN MILLIMETERS

C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED

0.25MM.

D. DOES NOT INCLUDE DAMBAR PROTRUSIONS.

DAMBAR PROTRUSIONS SHALL NOT EXCEED

0.25MM.

E. DRAWING FILE NAME: N20SREV1

Figure 14. 20-Lead Dual In-Line Package (DIP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in

any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor

representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fair-

child’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

FAN7311 Rev. 1.0.7

www.fairchildsemi.com

14

FAN7311 Rev. 1.0.7

www.fairchildsemi.com

15


型号：	FAN7311GX
厂家：	Rochester Electronics
描述：	LIQUID CRYSTAL DISPLAY DRIVER, PDSO20, LEAD FREE, SSOP-20 驱动光电二极管接口集成电路
文件：	总16页 (文件大小：1305K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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