FAN7311N [FAIRCHILD]
LCD Backlight Inverter Drive IC; LCD背光逆变器驱动IC
| 型号： | FAN7311N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | LCD Backlight Inverter Drive IC |
| 文件： | 总16页 (文件大小：374K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2007
FAN7311
LCD Backlight Inverter Drive IC
Features
Description
High-Efficiency Single-Stage Power Conversion
Wide Input Voltage Range: 5V to 25.5V
Backlight Lamp Ballast and Soft Dimming
Reduced Number of Required External Components
Precision Voltage Reference Trimmed to 2%
ZVS Full-Bridge Topology
The FAN7311 provides all the control functions for a
series parallel resonant converter as well as a pulse
width modulation (PWM) controller to develop a supply
voltage. Typical operating frequency range is between
30kHz and 250kHz, depending on the cold cathode fluo-
rescent lamp (CCFL) and the transformer's characteris-
tics. The FAN7311 uses a new patent-pending phase-
shift control.
Soft-Start Capability
PWM Control at Fixed Frequency
Analog and Burst Dimming Function
Programmable Striking Frequency
Open-Lamp Protection
20-SOIC
20-SSOP
Open-Lamp Regulation
20-Pin SSOP/SOIC/DIP
Applications
LCD TV
1
1
LCD Monitor
20-DIP
1
Ordering Information
Part Number
FAN7311G
Package
20-SSOP
20-SSOP
20-SOIC
20-SOIC
20-DIP
Pb-Free
Yes
Operating Temperature Range Packing Method
Rail
FAN7311GX
FAN7311M
Yes
Tape & Reel
Yes
-25°C to 85°C
Rail
Tape & Reel
Rail
FAN7311MX
FAN7311N
Yes
Yes
Protected by U.S. Patent: 5,652,479; 7,158,390.
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
Internal Block Diagram
RT
CT
OUTA
OSCILLATOR
Output
Driver
max. 2V
OUTB
PGND
OUTC
min. 0.5V
Output
Control
Logic
-
+
+
6μA
S_S
RT1
Output
Driver
OUTD
MRT1
OLP
Striking
Logic
S_S
1.4μA
EA_OUT
ADIM
UVLO
OLP
OLR
+
-
SET
CLR
VOLP+α
VOLP
Q
S
R
+
-
Error Amp.
Q
UVLO
2.5V 1.5V
EA_IN
2.5V
+
-
Solr
Solr 105μA
Sburst 85μA
2V
2.5VREF
Voltage
Reference
&
Internal
Bias
REF
ENA
VIN
Va+α
max. 2V
min. 0.5V
+
-
BCT
BDIM
AGND
-
Sburst
1.4V
+
VIN
+
-
UVLO
UVLO 5V
FAN7311 Rev.06
Figure 1. Functional Block Diagram of FAN7311
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
2
Pin Assignments
RT1
OUTB OUTA
VIN
17
PGND OUTC OUTD CT
16 15 14 13
RT
12
BCT
11
20
19
18
FAN7311
1
2
3
4
5
6
7
8
9
10
OLP
OLR
ENA
S_S
REF
ADIM BDIM EA_IN EA_OUT
GND
FAN7311 Rev. 05
Figure 2. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
OLP
Description
Pin #
11
Name
BCT
Description
Burst Dimming Timing Capacitor
Timing Resistor
1
2
Open-Lamp Protection
Open-Lamp Regulation
Enable Input
OLR
12
RT
3
ENA
13
CT
Timing Capacitor
4
S_S
Soft-Start
14
OUTD
OUTC
PGND
VIN
NMOSFET Drive Output D
PMOSFET Drive Output C
Power Ground
5
GND
Analog Ground
15
6
REF
2.5V Reference Voltage
Analog Dimming Input
Burst Dimming Input
Error Amplifier Input
Error Amplifier Output
16
7
ADIM
BDIM
EA_IN
EA_OUT
17
Supply Voltage
8
18
OUTA
OUTB
RT1
PMOSFET Drive Output A
NMOSFET Drive Output B
Striking Frequency Resistor
9
19
10
20
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
For typical values, TA=25°C and VIN=12V. For min. and max. values, TA is the operating ambient temperature range
with -25°C ≤ TA ≤ 85°C and 5V ≤ VIN ≤ 25.5V, unless otherwise specified.
Symbol
VIN
Characteristics
Value
5 to 25.5
-25 to 85
150
Unit
V
Supply Voltage
TA
Operating Temperature Range
°C
TJ
Junction Temperature
°C
TSTG
Storage Temperature Range
-65 to 150
°C
Thermal Resistance Junction-to-Ambient (still air)(1)
20-SSOP
20-SOIC
112
70
TBD(2)
θJA
°C/W
W
20-DIP
Power Dissipation
20-SSOP
20-SOIC
1.1
1.8
PD
20-DIP
TBD
Notes:
1. Thermal resistance test board size: 76.2 * 114.3 * 1.6mm (1S0P). JEDEC standard: JESD51-2, JESD51-3.
2. To be determined.
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
4
Electrical Characteristics
For typical values, TA=25°C and VIN=12V. For min. and max. values, TA is the operating ambient temperature range
with -25°C ≤ TA ≤ 85°C and 5V ≤ VIN ≤ 25.5V, unless otherwise specified. Specifications from -25°C to 85°C are guar-
anteed by design based on final characterization results.
Symbol
Characteristics
Test Condition
Min.
Typ.
Max.
Unit
REFERENCE SECTION (Recommend X7R Capacitor)
ΔVref
Line Regulation
5 ≤ VIN ≤ 25.5V
2
25
mV
V
V25
2.5V Regulation Voltage
2.45
2.50
2.55
OSCILLATOR SECTION (MAIN)
TA = 25°C, CT = 270pF,
RT = 18kΩ
110.4
108
115.0
119.6
122
fosc
Oscillation Frequency
kHz
CT = 270pF, RT = 18kΩ
115
2.0
0.5
Vcth
Vctl
CT High Voltage
CT Low Voltage
V
V
OSCILLATOR SECTION (BURST)
TA = 25°C, CTB = 10nF,
RT=18kΩ
209.25 225.00 240.75
foscb
Oscillation Frequency
Hz
CTB = 10nF, RT=18kΩ
206.25 225.00 241.75
Vbcth
Vbctl
BCT High Voltage
BCT Low Voltage
2
V
V
0.5
ERROR AMP SECTION
Av
GBW
Veh
lsin
Open Loop Gain(3)
Unit Gain Bandwidth(3)
80
dB
MHz
V
1.5
Feedback Output High Voltage
Output Sink Current
EA_IN = 0V
2.00
2.27
2.54
-1
EA_OUT = 1.5V
EA_OUT = 1.5V
mA
mA
µA
µA
V
lsur
Output Source Current
1
Iolr
EA_IN Driving Current on OLR
EA_IN Driving Current on Burst Dimming
75
61
105
85
135
109
Iburst
Vfbh
SOFT-START SECTION
Feedback High Voltage on Burst Dimming R(EA_IN) = 60kΩ
Va+0.1 Va+0.4 Va+0.7
ISS
Soft-Start Current
Soft-Start Clamping Voltage(3)
S_S=1V
4
6
4
8
µA
V
Vssh
PROTECTION SECTION
Volp0
Volp1
Volr
Open-Lamp Protection Voltage 0
Start at open lamp
2.2
1.3
2.5
1.5
2.8
1.7
V
V
Open-Lamp Protection Voltage 1
Open-Lamp Regulation Voltage
Normal -> open lamp
1.75
0.7
2.00
1.4
2.25
2.1
V
Iolp
Open-Lamp Protection Charging Current
µA
UNDER-VOLTAGE LOCKOUT SECTION
Vth
Ist
Start Threshold Voltage
Startup Current
5
V
VIN = Vth-0.2
VIN = 12V
VIN = 12V
130
1.5
180
4.0
370
µA
mA
µA
Iop
Isb
Note:
Operating Supply Current
Stand-by Current
200
3. These parameters, although guaranteed, are not 100% tested in production.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7311 Rev. 1.0.6
5
Electrical Characteristics (Continued)
For typical values, TA=25°C and VIN=12V. For min. and max. values, TA is the operating ambient temperature range
with -25°C ≤ TA ≤ 85°C and 5V ≤ VIN ≤ 25.5V, unless otherwise specified. Specifications from -25°C to 85°C are guar-
anteed by design based on final characterization results.
Symbol
Characteristics
Test Condition
Min.
Typ.
Max.
Unit
ON/OFF SECTION
Von
Voff
On State Input Voltage
Off Stage Input Voltage
2
5
V
V
0.7
OUTPUT SECTION
Vpdhv PMOS Gate High Voltage
Vphlv PMOS Gate Low Voltage
VIN = 12V
VIN
V
V
VIN = 12V
VIN = 12V
VIN = 12V
VIN-10.5 VIN-8.5 VIN-6.5
Vndhv NMOS Gate Drive Voltage
Vndhv NMOS Gate Drive Voltage
6.5
8.5
0
10.5
V
V
Vpuv
Vnuv
tr
PMOS Gate Voltage With UVLO Activated VIN = Vth-0.2
NMOS Gate Voltage With UVLO Activated VIN = Vth-0.2
VIN-0.3
V
0.3
500
500
V
Rising Time(4)
Falling Time(4)
VIN = 12V, CL=2nF
200
200
ns
ns
tf
VIN = 12V, CL=2nF
MAX./MIN. OVERLAP
Min. Overlap Between Diagonal
fosc = 100kHz
fosc = 100kHz
0
%
%
Switches(4)
Max. Overlap Between Diagonal
Switches(4)
100
DELAY TIME
PDR_A/NDR_B(4)
PDR_C/NDR_D(4)
RT = 18kΩ
RT = 18kΩ
450
450
ns
ns
Note:
4. These parameters, although guaranteed, are not 100% tested in production.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7311 Rev. 1.0.6
6
Function Description
UVLO: The under-voltage lockout circuit guarantees sta-
ble operation of the IC’s control circuit by stopping and
starting it as a function of the VIN value. The UVLO cir-
cuit turns on the control circuit when VIN exceeds 5V.
When VIN is lower than 5V, the IC’s standby current is
less than 200µA.
ENA: Applying voltage higher than 2V to the ENA pin
enables operation of the IC. Applying voltage lower than
0.7V to the ENA pin disables operation of the inverter.
Soft-Start: The soft-start function requires that the S_S
pin is connected through a capacitor to GND. A soft-start
circuit ensures a gradual increase in the input and output
power. The capacitor connected to the S_S pin deter-
mines the rate at which the duty ratio rises. It is charged
by a 6µA current source.
Figure 4. Main Oscillator Waveform
Burst Oscillator & Burst Dimming: The timing capaci-
tors (BCTs) are charged by the reference current source,
which is formed by the timing resistor (RT). The timing
resistor’s voltage is regulated at 1.25V. The sawtooth
waveform charges up to 2V. Once this voltage is
reached, the capacitors begin discharging down to 0.5V.
Next, the timing capacitors start charging again and a
new switching cycle begins. The burst dimming fre-
quency can be programmed by adjusting the RT and
BCT values. The burst dimming frequency can be calcu-
lated as shown in Equation 2.
3.75
(2)
fburst =
96 ⋅RT ⋅CT
Figure 3. Soft-Start During Initial Operation
To avoid visible flicker, the burst dimming frequency
should be greater than 120Hz.
Main Oscillator: The timing capacitors (CTs) are
charged by the reference current source, which is
formed by the timing resistor (RT). The timing resistor’s
voltage is regulated at 1.25V. The sawtooth waveform
charges up to 2V. Once this voltage is reached, the
capacitors begin discharging down to 0.5V. Next, the tim-
ing capacitors start charging again and a new switching
cycle begins. The main frequency can be programmed
by adjusting the RT and CT values. The main frequency
can be calculated as shown below.
By comparing the input of BDIM pin with the 0.5~2V tri-
angular wave of the burst oscillator, the PWM pulses for
burst dimming. The PWM pulse controls EA_OUT’s volt-
age by summing 85µA into the EA_IN pin.
19
(1)
fop =
32 ⋅ RT ⋅CT
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
7
Figure 5. Burst Oscillator Waveform
Figure 7. OLR Voltage During Striking Mode
Output Drives: The four output drives are designed so
that switches A and B, C and D never turn on simulta-
neously. The OUTA-OUTB pair is intended to drive one
half-bridge in the external power stage. The OUTC-
OUTD pair drives the other half-bridge.
VIN
8.5V
8.5V
VIN
8.5V
Figure 6. Burst Dimming
Open Lamp Regulation and Open-Lamp Protection: It
is necessary to suspend power stage operation if an
open lamp occurs, because the power stage has high
gain. When a voltage higher than 2V is applied to the
OLR pin, the part enters regulation mode and controls
the EA_OUT voltage. This limits the lamp voltage by
summing 105µA into the feedback node. At the same
time, the OLP capacitor, connected to the OLP pin, is
charged by the 1.4µA internal current source. Once it
reaches 2.5V, the IC enters shut down where all output is
high.
8.5V
Figure 8. Phase-Shift Control Waveforms
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
8
Timing Diagram
The FAN7311 uses the improved phase-shift control full-bridge to drive CCFL. As a result, the temperature difference
between the left and the right leg is almost zero. The detail timing is shown below.
EA_OUT
CT
SYNC
T
T1
POUT A
NOUT B
POUT C
NOUT D
FAN7311 Rev.04
Figure 9. Phase-Shift Control Waveforms
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
9
Typical Application Circuits
Application
Lamps
Input Voltage
19-inch LCD Monitor
4
13V
1. Schematic
F1
FUSE
C22
C25
C27
220μF
25V
1μF
1μF
M1
CN5
0.1μF
82kΩ
C26
R6
IC1
FAN7311
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
SN
GN
SP
DN
DN
DP
DP
12V
RT
OLP
RT1
OUTB
OUTA
VIN
OUTB
OUTA
OLR
R25
10kΩ
C7
10μF
ON/OFF
LTM190EX
ENA
GP
R24
C1 0.22μF
C2 1μF
C6 1μF
TX1
10kΩ
C28
10nF
FDS8958A
1
0
0
0
0
0
S_S
HOT
12505WR-10
C8
10μF
CN1
CCFL
0
GND
REF
PGND
OUTC
OUTD
CT
0
M2
SN
GN
SP
2
COLD
J1
REF
1
2
DIM(0~3.3V)
0
HOT
DN
0
CN2
CCFL
R2
56kΩ
ADIM
BDIM
EA_IN
EA_OUT
C10
15pF
C11
15pF
DN
DP
COLD
R7
0Ω
C5
R5
C4
220pF
27kΩ
4.7nF
0
0
0
R4
22kΩ
R27
10kΩ
OLP1
OLP2
R3
C21
10nF
RT
DP
GP
18kΩ
C3 4.7n
FDS8958A
BCT
D6
D7
OLR
0
0
BAV99
BAV99
R26
1kΩ
C14
10nF
R13
1kΩ
C30
10nF
R16
1kΩ
R17
1kΩ
RT
D4
BAV70
FB
R8
R15
10kΩ
0
0
0
0
0
0
0
0
100kΩ
R9
9.1kΩ
FB
TX2
1
2
HOT
0
OLR
CN3
CCFL
R14
COLD
100kΩ
1
2
HOT
REF
OLP1
OLP2
CN4
CCFL
0
R1
330kΩ
R22
R23
COLD
OLP
10kΩ
10kΩ
C12
15pF
C13
15pF
Q1
OLP3
OLP4
C9
KST2222
1μF
C19
2.2nF
C20
2.2nF
D11
BAW56
OLP3
OLP4
D3
BAV70
D8
D9
OLR
D1
BAW56
BAV99
BAV99
R20
10kΩ
R21
10kΩ
C29
10nF
R11
1kΩ
R18
1kΩ
R19
1kΩ
R12
1kΩ
C15
10nF
0
0
0
0
0
0
0
0
0
0
0
D10
BAW56
FB
C18
2.2n
C17
2.2n
0
0
FAN7311 Rev. 04
Figure 10. Typical Application Circuit
2. Transformer Schematic Diagram
- Supported by Namyang electronics (http://www.namyangelec.co.kr)
FAN7311 Rev. 04
Figure 11. Transformer Schematic
3. Core & Bobbin
Core: EFD2124
Material: PL7
Bobbin: EFE2124
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
10
4. Winding Specification
Pin No.
5 --> 2
Wire
Turns
19
Inductance Leakage Inductance
Remarks
1KHz, 1V
1KHz, 1V
1 UEW 0.45 φ
1 UEW 0.04 φ
115 µH
1.5 H
21.5µH
280mH
7 --> 9
2300
5. BOM of the Application Circuit
Part Ref.
Value
Description / Vendor
Part Ref.
Value
220pF
1µF
Description / Vendor
50V 1608 J
50V 2012 K
16V 3216
Fuse
C5
C6
F1
24V 3A
Fuse
Resistor (SMD)
330kΩ
C7
10µF
10µF
1µF
R1
R2
1608 J
1608 F
1608 F
1608 F
1608 F
1608 F
1608 F
1608 F
1608 F
1608 F
1608 F
1608 F
1608 F
1608 F
1608 F
1608 F
1608 F
1608 J
1608 J
1608 J
1608 J
1608 J
1608 J
1608 F
1608 J
C8
16V 3216
56kΩ
18kΩ
22kΩ
27kΩ
82kΩ
100kΩ
9.1kΩ
1kΩ
C9
16V 1608 K
3KV 3216
R3
C10
C11
C12
C13
C14
C15
C17
C18
C19
C20
C21
C25
C26
C27
C28
C29
C30
15pF
15pF
15pF
15pF
10nF
10nF
2.2nF
2.2nF
2.2nF
2.2nF
10nF
1µF
R4
3KV 3216
R5
3KV 3216
R6
3KV 3216
R8
50V 1608 K
50V 1608 K
50V 1608 Z
50V 1608 Z
50V 1608 Z
50V 1608 Z
50V 1608 Z
50V 2012 K
16V 1608 K
50V 2012 K
50V 1608 Z
50V 1608 K
50V 1608 K
R9
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
1kΩ
1kΩ
100kΩ
10kΩ
1kΩ
1kΩ
0.1µF
1µF
1kΩ
1kΩ
10nF
10nF
10nF
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
1kΩ
Diode / TR (SMD)
D1
D3
BAW56
BAV70
BAV70
BAV99
BAV99
BAV99
BAV99
BAW56
BAW56
KST2222
Fairchild Semiconductor
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D4
D6
10kΩ
Capacitor (SMD)
0.22µF
1µF
D7
D8
C1
C2
C3
C4
16V 1608 K
50V 2012 K
50V 1608 K
50V 1608 K
D9
D10
D11
Q1
4.7nF
4.7nF
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
11
5. BOM of the Application Circuit (Continued)
Part Ref.
Value
Description / Vendor Part Ref.
Value
Description / Vendor
Electrolytic capacitor
220µF
Wafer (SMD)
C22
25V
CN1
CN2
CN3
CN4
CN5
35001WR-02A
35001WR-02A
35001WR-02A
35001WR-02A
12505WR-10
MOSFET (SMD)
M1
M2
FDS8958A
FDS8958A
Fairchild semiconductor
Fairchild semiconductor
Transformer (SMD)
EFD2124
TX1
TX2
Supported by Namyang electronics (http://www.namyangelec.co.kr)
EFD2124
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
12
Mechanical Dimensions
20-SSOP
Dimensions are in millimeters unless otherwise specified.
NOTE
1. THESE DIMENSIONS DO NOT INCLUDE MOLD PROTRUSION.
2. ( ) IS REFERENCE
3. [ ] IS ASS'Y OUT QUALITY
0.10 MAX
-0.05
+0.10
BD-6305 Rev. 00
2001.04.06
0.10 MAX
Figure 12. 20-Lead Shrink Small Outline Package (SSOP)
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
13
Mechanical Dimensions (Continued)
20-SOIC
Dimensions are in millimeters unless otherwise specified.
Inches
Millimeters
Symbol
Notes
Min.
Max.
Min.
Max.
A
.093
.004
.013
.009
.496
.291
.104
.012
.020
.013
.512
.299
2.35
0.10
0.33
0.23
12.60
7.40
2.65
0.30
0.51
0.32
13.00
7.60
A1
B
C
D
E
5
2
2
e
.050 BSC
1.27 BSC
H
h
.394
.010
.016
.419
.029
.050
10.00
0.25
0.40
10.65
0.75
1.27
L
3
6
N
α
20
20
0°
8°
0°
8°
ccc
—
.004
—
0.10
Notes:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5. "C" dimension does not include solder finish thickness.
6. Symbol "N" is the maximum number of terminals.
20
11
E
H
1
10
D
h x 45°
A1
A
C
SEATING
PLANE
– C –
α
e
B
LEAD COPLANARITY
ccc C
L
January 2001, Rev. A
soic20_dim.pdf
Figure 13. 20-Lead Small Outline Integrated Circuit (SOIC)
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
14
Mechanical Dimensions (Continued)
20-DIP
Dimensions are in millimeters unless otherwise specified.
Figure 14. 20-Lead Dual In-Line Package (DIP)
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
15
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Rev. I22
© 2006 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.6
www.fairchildsemi.com
16
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