CY7B9910-2SXCT [ROCHESTER]
7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, 0.300 INCH, LEAD FREE, MO-119, SOIC-24;
| 型号： | CY7B9910-2SXCT |
| 厂家： | 
Rochester Electronics |
| 描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, 0.300 INCH, LEAD FREE, MO-119, SOIC-24 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：1252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7B9910
CY7B9920
Low Skew Clock Buffer
Low Skew Clock Buffer
Features
Block Diagram Description
■ All outputs skew < 100 ps typical (250 max)
■ 15 to 80 MHz output operation
Phase Frequency Detector and Filter
The phase frequency detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the voltage controlled oscillator (VCO). These
blocks, along with the VCO, form a phase-locked loop (PLL) that
tracks the incoming REF signal.
■ Zero input to output delay
■ 50% duty cycle outputs
■ Outputs drive 50 terminated lines
■ Low operating current
VCO
■ 24-pin small-outline integrated circuit (SOIC) package
■ Jitter: < 200 ps peak-to-peak, < 25 ps RMS
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency. The operational range of the VCO is
determined by the FS control pin.
Functional Description
The CY7B9910 and CY7B9920 low skew clock buffers offer low
skew system clock distribution. These multiple output clock
drivers optimize the timing of high performance computer
systems. Each of the eight individual drivers can drive terminated
transmission lines with impedances as low as 50 . They deliver
minimal and specified output skews and full swing logic levels
(CY7B9910 TTL or CY7B9920 CMOS).
The completely integrated PLL enables ‘zero delay’ capability.
External divide capability, combined with the internal PLL, allows
distribution of a low frequency clock that is multiplied by virtually
any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock
speed and flexibility.
Logic Block Diagram
TEST
Voltage
Controlled
Oscillator
FB
Phase
Filter
Freq Det
REF
FS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Cypress Semiconductor Corporation
Document Number: 38-07135 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 6, 2010
[+] Feedback
CY7B9910
CY7B9920
Contents
Pinouts ..............................................................................3
Test Mode ..........................................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Switching Characteristics ................................................6
Switching Characteristics ................................................7
Switching Characteristics ................................................8
AC Timing Diagrams ........................................................9
Operational Mode Descriptions ....................................10
Ordering Information ......................................................11
Ordering Code Definition ...........................................11
Package Diagram ............................................................12
Acronyms ........................................................................13
Document Conventions .................................................13
Units of Measure .......................................................13
Document History Page .................................................14
Sales, Solutions, and Legal Information ......................15
Worldwide Sales and Design Support .......................15
Products ....................................................................15
PSoC Solutions .........................................................15
Document Number: 38-07135 Rev. *F
Page 2 of 15
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CY7B9910
CY7B9920
Pinouts
Figure 1. Pin Configuration – 24-pin (300-Mil) Molded SOIC
SOIC
Top View
REF
1
24
23
22
21
GND
TEST
NC
V
CCQ
2
FS
NC
3
4
GND
V
CCQ
20
19
18
17
16
15
5
V
CCN
6
V
CCN
Q0
7B9910
7B9920
Q7
Q6
GND
Q5
7
Q1
GND
Q2
8
9
10
11
12
Q4
14
13
Q3
V
CCN
V
CCN
FB
Table 1. Pin Definition
Signal Name
IO
Description
REF[1]
I
Reference frequency input. This input supplies the frequency and timing against which all functional
variations are measured.
FB
FS[1, 2, 3]
I
I
PLL feedback input (typically connected to one of the eight outputs).
Three level frequency range select. The ranges are described in the switching characteristics
tables.
TEST
Q[0..7]
NC
I
Three level select. See TEST MODE.
Clock outputs.
O
NC
No connect.
VCCN
VCCQ
GND
PWR
PWR
PWR
Power supply for output drivers.
Power supply for internal circuitry.
Ground.
Test Mode
The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 and
CY7B9920 to operate as described in Block Diagram Description on page 1. For testing purposes, any of the three level inputs can
have a removable jumper to ground or be tied LOW through a 100 resistor. This enables an external tester to change the state of
these pins.
If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected and input
levels supplied to REF directly control all outputs. Relative output-to-output functions are the same as in normal mode.
Notes
1. When the FS pin is selected HIGH, the REF input must not transition upon power up until V reached 4.3 V.
CC
2. The level to be set on FS is determined by the “normal” operating frequency (f
) of the VCO (see Logic Block Diagram). The frequency appearing at the REF and
NOM
FB inputs are f
when the output connected to FB is undivided. The frequency of the REF and FB inputs are f
/ X when the device is configured for a frequency
NOM
NOM
multiplication by using external division in the feedback path of value X.
3. For all three state inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
CC
circuitry holds an unconnected input to V / 2.
CC
Document Number: 38-07135 Rev. *F
Page 3 of 15
[+] Feedback
CY7B9910
CY7B9920
Maximum Ratings
Operating Range
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Ambient
Temperature
Range
VCC
Storage temperature ................................–65 C to +150 C
Ambient temperature with
power applied ...........................................–55 C to +125 C
Commercial
Industrial
0 C to +70 C
–40 C to +85 C
5 V 10%
5 V 10%
Supply voltage to ground potential ...............–0.5 V to +7.0 V
DC input voltage...........................................–0.5 V to +7.0 V
Output current into outputs (LOW) .............................. 64 mA
Static discharge voltage...........................................> 2001 V
(MIL-STD-883, method 3015)
Latch-up current .....................................................> 200 mA
Electrical Characteristics
Over the Operating Range
CY7B9910
CY7B9920
Parameter
Description
Test Conditions
Min
2.4
–
Max
–
Min
Max
–
Unit
VOH
Output HIGH voltage
VCC = Min, IOH = –16 mA
–
V
V
CC = Min, IOH = –40 mA
–
VCC – 0.75
–
VOL
Output LOW voltage
VCC = Min, IOL = 46 mA
VCC = Min, IOL = 46 mA
–
0.45
–
–
–
–
V
–
0.45
VCC
VIH
VIL
Input HIGH voltage
(REF and FB inputs only)
2.0
VCC
VCC – 1.35
V
V
Input LOW voltage
(REF and FB inputs only)
–0.5
0.8
–0.5
1.35
VCC
VIHH
VIMM
VILL
IIH
Three level input HIGH
voltage (Test, FS)[4]
Min VCC Max
Min VCC Max
Min VCC Max
VCC – 1 V
VCC
VCC – 1 V
V
Three level input MID
voltage (Test, FS)[4]
VCC / 2 – VCC / 2 +
500 mV 500 mV
VCC / 2 –
500 mV
VCC / 2 +
500 mV
V
Three level input LOW
voltage (Test, FS)[4]
0.0
1.0
0.0
1.0
V
Input HIGH leakage current VCC = Max, VIN = Max
(REF and FB inputs only)
–
10
–
10
µA
µA
µA
µA
µA
mA
IIL
Input LOW leakage current VCC = Max, VIN = 0.4 V
(REF and FB inputs only)
–500
–
–
–500
–
–
IIHH
IIMM
IILL
Input HIGH current
(Test, FS)
VIN = VCC
200
50
200
50
Input MID current
(Test, FS)
VIN = VCC / 2
VIN = GND
–50
–
–50
–
Input LOW current
(Test, FS)
–200
–250
–200
N/A
IOS
Output short circuit
current[5]
VCC = Max, VOUT
= GND (25 C only)
–
–
Notes
4. These inputs are normally wired to V , GND, or left unconnected (actual threshold voltages vary as a percentage of V ). Internal termination resistors hold
CC
CC
unconnected inputs at V / 2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t
CC
time before
LOCK
all datasheet limits are achieved.
5. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short circuit
protected.
Document Number: 38-07135 Rev. *F
Page 4 of 15
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CY7B9910
CY7B9920
Electrical Characteristics
Over the Operating Range (continued)
CY7B9910
Min Max
CY7B9920
Min Max
Parameter
Description
Test Conditions
Unit
ICCQ
Operating current used by VCCN = VCCQ = Max Commercial
–
–
–
85
90
14
–
–
–
85
90
19
mA
internal circuitry
All input selects open
VCCN = VCCQ = Max
Industrial
ICCN
Output buffer current per
output pair[6]
mA
IOUT = 0 mA
Input selects open, fMAX
PD
Power dissipation per
output pair[7]
VCCN = VCCQ = Max
–
78
–
104[8]
mW
IOUT = 0 mA
Input selects open, fMAX
[9]
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Test Conditions
Max
Unit
Input capacitance
TA = 25 C, f = 1 MHz, VCC = 5.0 V
10
pF
Figure 2. AC Test Loads and Waveforms
5V
3.0 V
2.0 V
2.0 V
th
0.8 V
R1 = 130
R2 = 91
R1
R2
V
th
=1.5 V
V =1.5 V
0.8 V
0.0 V
C = 50 pF (C = 30pF for –5 and – 2 devices)
L
L
C
L
(Includes fixture and probe capacitance)
1 ns
1 ns
7B9910–3
7B9910–4
TTL AC Test Load (CY7B9910)
TTL Input Test Waveform (CY7B9910)
V
CC
V
CC
R1 = 100
R2 = 100
80%
CC
20%
0.0 V
80%
= V / 2
20%
R1
R2
C = 50 pF (C = 30 pF for –5 and –2 devices)
V
th
= V / 2
V
th
L
L
CC
(Includes fixture and probe capacitance)
C
L
3 ns
3 ns
7B9910–5
7B9910–6
CMOS Input Test Waveform (CY7B9920)
CMOS AC Test Load (CY7B9920)
Notes
6. Total output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B9910:
ICCN = [(4 + 0.11 F) + [((835 – 3 F) / Z) + (.0022 FC)] N] x 1.1
CY7B9920:
ICCN = [(3.5 +.17 F) + [((1160 – 2.8 F) / Z) + (.0025 FC)] N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C.
7. Total power dissipation per output pair is approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit:
CY7B9910:
PD = [(22 + 0.61 F) + [((1550 – 2.7 F) / Z) + (.0125 FC)] N] x 1.1
CY7B9920:
PD = [(19.25+ 0.94 F) + [((700 + 6 F) / Z) + (.017 FC)] N] x 1.1.See note 3 for variable definition.
8. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
9. Applies to REF and FB inputs only.
Document Number: 38-07135 Rev. *F
Page 5 of 15
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CY7B9910
CY7B9920
Switching Characteristics
Over the Operating Range [10]
CY7B9910–2[11]
CY7B9920–2[11]
Parameter
fNOM
Description
Min
Typ
–
Max
Min
Typ
–
Max
Unit
Operating clock
frequency in MHz
FS = LOW[12, 13]
FS = MID[12, 13]
15
25
30
50
15
25
30
50
MHz
–
–
FS = HIGH[12, 13, 14]
40
–
80
40
–
80[15]
tRPWH
tRPWL
tSKEW
tDEV
REF pulse width HIGH
REF pulse width LOW
5.0
5.0
–
–
–
5.0
5.0
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
–
–
–
–
Zero output skew (all outputs)[16, 17]
Device-to-device skew[17, 18]
Propagation delay, REF rise to FB rise
Output duty cycle variation[19]
Output rise time[20, 21]
Output fall time[20, 21]
PLL lock time[22]
0.1
–
0.25
0.75
+0.25
+0.65
1.2
1.2
0.5
200
25
0.1
–
0.25
0.75
+0.25
+0.65
2.5
–
–
tPD
–0.25
–0.65
0.15
0.15
–
0.0
0.0
1.0
1.0
–
–0.25
–0.65
0.5
0.5
–
0.0
0.0
2.0
2.0
–
tODCV
tORISE
tOFALL
tLOCK
tJR
2.5
0.5
Cycle-to-cycle output jitter Peak-to-peak
RMS
–
–
–
–
200
25
–
–
–
–
Notes
10. Test measurement levels for the CY7B9910 are TTL levels (1.5 V to 1.5 V). Test measurement levels for the CY7B9920 are CMOS levels (V / 2 to V / 2).
CC
CC
Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
11. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
12. For all three state inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
CC
circuitry holds an unconnected input to V / 2.
CC
13. The level to be set on FS is determined by the “normal” operating frequency (f
) of the VCO (see Logic Block Diagram). The frequency appearing at the REF
NOM
and FB inputs are f
when the output connected to FB is undivided. The frequency of the REF and FB inputs are f
/ X when the device is configured for
NOM
NOM
a frequency multiplication by using external division in the feedback path of value X.
14. When the FS pin is selected HIGH, the REF input must not transition upon power-up until V reached 4.3 V.
CC
15. Except as noted, all CY7B9920–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load.
16. t
is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50 to
SKEW
2.06 V (CY7B9910) or V / 2 (CY7B9920).
CC
17. t
18. t
is defined as the skew between outputs.
is the output-to-output skew between any two outputs on separate devices operating under the same conditions (V , ambient temperature, air flow, and
so on).
SKEW
DEV
CC
19. t
is the deviation of the output from a 50% duty cycle.
ODCV
20. Specified with outputs loaded with 30 pF for the CY7B99X0–2 and –5 devices and 50 pF for the CY7B99X0–7 devices. Devices are terminated through 50 to
2.06 V (CY7B9910) or V / 2 (CY7B9920).
CC
21. t
22. t
and t
measured between 0.8 V and 2.0 V for the CY7B9910 or 0.8 V and 0.2 V for the CY7B9920.
ORISE
LOCK
OFALL CC CC
is the time that is required before synchronization is achieved. This specification is valid only after V is stable and within normal operating limits. This
parameter is measured from the application of a new signal or frequency at REF or FB until t is within specified limits.
PD
CC
Document Number: 38-07135 Rev. *F
Page 6 of 15
[+] Feedback
CY7B9910
CY7B9920
Switching Characteristics
Over the Operating Range [23]
CY7B9910–5
CY7B9920–5
Parameter
fNOM
Description
Min
15
Typ
–
Max
30
Min
15
25
40
5.0
5.0
–
Typ
–
Max
Unit
Operating clock
frequency in MHz
FS = LOW[24, 25]
FS = MID[24, 25]
FS = HIGH[24, 25, 26]
30
50
MHz
25
–
50
–
40
–
80
–
80[27]
tRPWH
tRPWL
tSKEW
tDEV
REF pulse width HIGH
REF pulse width LOW
5.0
5.0
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
–
–
–
–
Zero output skew (All outputs)[28, 29]
Device-to-device skew[30, 31]
Propagation delay, REF rise to FB rise
Output duty cycle variation[32]
Output rise time[33, 34]
0.25
–
0.5
1.0
+0.5
+1.0
1.5
1.5
0.5
200
25
0.25
–
0.5
1.0
+0.5
+1.0
3.0
3.0
0.5
200
25
–
–
tPD
–0.5
–1.0
0.15
0.15
–
0.0
0.0
1.0
1.0
–
–0.5
–1.0
0.5
0.5
–
0.0
0.0
2.0
2.0
–
tODCV
tORISE
tOFALL
tLOCK
tJR
Output fall time[33, 34]
PLL lock time[35]
Cycle-to-cycle output jitter Peak-to-peak[30]
RMS[30]
–
–
–
–
–
–
–
–
Notes
23. Test measurement levels for the CY7B9910 are TTL levels (1.5 V to 1.5 V). Test measurement levels for the CY7B9920 are CMOS levels (V / 2 to V / 2).
CC
CC
Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
24. For all three state inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
CC
circuitry holds an unconnected input to V / 2.
CC
25. The level to be set on FS is determined by the “normal” operating frequency (f
) of the VCO (see Logic Block Diagram). The frequency appearing at the REF
NOM
and FB inputs are f
when the output connected to FB is undivided. The frequency of the REF and FB inputs are f
/ X when the device is configured for
NOM
NOM
a frequency multiplication by using external division in the feedback path of value X.
26. When the FS pin is selected HIGH, the REF input must not transition upon power up until V reached 4.3 V.
CC
27. Except as noted, all CY7B9920–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load.
28. t
is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50 to
SKEW
2.06 V (CY7B9910) or V / 2 (CY7B9920).
CC
29. t
is defined as the skew between outputs.
SKEW
30. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
31. t is the output-to-output skew between any two outputs on separate devices operating under the same conditions (V , ambient temperature, air flow, and
DEV
so on).
CC
32. t
is the deviation of the output from a 50% duty cycle.
ODCV
33. Specified with outputs loaded with 30 pF for the CY7B99X0–2 and –5 devices and 50 pF for the CY7B99X0–7 devices. Devices are terminated through 50 to
2.06 V (CY7B9910) or V / 2 (CY7B9920).
CC
34. t
35. t
and t
measured between 0.8 V and 2.0 V for the CY7B9910 or 0.8 V and 0.2 V for the CY7B9920.
ORISE
LOCK
OFALL CC CC
is the time that is required before synchronization is achieved. This specification is valid only after V is stable and within normal operating limits. This
parameter is measured from the application of a new signal or frequency at REF or FB until t is within specified limits.
PD
CC
Document Number: 38-07135 Rev. *F
Page 7 of 15
[+] Feedback
CY7B9910
CY7B9920
Switching Characteristics
Over the Operating Range [36]
CY7B9910–7
CY7B9920–7
Parameter
fNOM
Description
Min
15
Typ
–
Max
30
Min
15
25
40
5.0
5.0
–
Typ
–
Max
Unit
Operating clock
frequency in MHz
FS = LOW[37, 38]
FS = MID[37, 38]
FS = HIGH[37, 38, 39]
30
MHz
25
–
50
–
50
40
–
80
–
80[40]
–
tRPWH
tRPWL
tSKEW
tDEV
REF pulse width HIGH
REF pulse width LOW
5.0
5.0
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
–
–
–
–
Zero output skew (All outputs)[41, 42]
Device-to-device skew[43, 44]
Propagation delay, REF Rise to FB Rise
Output duty cycle variation[45]
Output rise time[46, 47]
0.3
–
0.75
1.5
+0.7
+1.2
2.5
2.5
0.5
200
25
0.3
–
0.75
1.5
+0.7
+1.2
5.0
5.0
0.5
200
25
–
–
tPD
–0.7
–1.2
0.15
0.15
–
0.0
0.0
1.5
1.5
–
–0.7
–1.2
0.5
0.5
–
0.0
0.0
3.0
3.0
–
tODCV
tORISE
tOFALL
tLOCK
tJR
Output fall time[46, 47]
PLL lock time[48]
Cycle-to-cycle output
jitter
Peak-to-peak[43]
RMS[43]
–
–
–
–
tJR
–
–
–
–
Notes
36. Test measurement levels for the CY7B9910 are TTL levels (1.5 V to 1.5 V). Test measurement levels for the CY7B9920 are CMOS levels (V / 2 to V / 2).
CC
CC
Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
37. For all three state inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
CC
circuitry holds an unconnected input to V / 2.
CC
38. The level to be set on FS is determined by the “normal” operating frequency (f
) of the VCO (see Logic Block Diagram). The frequency appearing at the REF
NOM
and FB inputs are f
when the output connected to FB is undivided. The frequency of the REF and FB inputs are f
/ X when the device is configured for
NOM
NOM
a frequency multiplication by using external division in the feedback path of value X.
39. When the FS pin is selected HIGH, the REF input must not transition upon power up until V reached 4.3 V.
CC
40. Except as noted, all CY7B9920–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load.
41. t
is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50 to
SKEW
2.06 V (CY7B9910) or V / 2 (CY7B9920).
CC
42. t
is defined as the skew between outputs.
SKEW
43. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
44. t is the output-to-output skew between any two outputs on separate devices operating under the same conditions (V , ambient temperature, air flow, and
DEV
so on).
CC
45. t
is the deviation of the output from a 50% duty cycle.
ODCV
46. Specified with outputs loaded with 30 pF for the CY7B99X0–2 and –5 devices and 50 pF for the CY7B99X0–7 devices. Devices are terminated through 50
to 2.06 V (CY7B9910) or V / 2 (CY7B9920).
CC
47. t
48. t
and t
measured between 0.8 V and 2.0 V for the CY7B9910 or 0.8 V and 0.2 V for the CY7B9920.
ORISE
LOCK
OFALL CC CC
is the time that is required before synchronization is achieved. This specification is valid only after V is stable and within normal operating limits. This
parameter is measured from the application of a new signal or frequency at REF or FB until t is within specified limits.
PD
CC
Document Number: 38-07135 Rev. *F
Page 8 of 15
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CY7B9910
CY7B9920
AC Timing Diagrams
Figure 3. AC Timing Diagrams
tREF tRPWL
t RPWH
REF
tPD
tODCV
tODCV
FB
Q
tSKEW
tJR
tSKEW
Other Q
Figure 4. Zero Skew and Zero Delay Clock Driver
REF
Load
Load
Load
Load
Z0
FB
System
Clock
REF
FS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Z0
Z0
Z0
TEST
Document Number: 38-07135 Rev. *F
Page 9 of 15
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CY7B9910
CY7B9920
Operational Mode Descriptions
Figure 4 on page 9 shows the device configured as a zero skew
clock buffer. In this mode the CY7B9910/CY7B9920 is used as
the basis for a low skew clock distribution tree. The outputs are
aligned and may each drive a terminated transmission line to an
independent load. The FB input is tied to any output and the
operating frequency range is selected with the FS pin. The low
skew specification, coupled with the ability to drive terminated
transmission lines (with impedances as low as 50 ohms),
enables efficient printed circuit board design.
Figure 3 on page 9 shows the CY7B9910/CY7B9920 connected
in series to construct a zero skew clock distribution tree between
boards. Cascaded clock buffers accumulates low frequency jitter
because of the non-ideal filtering characteristics of the PLL filter.
Do not connect more than two clock buffers in series.
Figure 5. Board-to-Board Clock Distribution
REF
Load
Z0
FB
System
Clock
REF
FS
Load
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Z0
Load
Z0
TEST
FB
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Load
Load
REF
FS
Z0
TEST
Document Number: 38-07135 Rev. *F
Page 10 of 15
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CY7B9910
CY7B9920
Ordering Information
Accuracy
Operating
Ordering Code
Package Type
24-Pin Small Outline IC
(ps)
Range
500
CY7B9920–5SC[49]
CY7B9920–5SCT[49]
CY7B9920–5SI[49]
Commercial, 0C to +70 C
Commercial, 0C to +70C
Industrial, –40 C to +85 C
24-Pin Small Outline IC - Tape and Reel
24-Pin Small Outline IC
Pb-free
250
CY7B9910–2SXC
CY7B9910–2SXCT
CY7B9910–5SXC
CY7B9910–5SXCT
CY7B9910–5SXI
CY7B9910–5SXIT
CY7B9910–7SXC
CY7B9910–7SXCT
24-Pin Small Outline IC
Commercial, 0 C to +70 C
Commercial, 0 C to +70 C
Commercial, 0 C to +70 C
Commercial, 0 C to +70 C
Industrial, –40 C to +85 C
Industrial, –40 C to +85 C
Commercial, 0C to +70 C
Commercial, 0 C to +70 C
24-Pin Small Outline IC - Tape and Reel
24-Pin Small Outline IC
500
750
24-Pin Small Outline IC - Tape and Reel
24-Pin Small Outline IC
24-Pin Small Outline IC - Tape and Reel
24-Pin Small Outline IC
24-Pin Small Outline IC - Tape and Reel
Ordering Code Definition
X
S
CY 7B99X0 –
(X)
C
(T)
T = Tape and Reel, blank = Tube
Temperature: C = Commercial; I = Industrial
X = Pb-free, blank = not Pb-free
S = SOIC package
Speed grade: 2 / 5 / 7, based on propagation delay
Base part number
7B9910 = Clock buffer with TTL outputs
7B9920 = Clock buffer with CMOS outputs
Company ID: CY = Cypress
Note
49. Not recommended for new design. New designs should use Pb-free devices.
Document Number: 38-07135 Rev. *F
Page 11 of 15
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CY7B9910
CY7B9920
Package Diagram
Figure 6. 24-Pin (300-Mil) Molded SOIC
NOTE :
1. JEDEC STD REF MO-119
PIN 1 ID
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT
DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE
12
1
MIN.
MAX.
3. DIMENSIONS IN INCHES
4. PACKAGE WEIGHT 0.65gms
0.291[7.391]
0.300[7.620]
*
0.394[10.007]
0.419[10.642]
PART #
S24.3 STANDARD PKG.
SZ24.3 LEAD FREE PKG.
13
24
0.026[0.660]
0.032[0.812]
SEATING PLANE
0.597[15.163]
0.615[15.621]
0.092[2.336]
0.105[2.667]
*
0.004[0.101]
0.0091[0.231]
0.0125[0.317]
*
0.015[0.381]
0.050[1.270]
0.004[0.101]
0.0118[0.299]
0.050[1.270]
TYP.
0.013[0.330]
0.019[0.482]
51-85025 *D
Document Number: 38-07135 Rev. *F
Page 12 of 15
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CY7B9910
CY7B9920
Acronyms
Acronym
FB
Description
feedback
PLL
phase-locked loop
SOIC
VCO
small-outline integrated circuit
Voltage controlled oscillator
Document Conventions
Units of Measure
Symbol
°C
Unit of Measure
degree Celsius
kilohms
k
MHz
µA
mA
ms
mW
ns
megahertz
microamperes
milliamperes
milliseconds
milliwatts
nanoseconds
ohms
%
percent
pF
ppm
ps
picofarads
parts per million
picoseconds
volts
V
Document Number: 38-07135 Rev. *F
Page 13 of 15
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CY7B9910
CY7B9920
Document History Page
Document Title: CY7B9910/CY7B9920 Low Skew Clock Buffer
Document Number: 38-07135
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
**
110244
SZV
10/28/01
Change from Specification number: 38-00437 to 38-07135
*A
1199925 DPF/AESA
See ECN Added Pb-free parts in Ordering Information
Added Note 20: Not recommended for the new design
*B
*C
*D
1353343
2750166
2761988
AESA
TSAI
CXQ
See ECN Change status to final
08/10/09
09/10/09
Post to external web
Fixed typo from 100 W resistor to 100 resistor.
Added “Not recommended for new designs” note to Pb devices.
Fixed incorrect instances of auto-replacement of “lead” to “Pb”.
*E
*F
2896073
3010397
CXQ
KVM
03/19/10
Removed inactive parts from ordering information table
Updated package diagram
08/18/2010 Added ordering code definition
Document Number: 38-07135 Rev. *F
Page 14 of 15
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CY7B9910
CY7B9920
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07135 Rev. *F
Revised September 6, 2010
Page 15 of 15
All products and company names mentioned in this document may be the trademarks of their respective holders.
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相关型号：
CY7B9910-5SXC
7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, 0.300 INCH, LEAD FREE, MO-119, SOIC-24
ROCHESTER
CY7B9910-7SCT
PLL Based Clock Driver, 7B Series, 8 True Output(s), 0 Inverted Output(s), BICMOS, PDSO24, 0.300 INCH, MO-119, SOIC-24
CYPRESS
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