CY62256VLL-70ZXI [ROCHESTER]
32KX8 STANDARD SRAM, 70ns, PDSO28, 8 X 13.40 MM, LEAD FREE, TSOP1-28;
| 型号： | CY62256VLL-70ZXI |
| 厂家： | 
Rochester Electronics |
| 描述： | 32KX8 STANDARD SRAM, 70ns, PDSO28, 8 X 13.40 MM, LEAD FREE, TSOP1-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总13页 (文件大小：1103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62256V
256K (32K x 8) Static RAM
Features
Functional Description[1]
• High Speed
The CY62256V family is composed of two high-performance
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and Tri-state drivers.
These devices have an automatic power-down feature,
reducing the power consumption by over 99% when
deselected.
— 70 ns
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• Low voltage range:
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
— 2.7V – 3.6V
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
• Available in a Pb-free and non Pb-free standard 28-pin
narrow SOIC, 28-pin TSOP-1 and 28-pin Reverse
TSOP-1 packages
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
INPUTBUFFER
A
A
A
10
9
8
A
7
6
5
32K × 8
ARRAY
A
A
A
A
A
4
3
2
CE
WE
POWER
DOWN
COLUMN
DECODER
I/O
7
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05057 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 25, 2006
CY62256V
Product Portfolio
Power Dissipation
Operating, ICC (mA) Standby, ISB2 (µA)
VCC Range (V)
Typ.[2]
Speed
(ns)
70
Product
Range
Min.
Max.
Typ.[2]
Max.
Typ.[2]
Max.
5
CY62256VLL
Com’l/Ind’l
Automotive
2.7
3.0
3.6
11
30
0.1
130
Pin Configurations
Narrow SOIC
Top View
A
5
28
V
CC
1
27 WE
A
A
7
2
3
4
A
8
A
A
A
I/O
I/O
I/O
GND
I/O
I/O
4
I/O
6
7
6
21
11
A
12
13
14
0
1
2
OE
22
0
A
9
26
20
19
18
10
A
1
A
A
23
24
CE
I/O
I/O
4
10
11
12
13
14
15
16
A
9
A
A
5
4
3
A
A
25
3
24
7
6
5
4
2
8
8
7
A
3
25
26
27
28
1
A
A
5
6
9
10
2
17
16
I/O
A
4
A
23
22
A
TSOP I
Reverse Pinout
Top View
1
2
I/O
A
A
CC
TSOP I
WE
6
5
I/O
15
14
13
A
11
OE
1
28
3
V
Top View
7
8
9
10
11
12
13
14
CC
GND
I/O
V
A
5
3
A
0
CE
21
20
19
18
17
A
(not to scale)
12
A
27
26
25
24
23
2
2
3
6
(not to scale)
WE
A
17
18
12
11
13
I/O
1
A
4
A7
A
8
5
I/O
A
A
4
I/O
6
0
I/O
I/O
I/O
3
14
I/O
7
6
5
10
9
A
13
19
20
5
A
2
A
OE
A
14
I/O
7
9
10
A
11
0
A
A
CE
6
7
1
I/O
8
A
21
1
22
A
0
12
I/O
16 I/O
2
4
3
I/O
GND
15
Pin Definitions
Pin Number
1–10, 21, 23–26
11–13, 15–19
27
Type
Description
Input
A0–A14. Address Inputs
Input/Output
Input/Control
I/O0–I/O7. Data lines. Used as input or output lines depending on operation
WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ
is conducted
20
22
Input/Control
Input/Control
CE. When LOW, selects the chip. When HIGH, deselects the chip
OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are Tri-stated, and act as
input data pins
14
28
Ground
GND. Ground for the device
Power Supply
VCC. Power supply for the device
Note:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C, and t = 70 ns.
A AA
CC
CC(typ.)
Document #: 38-05057 Rev. *F
Page 2 of 12
CY62256V
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Temperature (TA)[4]
0°C to +70°C
VCC
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +4.6V
Device
Range
CY62256V Commercial
Industrial
2.7V to 3.6V
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
−40°C to +85°C
−40°C to +125°C
DC Input Voltage[3].................................–0.5V to VCC + 0.5V
Automotive
Electrical Characteristics Over the Operating Range
CY62256V-70
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min. Typ.[2] Max. Unit
IOH = −1.0 mA
VCC = 2.7V
VCC = 2.7V
2.4
2.2
V
V
V
VOL
IOL = 2.1 mA
0.4
VIH
VCC
+0.3V
VIL
IIX
Input LOW Voltage
–0.5
–1
0.8
+1
V
Input Leakage Current
GND < VIN < VCC
Com’l, Ind’l
Automotive
µA
µA
µA
µA
mA
–10
–1
+10
+1
IOZ
Output Leakage Current
GND < VIN < VCC, Output Disabled Com’l, Ind’l
Automotive
–10
+10
30
ICC
VCC Operating Supply Current VCC = 3.6V, IOUT = 0 mA,
f = fMax = 1/tRC
All ranges
11
ISB1
ISB2
Automatic CE Power-down
Current— TTL Inputs
VCC = 3.6V, CE > VIH,
IN > VIH or VIN < VIL, f = fMax
All ranges
100
300
µA
µA
V
Automatic CE Power-down
Current— CMOS Inputs
VCC = 3.6V, CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V, f = 0
Com’l
0.1
0.1
0.1
5
Ind’l
10
Automotive
130
Notes:
3. V (min.) = –2.0V for pulse durations of less than 20 ns.
IL
4. T is the “Instant-On” case temperature.
A
Document #: 38-05057 Rev. *F
Page 3 of 12
CY62256V
Capacitance[5]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz, VCC = VCC(typ.)
6
8
COUT
pF
Thermal Resistance
Parameter
ΘJA
Description
Test Conditions
SOIC
TSOPI
RTSOPI
Unit
Thermal Resistance
Still Air, soldered on a 3 × 4.5 inch,
2-layer printed circuit board
68.45
87.62
87.62
°C/W
(Junction to Ambient)[6]
ΘJC
Thermal Resistance
(Junction to Case)[5]
26.94
23.73
23.73
°C/W
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
90%
OUTPUT
VCC
90%
10%
10%
R2
50 pF
GND
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameter
R1
3.3V
1100
1500
645
Units
Ohms
Ohms
Ohms
Volts
R2
RTH
VTH
1.750
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions[6]
Min.
Typ.[2]
Max.
Unit
V
1.4
VCC = 1.4V, CE > VCC – 0.3V,
IN > VCC – 0.3V or VIN < 0.3V
Com’l
Ind’l
0.1
0.1
0.1
3
6
µA
V
Auto
50
[6]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[6]
tR
Operation Recovery Time
tRC
Data Retention Waveform
DATA RETENTION MODE
> 1.4V
VCC(min)
VCC(min)
V
V
CC
DR
t
t
R
CDR
CE
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.
6. No input may exceed V + 0.3V.
CC
Document #: 38-05057 Rev. *F
Page 4 of 12
CY62256V
Switching Characteristics Over the Operating Range[7]
CY62256V-70
Min. Max.
Parameter
Description
Unit
Read Cycle
tRC
Read Cycle Time
70
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
70
tOHA
tACE
70
35
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
25
25
70
CE HIGH to High-Z[8, 9]
CE LOW to Power-up
CE HIGH to Power-down
tPD
Write Cycle[10, 11]
tWC
tSCE
tAW
Write Cycle Time
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
0
tPWE
tSD
50
30
0
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[8, 9]
WE HIGH to Low-Z[8]
tHD
tHZWE
tLZWE
25
10
Notes:
7. Test conditions assume signal transition time of 5 ns or less timing reference levels of V /2, input pulse levels of 0 to V , and output loading of the specified
CC
CC
I
/I and 50 pF load capacitance.
OL OH
8. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
9. t
, t
, and t
are specified with C = 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
HZOE HZCE
HZWE L
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05057 Rev. *F
Page 5 of 12
CY62256V
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
Read Cycle No. 2 (OE Controlled)[13, 14]
t
RC
CE
t
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
VCC
SUPPLY
CURRENT
t
LZCE
t
PD
t
PU
ICC
50%
50%
ISB
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
NOTE 17
DATA VALID
DATA I/O
IN
t
HZOE
Notes:
12. Device is continuously selected. OE, CE = V .
IL
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
.
IH
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05057 Rev. *F
Page 6 of 12
CY62256V
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA VALID
DATA I/O
IN
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
NOTE 17
DATA VALID
IN
DATA I/O
t
t
LZWE
HZWE
Document #: 38-05057 Rev. *F
Page 7 of 12
CY62256V
Typical DC and AC Characteristics
CURRENT
STANDBY
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.8
3.0
2.5
2.0
1.5
1.0
1.4
V
= 3.0V
CC
1.6
1.4
1.2
1.0
0.8
0.6
1.2
1.0
0.8
V
= 2.5V
CC
TA= 25°C
0.6
0.4
0.2
0.5
0.4
I
SB
0.0
0.2
0.0
–0.5
−55
25
105
−55
25
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
14
12
10
8
2.5
2.0
1.6
1.4
V
= 3.0V
CC
V
= 2.5V
CC
1.2
1.0
1.5
6
TA = 25°C
V
= 2.5 V
CC
1.0
0.5
4
2
T
= 25°C
A
0.8
0
0.0
0.6
−55
0.0
1.65
2.0
OUTPUT VOLTAGE (V)
3.0
1.0
25
125
2.1
2.6
3.1
3.6
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
–14
–12
–10
–8
V
T
= 2.5V
CC
–6
= 25°C
A
–4
0
0.5
1.5
0.0
1.0
2
2.5
OUTPUT VOLTAGE (V)
Document #: 38-05057 Rev. *F
Page 8 of 12
CY62256V
Typical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
NORMALIZED I vs.CYCLETIME
CC
1.25
1.00
0.75
0.50
V
= 3.0V
CC
25.0
TA = 25°C
VCC = 3V
20.0
TA = 25°C
VIN = 0.5V
15.0
10.0
5.0
0.0
20
30
10
1
0
200 400
600 800 1000
CYCLE FREQUENCY (MHz)
CAPACITANCE (pF)
Truth Table
CE
H
L
WE
OE
X
Inputs/Outputs
Mode
Deselect/Power-down
Read
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
X
H
L
High-Z
Data Out
Data In
High-Z
)
L
)
L
X
Write
)
L
H
H
Deselect, Output Disabled
)
Ordering Information
Speed
Package
Diagram
Operating
Ordering Code
CY62256VLL-70SNC
Package Type
(ns)
Range
70
51-85092 28-pin (300-mil Narrow Body) SNC
28-pin (300-mil Narrow Body) SNC (Pb-Free)
51-85071 28-pin TSOP I
Commercial
CY62256VLL-70SNXC
CY62256VLL-70ZC
CY62256VLL-70ZXC
CY62256VLL-70SNXI
CY62256VLL-70ZI
28-pin TSOP I (Pb-Free)
51-85092 28-pin (300-mil Narrow Body) SNC (Pb-Free)
51-85071 28-pin TSOP I
Industrial
CY62256VLL-70ZXI
CY62256VLL-70ZRI
CY62256VLL-70ZRXI
CY62256VLL-70SNE
CY62256VLL-70SNXE
CY62256VLL-70ZE
CY62256VLL-70ZXE
CY62256VLL-70ZRE
CY62256VLL-70ZRXE
28-pin TSOP I (Pb-Free)
51-85074 28-pin Reverse TSOP I
28-pin Reverse TSOP I (Pb-Free)
51-85092 28-pin (300-mil Narrow Body) SNC
28-pin (300-mil Narrow Body) SNC (Pb-Free)
51-85071 28-pin TSOP I
Automotive
28-pin TSOP I (Pb-Free)
51-85074 28-pin Reverse TSOP I
28-pin Reverse TSOP I (Pb-Free)
Please contact your local Cypress sales representative for availability of these parts
Document #: 38-05057 Rev. *F
Page 9 of 12
CY62256V
Package Diagrams
28-pin (300-mil) SNC (Narrow Body) (51-85092)
51-85092-*B
28-pin Thin Small Outline Package Type 1 (8 × 13.4 mm) (51-85071)
51-85071-*G
Document #: 38-05057 Rev. *F
Page 10 of 12
CY62256V
Package Diagrams (continued)
28-pin Reverse Thin Small Outline Package Type 1 (8 × 13.4 mm) (51-85074)
51-85074-*F
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05057 Rev. *F
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62256V
Document History Page
Document Title: CY62256V, 256K (32K x 8) Static RAM
Document Number: 38-05057
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Changed from spec number: 38-00519 to 38-05057
Removed obsolete parts. Change to standard format
Changed SN package diagram
107248
111445
115229
116507
09/10/01
11/01/01
05/23/02
09/04/02
SZV
MGN
GBI
*A
*B
*C
GBI
Added footnote 1
Clarified ICC spec for VCC(typ) = 2.5V
*D
*E
*F
239134
344595
493277
See ECN
See ECN
See ECN
AJU
SYT
VKN
Added Automotive product information
Added Pb-Free packages on page# 10
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed part # CY62256V25LL from the product offering
Updated Ordering Information Table
Document #: 38-05057 Rev. *F
Page 12 of 12
相关型号：
CY62256VNLL-70SNXCT
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28
CYPRESS
CY62256VNLL-70SNXET
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28
CYPRESS
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