CY62256VNLL-70SNXCT [CYPRESS]
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28;
| 型号： | CY62256VNLL-70SNXCT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总13页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62256VN
256K (32K x 8) Static RAM
Features
Functional Description
■
Temperature Ranges
The CY62256VN[1] family is composed of two high performance
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and tristate drivers.
These devices have an automatic power down feature, reducing
the power consumption by over 99% when deselected.
❐
❐
❐
❐
Commercial: 0°C to 70°C
Industrial: –40°C to 85°C
Automotive-A: –40°C to 85°C
Automotive-E: –40°C to 125°C
■
■
■
■
■
■
■
■
Speed: 70 ns
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location addressed
by the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
Low Voltage Range: 2.7V to 3.6V
Low Active Power and Standby Power
Easy Memory Expansion with CE and OE Features
TTL Compatible Inputs and Outputs
Automatic Power Down when Deselected
CMOS for Optimum Speed and Power
The input/output pins remain in a high impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH.
Available in Standard Pb-free and non Pb-free 28-Pin (300-mil)
Narrow SOIC, 28-Pin TSOP-I, and 28-Pin Reverse TSOP-I
Packages
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
INPUTBUFFER
A
A
A
10
9
8
A
7
6
5
A
32K x 8
ARRAY
A
A
A
A
4
3
2
CE
WE
POWER
DOWN
COLUMN
DECODER
I/O
7
OE
.
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06512 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 25, 2009
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CY62256VN
Product Portfolio
Power Dissipation
Operating, ICC (mA) Standby, ISB2 (μA)
VCC Range (V)
Product
Range
Min
2.7
2.7
2.7
2.7
Typ[2]
3.0
Max
3.6
3.6
3.6
3.6
Typ[2]
Max
30
Typ[2]
Max
5
CY62256VNLL
CY62256VNLL
CY62256VNLL
CY62256VNLL
Com’l
Ind’l
11
0.1
3.0
11
30
0.1
10
Automotive-A
Automotive-E
3.0
11
30
0.1
10
3.0
11
30
0.1
130
Pin Configurations
Narrow SOIC
Top View
A
28
V
CC
1
2
3
4
5
A
8
9
A
21
20
7
6
11
A
12
OE
22
23
0
27 WE
26
A
6
A
A
A
1
10
13
CE
I/O
I/O
A
A
10
11
12
13
14
15
16
A
7
19
18
17
16
A
9
A
A
A
5
4
3
14
A
4
24
7
6
5
4
2
I/O
I/O
1
I/O
GND
I/O
I/O
4
I/O
A
A
8
7
0
25
3
24
A
3
25
26
8
I/O
A
4
A
A
5
6
9
10
2
TSOP I
2
I/O
TSOP I
Top View
(not to scale)
27
28
1
WE
2
6
5
A
23
22
A
1
I/O
15
14
13
Reverse Pinout
A
1
28
3
V
CC
A
11
OE
A
0
CE
GND
I/O
V
A
5
Top View
3
7
8
9
10
11
12
13
14
CC
A
2
27
26
25
24
23
2
3
6
21
20
19
18
17
(not to scale)
A
WE
12
12
11
17
18
I/O
1
A
7
A
4
5
A
13
I/O
A
A
4
5
0
I/O
6
8
3
10
9
A
19
20
A
A
14
A
2
A
OE
I/O
7
I/O
14
I/O
9
10
11
7
A
A
13
CE
6
7
I/O
1
6
0
8
A
12
A
21
22
A
0
I/O
I/O
5
1
I/O
16 I/O
15
2
4
3
I/O
GND
Pin Definitions
Pin Number
Type
Description
1–10, 21, 23–26 Input
A0–A14. Address Inputs
I/O0–I/O7. Data lines. Used as input or output lines depending on operation
11–13, 15–19
Input/Output
Input/Control
Input/Control
Input/Control
27
20
22
WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted
CE. When LOW, selects the chip. When HIGH, deselects the chip
OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins
14
28
Ground
GND. Ground for the device
Power Supply
VCC. Power supply for the device
Note
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V Typ, T = 25°C, and t = 70 ns.
CC
CC
A
AA
Document #: 001-06512 Rev. *B
Page 2 of 13
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CY62256VN
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch-up Current.................................................... > 200 mA
Operating Range
Storage Temperature ................................ –65°C to + 150°C
Ambient
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Device
Range
Temperature
VCC
(TA)[4]
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)...........................................–0.5V to + 4.6V
CY62256VN Commercial
Industrial
0
°
C to +70
°
C
2.7V to 3.6V
−40
−40
°
C to +85
°C
DC Voltage Applied to Outputs
in High-Z State[3]....................................–0.5V to VCC + 0.5V
Automotive-A
°C to +85
°C
DC Input Voltage[3] ................................–0.5V to VCC + 0.5V
Automotive-E −40
°
C to +125°C
Output Current into Outputs (LOW)............................. 20 mA
Electrical Characteristics Over the Operating Range
-70
Typ[2]
Parameter
Description
Test Conditions
Unit
Min
Max
VOH
VOL
VIH
VIL
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
IOH = −1.0 mA
VCC = 2.7V
2.4
V
V
IOL = 2.1 mA
VCC = 2.7V
0.4
2.2
–0.5
–1
VCC + 0.3V
V
0.8
+1
V
IIX
GND < VIN < VCC
Com’l/Ind’l/Auto-A
Auto-E
μA
μA
μA
μA
mA
–10
–1
+10
+1
IOZ
Output Leakage Current GND < VIN < VCC, Output
Disabled
Com’l/Ind’l/Auto-A
Auto-E
–10
+10
30
ICC
VCC Operating Supply
Current
VCC = 3.6V, IOUT = 0 mA,
f = fMAX = 1/tRC
All Ranges
11
ISB1
Automatic CE Power
Down Current -
TTL Inputs
VCC = 3.6V, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
All Ranges
100
300
μA
μA
ISB2
Automatic CE Power
Down Current- CMOS
Inputs
VCC = 3.6V, CE > VCC – 0.3V Com’l
0.1
5
V
IN > VCC – 0.3V or VIN < 0.3V,
Ind’l/Auto-A
Auto-E
10
f = 0
130
Notes
3.
4.
V
(min) = –2.0V for pulse durations of less than 20 ns.
is the “Instant-On” case temperature.
IL
T
A
Document #: 001-06512 Rev. *B
Page 3 of 13
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CY62256VN
Capacitance[5]
Parameter
Description
Test Conditions
Test Conditions
Max
6
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = 3.0V
COUT
Output Capacitance
8
pF
Thermal Resistance[5]
Parameter
Description
SOIC
TSOPI RTSOPI
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
68.45
87.62
87.62
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
26.94
23.73
23.73
°C/W
Figure 1. AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
90%
OUTPUT
VCC
90%
10%
10%
R2
50 pF
GND
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
Rth
OUTPUT
Vth
Parameter
R1
Value
1100
1500
645
Units
Ohms
Ohms
Ohms
Volts
R2
RTH
VTH
1.750
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions[6]
Min
Typ[2]
Max
Unit
V
1.4
VCC = 1.4V,
CE > VCC – 0.3V,
IN > VCC – 0.3V
or VIN < 0.3V
Com’l
0.1
3
6
μA
Ind’l/Auto-A
Auto-E
V
50
[6]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[5]
tR
Operation Recovery Time
tRC
Figure 2. Data Retention Waveform
DATA RETENTION MODE
1.8V
1.8V
V
DR
> 1.4V
V
CC
t
t
R
CDR
CE
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. No input may exceed V + 0.3V.
CC
Document #: 001-06512 Rev. *B
Page 4 of 13
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CY62256VN
Switching Characteristics Over the Operating Range[7]
CY62256VN-70
Min Max
Parameter
Description
Unit
Read Cycle
tRC
Read Cycle Time
70
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
CE HIGH to High-Z[8, 9]
CE LOW to Power Up
CE HIGH to Power Down
70
tOHA
tACE
70
35
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
25
25
70
tPD
Write Cycle[10, 11]
tWC
Write Cycle Time
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tAW
tHA
tSA
0
tPWE
tSD
50
30
0
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z[8, 9]
WE HIGH to Low-Z[8]
tHD
tHZWE
tLZWE
25
10
Notes
7. Test conditions assume signal transition time of 5 ns or less timing reference levels of V /2, input pulse levels of 0 to V , and output loading of the specified I /I
CC
CC
OL OH
and 100-pF load capacitance.
8. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
LZWE
HZCE
LZCE HZOE
LZOE
HZWE
9.
t
, t
, and t
are specified with C = 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
HZOE HZCE
HZWE L
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
Document #: 001-06512 Rev. *B
Page 5 of 13
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CY62256VN
Switching Waveforms
Figure 3. Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No. 2[13, 14]
t
RC
CE
OE
t
t
ACE
t
HZOE
t
DOE
t
HZCE
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
VCC
SUPPLY
CURRENT
ICC
ISB
50%
50%
Figure 5. Write Cycle No. 1 (WE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
NOTE 17
DATA VALID
DATA I/O
IN
t
HZOE
Notes
12. Device is continuously selected. OE, CE = V
13. WE is HIGH for read cycle.
.
IL
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
.
IH
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 001-06512 Rev. *B
Page 6 of 13
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CY62256VN
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (CE Controlled)[10, 15, 16]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
NOTE 17
DATA VALID
IN
t
t
LZWE
HZWE
Document #: 001-06512 Rev. *B
Page 7 of 13
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CY62256VN
Typical DC and AC Characteristics
STANDBY CURRENT
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
vs. AMBIENT TEMPERATURE
1.8
1.6
1.4
3.0
2.5
2.0
1.5
1.0
1.4
1.2
1.0
V
= 3.0V
CC
1.2
0.8
0.6
1.0
0.8
TA= 25°C
0.6
0.4
0.2
0.5
0.4
ISB
0.0
0.2
0.0
–0.5
−55
25
105
−55
25
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
14
12
10
8
2.5
2.0
1.6
1.4
V
= 3.0V
CC
1.2
1.0
1.5
6
TA = 25°C
1.0
0.5
4
2
T
= 25°C
A
0.8
0.6
0
0.0
1.65
2.0
OUTPUT VOLTAGE (V)
3.0
0.0
1.0
−55
25
125
2.1
2.6
3.1
3.6
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
–14
–12
–10
–8
–6
T
= 25°C
1.0
A
–4
0
0.5
1.5
0.0
2
2.5
OUTPUT VOLTAGE (V)
Document #: 001-06512 Rev. *B
Page 8 of 13
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CY62256VN
Typical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
NORMALIZED ICC vs. CYCLE TIME
1.25
1.00
0.75
0.50
V
= 3.0V
CC
25.0
TA = 25°C
VCC = 3V
20.0
TA = 25°C
VIN = 0.5V
15.0
10.0
5.0
0.0
20
30
10
1
0
200 400
600 800 1000
CYCLE FREQUENCY (MHz)
CAPACITANCE (pF)
Truth Table
CE
WE
OE
Inputs/Outputs
Mode
Power
H
X
H
L
X
High-Z
Data Out
Data In
High-Z
Deselect/Power Down
Standby (ISB)
L
L
L
L
X
H
Read
Active (ICC
Active (ICC
Active (ICC
)
)
)
Write
H
Deselect, Output Disabled
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
Package Type
28-Pin (300-mil) Narrow SOIC
(ns)
70
CY62256VNLL-70SNC
CY62256VNLL-70SNXC
CY62256VNLL-70ZC
CY62256VNLL-70ZXC
CY62256VNLL-70SNXI
CY62256VNLL-70ZI
51-85092
Commercial
28-Pin (300-mil) Narrow SOIC (Pb-Free)
28-Pin TSOP I
51-85071
28-Pin TSOP I (Pb-Free)
51-85092
51-85071
28-Pin (300-mil) Narrow SOIC (Pb-Free)
28-Pin TSOP I
Industrial
CY62256VNLL-70ZXI
CY62256VNLL-70ZRI
CY62256VNLL-70ZRXI
CY62256VNLL-70ZXA
CY62256VNLL-70SNXE
CY62256VNLL-70ZXE
CY62256VNLL-70ZRXE
28-Pin TSOP I (Pb-Free)
51-85074
28-Pin Reverse TSOP I
28-Pin Reverse TSOP I (Pb-Free)
28-Pin TSOP I (Pb-Free)
51-85071
51-85092
51-85071
51-85074
Automotive-A
Automotive-E
28-Pin (300-mil) Narrow SOIC (Pb-Free)
28-Pin TSOP I (Pb-Free)
28-Pin Reverse TSOP I (Pb-Free)
Contact your local Cypress sales representative for availability of other parts
Document #: 001-06512 Rev. *B
Page 9 of 13
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CY62256VN
Package Diagrams
Figure 8. 28-Pin (300-mil) SNC (Narrow Body) (51-85092)
51-85092-*B
Document #: 001-06512 Rev. *B
Page 10 of 13
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CY62256VN
Figure 9. 28-Pin TSOP 1 (8 × 13.4 mm) (51-85071)
51-85071-*G
Document #: 001-06512 Rev. *B
Page 11 of 13
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CY62256VN
Figure 10. 28-Pin Reverse TSOP 1 (8 × 13.4 mm) (51-85074)
51-85074-*F
Document #: 001-06512 Rev. *B
Page 12 of 13
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CY62256VN
Document History Page
Document Title: CY62256VN 256K (32K x 8) Static RAM
Document Number: 001-06512
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
426504
488954
See ECN
See ECN
NXR
New Data Sheet
*A
NXR
Added Automotive product
Updated ordering Information table
*B
2769239
09/25/09
VKN/AESA Corrected VIL description in the Electrical Characteristics table
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-06512 Rev. *B
Revised September 25, 2009
Page 13 of 13
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CY62256VNLL-70SNXET
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28
CYPRESS
CY62256VNLL-70SNXIT
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28
CYPRESS
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