ADF7011BRUZ-RL7_技术文档

High Performance ISM Band

ASK/FSK/GFSK Transmitter IC

ADF7011

FEATURES

GENERAL DESCRIPTION

Single Chip Low Power UHF Transmitter

Frequency Band

433 MHz to 435 MHz

The ADF7011 is a low power OOK/ASK/FSK/GFSK UHF

transmitter designed for use in ISM band systems. It contains

and integrated VCO and Σ-∆ fractional-N PLL. The output

power, channel spacing, and output frequency are program-

mable with four 24-bit registers. The fractional-N PLL enables

the user to select any channel frequency within the European

433 MHz and 868 MHz bands, allowing the use of the ADF7011

in frequency hopping systems. The fractional-N also allows the

transmitter to operate in the less congested sub-bands of the

868 MHz to 870 MHz SRD band.

868 MHz to 870 MHz

On-Chip VCO and Fractional-N PLL

2.3 V to 3.6 V Supply Voltage

Programmable Output Power

–16 dBm to +12 dBm, 0.3 dB Steps

Data Rates up to 76.8 kbps

Low Current Consumption

29 mA at +10 dBm at 433.92 MHz

Power-Down Mode (<1 ꢀA)

24-Lead TSSOP Package Hooks to External VCO for

< 1.4 GHz Operation

It is possible to choose from the four different modulation

schemes: Binary or Gaussian Frequency Shift Keying (FSK/

GFSK), Amplitude Shift Keying (ASK), or On/Off Keying

(OOK). The device also features a crystal compensation register

that can provide 1 ppm resolution in the output frequency.

Indirect temperature compensation of the crystal can be accom-

plished inexpensively using this register.

APPLICATIONS

Low Cost Wireless Data Transfer

Wireless Metering

Remote Control/Security Systems

Keyless Entry

Control of the four on-chip registers is via a simple 3-wire inter-

face. The devices operate with a power supply ranging from

2.3 V to 3.6 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

C

REG

VCO

CLK

CPV

CP

GND

OUT

DD

C

VCO

OSC1

OSC2

CP

VCO

IN

OUT

V

DD

OOK/ASK

PA

ꢁ CLK

RF

OUT

VCO

RF

GND

DV

DD

ꢁ R

PFD/

CHARGE

PUMP

D

GND

C

REG

LDO

REGULATOR

OOK/ASK

FSK/GFSK

TxCLK

ꢁ FRACTIONAL-N

SIGMA-DELTA

TxDATA

LOCK DETECT

MUXOUT

LE

DATA

CLK

MUXOUT

FREQUENCY

COMPENSATION

ADF7011

SERIAL

INTERFACE

R

SET

CENTER

FREQUENCY

CE

TEST

A

GND

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

(V_DD= 2.3 V to 3.6 V, GND = 0 V, T_A= T_MINto T_MAX, unless otherwise noted.

ADF7011–SPECIFICATIONS¹^{Typical specifications are at V}_DD= 3 V, T_A= 25؇C, FPFD = 4 MHz @ 433 MHz,

FPFD = 22.1184/5.)

Parameter

Min

Typ

Max

Unit

RF CHARACTERISTICS

Output Frequency Ranges

Lower SRD Band

Upper SRD Band

Phase Frequency Detector Frequency

433

868

3.4

435

870

20

MHz

TRANSMISSION PARAMETERS

Transmit Rate²

FSK

ASK

0.3

76.8

9.6

76.8

kbits/s

GFSK

Frequency Shift Keying

FSK Separation³

1

4.88

110

620

kHz using 3.625 MHz PFD

kHz using 20 MHz PFD

Gaussian Filter ꢀt

Amplitude Shift Keying Depth

On/Off Keying

0.5

28

40

dB

Output Power (No Filtering)⁴

868 MHz

3

10

dBm

433 MHz

Output Power Variation

Max Power Setting

Programmable Step Size

–16 dBm to +12 dBm

9

12

11

9.5

dBm V_DD= 3.6 V

dBm V_DD= 3.0 V

dBm V_DD= 2.3 V

0.3125

dB

LOGIC INPUTS

V_INH, Input High Voltage

V_INL, Input Low Voltage

I_INH/I_INL, Input Current

0.7 ꢁ V_DD

DV_DD– 0.4

2.3

V

µA

pF

MHz

0.2 ꢁ V_DD

ꢂ1

10

50

C

_IN, Input Capacitance

Control Clock Input

LOGIC OUTPUTS

V_OH, Output High Voltage

V_OL, Output Low Voltage

CLK_OUTRise/Fall Time

CLK_OUTMark: Space Ratio

V, I_OH= 500 µA

0.4

3.6

V, I_OL= 500 µA

16

50:50

ns F_CLK= 4.8 MHz into 10 pF

POWER SUPPLIES

Voltage Supply

DV_DD

V

Transmit Current Consumption

433 MHz

0 dBm (1 mW)

10 dBm (10 mW)

868 MHz

17

29

mA

0 dBm (1 mW)

3 dBm (2 mW)

19

20.5

34

mA

10 dBm (10 mW)

Crystal Oscillator Block Current

Consumption

Regulator Current Consumption

Power-Down Mode

Low Power Sleep Mode

190

280

µA

0.2

1

µA

–2–

REV. 0

ADF7011

Parameter

Min

Typ

Max

Unit

PHASE-LOCKED LOOP

VCO Gain 433 MHz/868 MHz

40/80

MHz/V @ 868 MHz

Phase Noise (In-Band)⁵433 MHz

Phase Noise (Out-of-Band)⁶

–81

–90

–83

–95

dBc/Hz @ 5 kHz offset

dBc/Hz @ 1 MHz offset

dBc/Hz @ 5 kHz offset

dBc/Hz @ 1 MHz offset

100 kHz loop BW

Phase Noise (In-Band)⁷868 MHz

Phase Noise (Out-of-Band)⁸

Spurious^{9, 10}

47–74, 87.5–118, 174–230, 470–862 MHz

9 kHz – 1 GHz

–54

–36

–30

dBm

Above 1 GHz

dBm. Assumes external harmonic filter.

Harmonics¹⁰

Second Harmonic, 433 MHz/868 MHz

Third Harmonic, 433 MHz/868 MHz

Other Harmonics, 433 MHz/868 MHz

–23/–28

–25/–29

–26/–40

–20/–23

–22/–25

–23/–35

dBc

REFERENCE INPUT

Crystal Reference

433 MHz

1.7

3.4

22.1184

MHz

868 MHz

External Oscillator

Frequency

Input Level, High Voltage

Input Level, Low Voltage

3.4

0.7 V_DD

40

MHz

V

0.2 V_DD

FREQUENCY COMPENSATION

Pull In Range of Register

1

100

ppm

PA CHARACTERISTICS

RF Output Impedance

868 MHz

16 – j33

25 – j2.6

ꢀ, Z_REF= 50 ꢀ

433 MHz

TIMING INFORMATION

Chip Enabled to Regulator Ready¹⁰

Crystal Oscillator to CLK_OUTOK

4 MHz Crystal

50

200

+85

µs

1.8

2.2

ms

22.1184 MHz Crystal

TEMPERATURE RANGE – T_A

–40

ꢁC

NOTES

¹Operating temperature range is as follows: –40ꢁC to +85ꢁC.

²Datarates should be limited to adhere to edge of band requirements in accordance with ETSI 300-220

³Frequency Deviation = (PFD Frequency ꢂ Mod Deviation )/2¹²

.

GFSK Frequency Deviation = (PFD Frequency ꢂ 2^m)/2¹²where m = Mod Control.

⁴The output power is limited by the spurious requirements of ETSI at +55ꢁC. The addition of an output filter (see Applications section) will allow increased output

levels to >10 dBm at both 433 MHz and 868 MHz

⁵V_DD= 3 V, PFD = 4 MHz, PA = 10 dBm

⁶V_DD= 3 V, Loop Filter BW = 100 kHz

⁷V_DD= 3 V, PFD = 4.42368 MHz, PA = 3 dBm

⁸V_DD= 3 V, Loop Filter BW = 100 kHz

⁹These spurious levels are based on a maximum output power of +3 dBm for 868 MHz and +10 dBm for 433 MHz. It assumes a PFD frequency of <5 MHz.

Recommended PFD frequencies are 4.42368 MHz (22.1184/5) for 868 MHz, and 4 MHz for 433 MHz operation. Compliance for higher output powers will require

an external filter. See Applications section.

¹⁰Not production tested. Based on characterization.

Specifications subject to change without notice.

REV. 0

–3–

ADF7011

(V_DD= 3 V ؎ 10%; VGND = 0 V, T_A= 25؇C, unless otherwise noted.)

TIMING CHARACTERISTICS

Limit at

T_MINto T_MAX

(B Version)

Parameter

Unit

Test Conditions/Comments

t₁

t₂

t₃

t₄

t₅

t₆

10

25

10

20

ns min

DATA to CLOCK Setup Time

DATA to CLOCK Hold Time

CLOCK High Duration

CLOCK Low Duration

CLOCK to LE Setup Time

LE Pulsewidth

Guaranteed by design but not production tested.

Specifications subject to change without notice.

t₃

t₄

CLOCK

t₁

t₂

DB0 (LSB)

(CONTROL BIT C1)

DB1

DATA

LE

DB23 (MSB)

DB22

DB2

(CONTROL BIT C2)

t₆

t₅

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS^{1, 2}

(T_A= 25°C, unless otherwise noted.)

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

V_DDto GND³. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to + 7 V

CPV_DDto GND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to + 7 V

Digital I/O Voltage to GND . . . . . . . –0.3 V to DV_DD+ 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C

TSSOP ꢃ_JAThermal Impedance . . . . . . . . . . . . . . 150.4°C/W

Lead Temperature, Soldering

²This device is a high performance RF integrated circuit with an ESD rating of

<1 kV and is ESD sensitive. Proper precautions should be taken for handling and

assembly.

³GND = VCOGND = CPGND = RFGND = DGND = AGND = 0 V.

ORDERING GUIDE

Temperature

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Model

Range

Package Option

ADF7011BRU

ADF7011BRU-REEL

ADF7011BRU-REEL7 –40ºC to +85ºC

–40ºC to +85ºC

RU-24 (TSSOP)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

ADF7011 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

–4–

REV. 0

ADF7011

PIN CONFIGURATION

1

2

24

23

22

21

20

19

18

17

R

C

REG

SET

CPV

C

VCO

DD

3

CP

VCO

GND

IN

TSSOP

4

CP

A

GND

OUT

5

CE

RF

DV

OUT

GND

DD

ADF7011

6

DATA

CLK

TOP VIEW

(Not to Scale)

7

8

LE

TEST

TxDATA

TxCLK

MUXOUT

9

16 VCO

GND

10

11

12

15

14

13

OSC1

OSC2

CLK

D

GND

OUT

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic

Function

1

R_SET

External Resistor to Set Change Pump Current and Some Internal Bias Currents. Use 4.7 kΩ as default:

9.5

R_SET

I_{CP MAX}

=

So, with R_SET= 4.7 kΩ, I_{CP MAX}= 2.02 mA.

2

CPV_DD

Charge Pump Supply. This should be biased at the same level as RF_OUTand DV_DD. The pin should be

decoupled with a 0.1 µF capacitor as close to the pin as possible.

3

4

CP_GND

CP_OUT

Charge Pump Ground.

Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The

integrated current changes the control voltage on the input to the VCO.

5

6

7

8

CE

Chip Enable. A logic low applied to this pin powers down the part. This must be high for the part to

function. This is the only way to power down the regulator circuit.

DATA

CLK

LE

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a

high impedance CMOS input.

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one

of the four latches, the latch being selected using the control bits.

9

TxDATA

TxCLK

Digital data to be transmitted is input on this pin.

10

GFSK Only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the

ADF7011. The clock is provided at the same frequency as the data rate.

11

MUXOUT

This multiplexer output allows either the digital lock detect (most common), the scaled RF, or the scaled

reference frequency to be accessed externally. Used commonly for system debug. See the Function Regis-

ter Map.

12

13

D_GND

Ground Pin for the RF Digital Circuitry.

CLK_OUT

The Divided Down Crystal Reference with 50:50 Mark-Space Ratio. May be used to drive the clock

input of a microcontroller. To reduce spurious components in the output spectrum, the sharp edges can

be reduced with a series RC. For 4.8 MHz output clock, a series 50 Ω into 10 pF will reduce spurs to

< –50 dBc. Defaults on power-up to divide by 16.

14

OSC2

Oscillator Pin. If a single-ended reference (such as a TCXO) is used, it should be applied to this pin.

When using an external signal generator, a 51 Ω resistor should be tied from this pin to ground. The

XOE bit in the R register should set high when using an external reference.

REV. 0

–5–

ADF7011

PIN FUNCTION DESCRIPTIONS (continued)

Pin No. Mnemonic

Function

15

OSC1

Oscillator Pin. For use with crystal reference only. This is three-stated when an external reference oscilla-

tor is used.

16

17

VCO_GND

TEST

Voltage Controlled Oscillator Ground.

Input to the RF Fractional-N Divider. This pin allows the user to connect an external VCO to the part.

Disabling the internal VCO activates this pin. If the internal VCO is used, this pin should be grounded.

18

DV_DD

Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors

to the analog ground plane should be placed as close as possible to this pin.

19

20

RF_GND

RF_OUT

Ground for Output Stage of Transmitter.

The modulated signal is available at this pin. Output power levels are from –16 dBm to +12 dBm. The

output should be impedance matched to the desired load using suitable components. See the RF Output

Stage section.

21

22

A_GND

Ground Pin for the RF Analog Circuitry.

VCO_IN

The tuning voltage on this pin determines the output frequency of the Voltage Controlled Oscillator

(VCO). The higher the tuning voltage, the higher the output frequency.

23

24

C_VCO

C_REG

A 0.22 µF capacitor should be added to reduce noise on VCO bias lines. Tied to the C_REGpin.

A 2.2 µF capacitor should be added at C_REG, tied to GND, to reduce regulator noise and improve

stability. A reduced capacitor will improve regulator power-on time but may cause higher spurious

components.

–6–

REV. 0

Typical Performance Characteristics–ADF7011

RL = 10.0dBm

885.000MHz

868.000MHz

V

= 3V

DD

PFD FREQUENCY = 19.2MHz

LOOP BW = 100kHz

V

= 3V

DD

PFD FREQUENCY = 19.2MHz

LOOP BW = 100kHz

RBW = 1kHz

851.000MHz

–20.00ꢀs

5.00ꢀs

5.00ꢀs/DIV

30.00ꢀs

868.3MHz

SPAN 5.000MHz

TPC 1. FSK Modulated Signal, F_DEVIATION= 58 kHz,

Data Rate = 19.2 kbps, 10 dBm

TPC 4. PLL Settling Time, 852 MHz to 878 MHz,

23 ꢂs ( 400 kHz)

+10dBm

RL = 10.0dBm

V

= 3V

DD

–2dBm

PFD FREQUENCY = 19.2MHz

LOOP BW = 1MHz

RBW = 3kHz

V

= 3V

DD

PFD FREQUENCY = 19.2MHz

LOOP BW = 100kHz

RBW = 100kHz

–36dBm

@ 200kHz

+19.2MHz

–61dBc

868.3MHz

SPAN 500kHz

RBW 100kHz

868.3MHz

SPAN 50.00MHz

TPC 2. OOK Modulated Signal, Data Rate = 4.8 kbps,

4 dBm

TPC 5. PFD Spurious/Fractional Spurious Components

+10dBm

SECOND HARMONIC

–22dBc

V

= 3V

DD

PFD FREQUENCY = 19.2MHz

LOOP BW = 100kHz

RBW = 30Hz

THIRD HARMONIC

–34dBc

PN @ 4kHz

80dBc/Hz

START 800MHz

RBW 1.0MHz

STOP 7.750GHz

868.3MHz

SPAN 10.00kHz

TPC 3. Harmonic Levels at 10 dBm Output Power.

See Figure 15.

TPC 6. In-Band Phase Noise

REV. 0

–7–

ADF7011

110

100

90

C1 FREQ

1.6MHz

V

= 3V

DD

C1 RISE

144.8ns

C1 FALL

145.6ns

C1 +DUTY

49.385%

T

= 25ꢃC

A

80

70

60

50

40

Ch1 500mV

M 200ns

885

895

905

915

925

935

945

FREQUENCY (MHz)

TPC 10. Typical VCO Gain

TPC 7. 1.6 MHz CLOCK_OUTWaveform

20

15

V

DD

= 2.2V

+10dBm

V

= 3.0V

= 3.6V

DD

V

= 3V

DD

V

DD

PFD FREQUENCY = 19.2MHz

LOOP BW = 100kHz

RBW = 10Hz

10

LOW RANGE

MID RANGE

5

0

+1.6MHz

–53dBc

HIGH RANGE

–5

–10

–15

–20

–25

–30

868.3MHz

SPAN 5.00MHz

40

60

80

100

120

PA SETTING (Modulation Register)

TPC 11. PA Output Programmability, T_A= 25°C

TPC 8. Spurious Signal Generated by CLOCK_OUT

0

44

42

–5

–10

–15

–20

–25

40

38

36

34

32

30

0.8

0.9

1.0

1.1

1.2

1.3

1.4

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

FREQUENCY (GHz)

SUPPLYVOLTAGE (V)

TPC 9. N-Divider Input Sensitivity

TPC 12. I_DDvs. V_DD@ 10 dBm

–8–

REV. 0

ADF7011

REGISTER MAPS

RF R REGISTER

CONTROL

BITS

CLK

11-BIT FREQUENCY ERROR CORRECTION

4-BIT R-VALUE

RESERVED

OUT

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

C1 (0)

F1 C2 (0)

R2

R1

CL4 CL3 CL2 CL1

X1

R4

R3

R2

R1

F11 F10 F9

F8

F7

F6

F5

F4

F3

F2

RF N REGISTER

CONTROL

BITS

8-BIT INTEGER-N

12-BIT FRACTIONAL-N

DB19

DB14 DB13

DB3

M2

DB22 DB21 DB20

DB17

N4

DB8

M7

DB6 DB5

M5 M4

DB4

M3

DB2 DB1

M1

DB23

DB18

N5

DB16 DB15

N3 N2

DB12 DB11 DB10 DB9

M11 M10 M9 M8

DB7

M6

DB0

LDP V1

N8

N7

N6

N1

C1 (1)

M12

C2 (0)

MODULATION REGISTER

INDEX

COUNTER

GFSK MOD

CONTROL

MODULATION

SCHEME

CONTROL

BITS

MODULATION DEVIATION

POWER AMPLIFIER

DB13

DB22

IC2

DB21 DB20

DB18 DB17 DB16 DB15

DB12

D2

DB11 DB10

DB8 DB7 DB6 DB5 DB4 DB3

DB1

DB23

P1

DB19

DB14

D4

DB9

P6

DB2

S1

DB0

C1 (0)

C2 (1)

IC1

MC3 MC2 MC1

D7

D6

D5

D3

D1

P7

P5

P4

P3

P2

P1

S2

FUNCTION REGISTER

CHARGE

PUMP

CONTROL

BITS

FAST LOCK

TEST MODES

MUXOUT

DB19

T5

DB14

DB10

DB9

DB23 DB22 DB21 DB20

T9 T8 T7 T6

DB15

T1

DB2

PD1

DB1

DB0

DB17 DB16

DB13 DB12 DB11

DB8 DB7 DB6 DB5

I1

DB3

PD2

DB18

T4

DB4

PD3

M1

T3

T2

M4

M3

VP1 CP4 CP3 CP2 CP1

C1 (1)

C2 (1)

M2

REV. 0

–9–

ADF7011

RF R Register

CONTROL

BITS

CLK

4-BIT R-VALUE

11-BIT FREQUENCY ERROR CORRECTION

RESERVED

DB23 DB22

OUT

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB21

DB0

C1 (0)

F1 C2 (0)

R2

R1

CL4 CL3 CL2 CL1

X1

R4

R3

R2

R1

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

X1

XOE

F-COUNTER

F11

...........

F3

F2

F1

OFFSET

0

1

XTAL OSCILLATOR ON

XTAL OSCILLATOR OFF

0

...........

1

.

0

1

.

0

1

0

.

1

0

ꢄ1023

ꢄ1022

.

ꢄ1

ꢄ0

.........................................................................................................................................................

1

...........

1

.

0

1

.

0

1

0

.

1

0

ꢅ1

ꢅ2

.

ꢅ1023

ꢅ1024

1

e.g., F-COUNTER OFFSET = ꢅ1, FRACTIONAL OFFSET = ꢅ1/2¹⁵

RF R COUNTER

DIVIDE RATIO

R1

R4

R3

R2

0

.

0

1

.

0

1

0

.

1

0

1

0

.

1

2

3

4

.

CLK

DIVIDE RATIO

OUT

CL3

CL2

CL4

CL1

0

.

1

0

1

.

1

0

1

0

.

0

1

0

1

0

.

0

2

4

6

8

.

1

.

1

.

0

.

0

.

12

1

0

1

0

1

13

14

15

.

24

1

0

1

0

1

26

28

30

–10–

REV. 0

ADF7011

RF N Register

CONTROL

BITS

12-BIT FRACTIONAL-N

8-BIT INTEGER-N

DB19

DB14 DB13

DB3

M2

DB22 DB21 DB20

DB17

N4

DB8

M7

DB6 DB5 DB4

M5 M4 M3

DB2 DB1

M1

DB23

DB18

N5

DB16 DB15

DB12 DB11 DB10 DB9

M11 M10 M9 M8

DB7

M6

DB0

LDP V1

N8 N7

N6

N3

N2

N1

C1 (1)

M12

C2 (0)

e.g., SETTING F = 0 IN FSK MODE TURNS ON THE

ꢄ-ꢅ WHILE THE PLL IS AN INTEGER VALUE

MODULUS

DIVIDE RATIO

M12

M11

M10

..........

M3

M2

M1

0

.

0

.

0

.

..........

1

.

0

1

.

0

1

0

.

4

5

6

.

1

0

4092

1

..........

1

0

1

0

1

4093

4094

4095

e.g., MODULUS DIVIDE RATIO = 2048 –> FRACTION 1/2

N COUNTER

DIVIDE RATIO

N8

N7

N6

N5

N4

N3

N2

N1

0

.

0

.

0

1

.

1

0

.

1

0

.

1

0

.

1

0

1

.

1

0

1

0

.

31

32

33

34

.

1

0

1

253

1

0

1

254

255

VCO BAND

(MHz)

V1

0

1

866–870

433–435

THE N VALUE CHOSEN IS A MINIMUM OF

2

P

+ 3P + 3. FOR PRESCALER = 8/9, THIS

MEANS A MINIMUM N DIVIDE OF 91.

LOCK DETECT

PRECISION

LDP

0

1

3 CYCLES < 15ns

5 CYCLES < 15ns

REV. 0

–11–

ADF7011

Modulation Register

MODULATION CONTROL

SCHEM

INDEX

COUNTER

GFSK MOD

CONTROL

MODULATION DEVIATION

POWER AMPLIFIER

E

BITS

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P1 IC2 IC1 MC3 MC2 MC1 D7 D6 D5 D4 D3 D2 D1 P7 P6 P5 P4 P3 P2 P1 S2 S1 C2 (1) C1 (0)

MODULATION

SCHEME

S2

S1

0

1

0

1

0

1

FSK

GFSK

ASK

OOK

POWER AMPLIFIER OUTPUT LEVEL

IF AMPLITUDE SHIFT KEYING SELECTED, TxDATA = 0

P7

P6

.

P2

P1

D7

D6

.

D2

D1

0

.

0

1

.

1

0

1

.

1

0

.

0

1

.

X

0

.

1

0

.

1

0

.

X

0

1

.

1

0

1

.

1

0

1

.

PA OFF

ꢅ16.0dBm

ꢅ16ꢄ1ꢂ(10/32)

.

ꢅ16ꢄ31ꢂ(10/32)

ꢅ6dBm

ꢅ6ꢄ1ꢂ(10/32)

.

ꢅ6ꢄ1ꢂ(10/32)

2dBm

2ꢄ1ꢂ(10/32)

.

0

.

0

1

.

1

0

1

.

1

0

.

0

1

.

X

0

.

1

0

.

1

0

.

X

0

1

.

1

0

1

.

1

0

1

.

PA OFF

.

ꢅ16.0dBm

ꢅ16ꢄ1ꢂ(10/32)

.

ꢅ16ꢄ31ꢂ(10/32)

ꢅ6dBm

ꢅ6ꢄ1ꢂ(10/32)

.

ꢅ6ꢄ1ꢂ(10/32)

2dBm

2ꢄ1ꢂ(10/32)

.

12dBm

P1

RF PRESCALER

1

12dBm

1

0

1

4/5

8/9

IF FREQUENCY SHIFT KEYING SELECTED

12

/2

F

= F

PFD

STEP

D7.

.

D3

D2

D1

F DEVIATION

PLL MODE

1 ꢂ F

2 ꢂ F

3 ꢂ F

0 .

.

0

1

0

1

0

1

.

STEP

0 .

.

1

.

1

.

1

...............

127 ꢂ F

1 .

.

STEP

IF GAUSSIAN FREQUENCY SHIFT KEYING SELECTED

D7

D3

D2

D1

DIVIDER FACTOR

INDEX

COUNTER

IC2

IC1

0

.

0

.

0

1

.

0

1

0

1

.

0

1

2

3

......

127

0

1

0

1

0

1

16

32

64

128

1

GFSK MOD

CONTROL

MC3

MC2

MC1

0

1

0

1

.

1

7

–12–

REV. 0

ADF7011

Function Register

CONTROL

BITS

CHARGE

PUMP

FAST LOCK

TEST MODES

MUXOUT

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

DB7 DB6

DB5

I1

DB4

PD3

DB3

PD2

DB2

PD1

DB1

DB0

T9

T8

T7

T6

T5

T4

T3

T2

T1

M4

M3

M2

M1

VP1

CP4

CP3

C2

C1

C2 (1) C1 (1)

I1

0

DATA INVERT

DATA

VP1

0

VCO DISABLE

VCO ON

1

DATA

1

VCO OFF

CP4

CP FLOCK DOWN

PD1

PLL ENABLE

0

1

BLEED OFF

BLEED ON

0

1

PLL OFF

PLL ON

CP3

CP FLOCK UP

PD2

PA ENABLE

PA OFF

0

1

BLEED OFF

BLEED ON

0

1

PA ON

CP2

CP1

R

I

(mA)

CP

SET

2.7kꢆ

4.7kꢆ

10kꢆ

0

1

0

1

0

1

0.50

1.50

2.51

3.51

0.29

0.87

1.44

2.02

0.14

0.41

0.68

0.95

PD3

CLK

ENABLE

OUT

0

1

CLK

OFF

ON

OUT

M4

M3

M2

M1

MUXOUT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LOGIC LOW

LOGIC HIGH

THREE-STATE

REGULATOR READY (DEFAULT)

DIGITAL LOCK DETECT

ANALOG LOCK DETECT

R DIVIDER / 2 OUTPUT

N DIVIDER / 2 OUTPUT

RF R DIVIDER OUTPUT

RF N DIVIDER OUTPUT

DATA RATE

LOGIC LOW

NORMAL TEST MODES

ꢃ-ꢄ TEST MODES

REV. 0

–13–

ADF7011

Default Values for Registers

R REGISTER

CONTROL

BITS

11-BIT FREQUENCY ERROR CORRECTION

4-BIT R-VALUE

RESERVED

DB23 DB22

CLK

OUT

DB20 DB19

DB21

1

DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

1

DB7 DB6

DB5 DB4 DB3 DB2 DB1

DB0

C1 (0)

C2 (0)

0

N REGISTER

CONTROL

BITS

8-BIT INTEGER-N

12-BIT FRACTIONAL-N

DB23

0

DB18

0

DB16 DB15

DB12 DB11 DB10 DB9

DB7

0

DB0

DB19

0

DB14 DB13

DB3

0

DB22 DB21 DB20

DB17

0

DB8

0

DB6 DB5 DB4

DB2 DB1

0

1

0

C2 (0) C1 (1)

1

MODULATION REGISTER

INDEX

COUNTER

CONTROL

BITS

GFSK MOD

CONTROL

MODULATION

SCHEME

MODULATION DEVIATION

POWER AMPLIFIER

DB13

DB22

0

DB18 DB17 DB16 DB15

DB12

0

DB11 DB10

DB8 DB7 DB6 DB5 DB4

DB3

DB2

DB1

DB23

DB21 DB20

DB19

0

DB14

0

DB9

1

DB0

0

1

C1 (0)

0

C2 (1)

1

FUNCTION REGISTER

CONTROL

BITS

CHARGE

PUMP

FAST LOCK

TEST MODES

MUXOUT

DB19

0

DB14

DB10

0

DB9

0

DB23 DB22 DB21 DB20

DB15

0

DB2

0

DB1

DB0

DB17 DB16

DB13 DB12 DB11

DB8 DB7 DB6 DB5

DB3

DB18

0

DB4

1

0

1

0

1

0

C1 (1)

C2 (1)

1

–14–

REV. 0

ADF7011

CIRCUIT DESCRIPTION

Prescaler, Phase Frequency Detector (PFD), and

Reference Input Section

Charge Pump

The on-board crystal oscillator circuitry (Figure 2), allows the

use of an inexpensive quartz crystal as the PLL reference. The

oscillator circuit is enabled by setting XOE low. It is enabled by

default on power-up and is disabled by bringing CE low. Two

parallel resonant capacitors are required for oscillation at the

correct frequency; the value of these is dependant on the crystal

specification. Errors in the crystal can be corrected using the

error correction register within the R register. A single-ended

reference (TCXO, CXO) may be used. The CMOS levels should

be applied to OSC2, with XOE set high.

The dual-modulus prescaler (P/P + 1) divides the RF signal

from the VCO to a lower frequency that is manageable by the

CMOS counters.

The PFD takes inputs from the R Counter and the N Counter

(N = Int + Fraction) and produces an output proportional to the

phase and frequency difference between them. Figure 4 is a

simplified schematic.

V

P

CHARGE

PUMP

UP

HI

D1 Q1

U1

OSC2

10pF

R DIVIDER

CLR1

100kꢆ

10pF

100kꢆ

NC

OSC1 500kꢆ

BUFFER

CP

U3

SW1

XTAL OSCILLATOR

DISABLED

TO R COUNTER AND

CLK DIVIDE

OUT

CLR2

Figure 2. Oscillator Circuit on the ADF7011

CLK_OUTDivider and Buffer

DOWN

HI

D2 Q2

U2

The CLK_OUTcircuit takes the reference clock signal from the

oscillator section above and supplies a divided down 50:50 mark-

space signal to the CLK_OUTpin. An even divide from 2 to 30 is

available. This divide is set by the four MSBs in the R register.

On power-up, the CLK_OUTdefaults to divide by 16.

N DIVIDER

CP

GND

R DIVIDER

DV

DD

N DIVIDER

CLK

OUT

ENABLE BIT

CP OUTPUT

DIVIDER

1 TO 15

DIVIDE

BY 2

Figure 4. PFD Stage

The PFD includes a delay element that sets the width of the

CLK

OUT

OSC1

antibacklash pulse. The typical value for this in the ADF7011 is

3 ns. This pulse ensures that there is no dead zone in the PFD

transfer function and minimizes phase noise and reference spurs.

Figure 3. CLK_OUTStage

The output buffer to CLK_OUTis enabled by setting Bit DB4 in

the function register high. On power-up, this bit is set high.

The output buffer can drive up to a 20 pF load with a 10% rise

time at 4.8 MHz. Faster edges can result in some spurious

feedthrough to the output. A small series resistor (50 Ω) can be

MUXOUT and Lock Detect

The MUXOUT pin allows the user to access various internal

points in the ADF7011. The state of MUXOUT is controlled

by Bits M1 to M4 in the function register.

Regulator Ready

used to slow the clock edges to reduce these spurs at F_CLK

.

This is the default setting on MUXOUT after the transmitter

has been powered up. The power-up time of the regulator is

typically 50 µs. Since the serial interface is powered from the

regulator, it is necessary for the regulator to be at its nominal

voltage before the ADF7011 can be programmed. The status

of the regulator can be monitored at MUXOUT. Once the

Regulator Ready signal on MUXOUT is high, programming of

the ADF7011 may begin.

R Counter

The 4-bit R Counter divides the reference input frequency by

an integer from 1 to 15. The divided down signal is presented

as the reference clock to the phase frequency detector (PFD).

The divide ratio is set in the R register. Maximizing the PFD

frequency reduces the N value. Having a higher PFD will

result in a higher level of spurious components. A PFD of

close to 4 MHz is recommended. This reduces the noise multi-

plied at a rate of 20 log(N) to the output, as well as reduces

occurrences of spurious components. The R register defaults

to R = 1 on power-up.

REV. 0

–15–

ADF7011

DV

DD

REGULATOR READY

DIGITAL LOCK DETECT

ANALOG LOCK DETECT

R COUNTER/2 OUTPUT

N COUNTER/2 OUTPUT

R COUNTER OUTPUT

N COUNTER OUTPUT

MUX

CONTROL

MUXOUT

DGND

Figure 5. MUXOUT Stage

Digital Lock Detect

Digital lock detect is active high. The lock detect circuit is con-

tained at the PFD. When the phase error on five consecutive

cycles is less than 15 ns, lock detect is set high. Lock detect

remains high until 25 ns phase error is detected at the PFD.

Since no external components are needed for digital lock detect,

it is more widely used than analog lock detect.

CHARGE

PUMP OUT

VCO

Analog Lock Detect

Figure 6. Typical Loop Filter Configuration––Third

Order Integrator

This N-channel open-drain lock detect should be operated with

an external pull-up resistor of 10 kΩ nominal. When lock has been

detected, this output will be high with narrow low-going pulses.

In FSK, the loop should be designed so that the loop bandwidth

(LBW) is approximately five times the data rate. Widening

the LBW excessively reduces the time spent jumping between

frequencies but may cause insufficient spurious attenuation.

Voltage Regulator

The ADF7011 requires a stable voltage source for the VCO and

modulation blocks. The on-board regulator provides 2.2 V

using a band gap reference. A 2.2 µF capacitor from C_REGto

ground is used to improve stability of the regulator over a sup-

ply ranging from 2.3 V to 3.6 V. The regulator consumes less

than 400 µA and can only be powered down using the chip

enable (CE) pin. Bringing CE low disables the regulator and

also erases all values held in the registers. The serial interface

operates off the regulator supply; therefore, to write to the part,

the user must have CE high. Regulator status can be monitored

using the Regulator Ready signal from MUXOUT.

For ASK systems, the wider the loop BW the better. The sud-

den large transition between two power levels will result in VCO

pulling and can cause a wider output spectrum than is desired.

By widening the loop BW to >10 times the data rate, the amount

of the VCO pulling is reduced since the loop will quickly settle

back to the correct frequency. The wider LBW may restrict the

output power and data rate of ASK based systems, compared

with FSK based systems.

Narrow-loop bandwidths may result in the loop taking long

periods of time to attain lock. Careful design of the loop filter is

critical in obtaining accurate FSK/GFSK modulation.

Loop Filter

The loop filter integrates the current pulses from the charge

pump to form a voltage that tunes the output of the VCO to the

desired frequency. It also attenuates spurious levels generated

by the PLL. A typical loop filter design is shown in Figure 6.

For GFSK, it is recommended that an LBW of 2.0 to 2.5 times

the data rate be used to ensure sufficient samples are taken of

the input data while filtering system noise.

–16–

REV. 0

ADF7011

Voltage Controlled Oscillator (VCO)

LOW

MED

An on-chip VCO is included on the transmitter. The VCO con-

verts the control voltage generated by the loop filter into an output

frequency that is sent to the antenna via the power amplifier

(PA). The VCO has a typical gain of 80 MHz/V and operates

from 866 MHz to 870 MHz. The PD1 bit in the function regis-

ter is the active high bit that turns on the VCO. A frequency

divided by 2 is included to allow operation in the lower 450 MHz

band. To enable operation in the lower band, the V1 bit in the

N Register should be set to 1.

HIGH

The VCO needs an external 220 nF between the VCO and the

regulator to reduce internal noise.

P5

P1

P7, P6

Figure 8. Output Stage

VCO CONTROL BIT

Serial Interface

The serial interface allows the user to program the four 24-bit

registers using a 3-wire interface (CLK, Data, and Load Enable).

The serial interface consists of a level shifter, a 24-bit shift regis-

ter, and four latches. Signals should be CMOS compatible. The

serial interface is powered by the regulator, and therefore is

inactive when CE is low.

TO PA AND

N DIVIDER

MUX

VCO

DIVIDE

BY 2

LOOP FILTER

220nF

Table I. C2, C1 Truth Table

C

REG

C2

C1

Data Latch

0

1

0

1

0

1

R Register

N Register

Modulation Register

Function Register

VCO SELECT BIT

Figure 7. Voltage Controlled Oscillator

RF Output Stage

The RF output stage consists of a DAC with a number of cur-

rent sources to adjust the output power level. To set up the

power level

Data is clocked into the shift register, MSB first, on the rising

edge of each clock (CLK). Data is transferred to one of four

latches on the rising edge of LE. The destination latch is deter-

mined by the value of the two control bits (C2 and C1). These

are the two LSBs, DB1 and DB0, as shown in the timing dia-

gram of Figure 1.

• FSK GFSK: The output power is set using the modulation

Register by entering a 7-bit number into Bits P1–P7. The

two MSBs set the range of the output stage, while the five

LSBs set the output power in the selected range.

V

DD

• ASK: The output power as set up for FSK is the output

power for a TxDATA of 1. The output power for a zero

data bit is set up the same way but using Bits D1–D7.

L1

PA

The output stage is powered down by setting Bit PD2 in the

function register to zero.

L2

C1

RF

50ꢆ

OUT

Figure 9. Output Stage Matching

REV. 0

–17–

ADF7011

The resolution of each register is the smallest amount that the

output frequency can be changed by changing the LSB of the

register.

0.00

0.0

0.20

0.50

1.00

2.00

5.00

25 – j2.6

433MHz

Changing the Output Frequency

The fractional part of the N register changes the output fre-

quency by

ꢅ5.00

ꢅ0.20

ꢅ150

ꢅ140

ꢅ130

PFD Frequency × FractionalRegisterValue

ꢅ30

ꢅ40

2¹²

16 – j33

868MHz

ꢅ2.00

The frequency error correction contained in the R register

changes the output frequency by

ꢅ0.50

ꢅ50

ꢅ120

ꢅ1.00

ꢅ60

ꢅ110

ꢅ70

PFD Frequency × Error CorrectionRegisterValue

ꢅ100

ꢅ80

ꢅ90

2¹⁵

Figure 10. Output Impedance on Smith Chart

Fractional-N

N Counter and Error Correction

The ADF7011 consists of a 15-bit ꢃ-ꢄ fractional-N divider.

The N Counter divides the output frequency to the output

stage back to the PFD frequency. It consists of a prescaler,

integer, and fractional part.

By default, this will be set to 0. The user can calibrate the system

and set this by writing a twos complement number to Bits F1–F11

in the R register. This can be used to compensate for initial error,

temperature drift, and aging effects in the crystal reference.

Integer-N Register

The integer part of the N Counter contains the prescaler and A

and B Counters. It is eight bits wide and offers a divide of

P²+ 3P + 3 to 255.

The prescaler can be 4/5 or 8/9. A prescaler setting of 8/9 is

recommended for 868 MHz operation. A prescaler setting of

4/5 is recommended for 433 MHz operation.

The combination of the integer (255) and the fractional (31767/

31768) gives a maximum N Divider of 256. The minimum

usable PFD is

The output frequency of the PLL is







8 × Fractional + Error

(

)

Maximum Required Output Frequency

PFD Frequency × Int +



2¹⁵

255 + 1

(

)









For use in the European 868 MHz to 870 MHz band, there is a

restriction to using a minimum PFD of 3.4 MHz to allow the

user to have a center frequency of 870 MHz.

REFERENCE IN

PFD/

CHARGE

PUMP

ꢁR

VCO

PFD Frequency

The PFD frequency is the number of times a comparison is

made between the reference frequency and the feedback signal

from the output.

ꢁN

THIRD ORDER

ꢇ-ꢈ MODULATOR

The higher the PFD frequency, the more often a comparison is

made at the PFD. This means that the frequency lock time will

be reduced when jumping from one frequency to another by

increasing the PFD. Having a PFD of > 5 MHz will reduce the

available output power due to EN300-220 spurious regulations.

FRACTIONAL-N

INTEGER-N

Figure 11. Fractional-N PLL

Fractional-N Registers

The fractional part is made up of a 15-bit divide, made up of a

12-bit N value in the N register summed with a 10-bit value

(plus sign bit) in the R register that is used for error correction,

as shown in Figure 12.

M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1

12-BIT NVALUE

ꢉ

F10 F9

F8

F7

F6

F5

F4

F3

N2

F2

N1

F1

N0

10-BIT (ꢄ SIGN) ERROR CORRECTION

N14 N13 N12 N11 N10 N9

N8 N7

N6 N5

N4 N3

15-BIT FRACTIONAL N REGISTER

Figure 12. Fractional Components

–18–

REV. 0

ADF7011

MODULATION SCHEMES

Setting Up the ADF7011 for GFSK

Frequency Shift Keying (FSK)

To set up the frequency deviation, set the PFD and the mod

control Bits MC1 to MC3.

Frequency shift keying is implemented by setting the N value

for the center frequency and then toggling this with the TxDATA

line. The deviation from the center frequency is set using Bits

D1–D7 in the modulation register. The deviation from the

center frequency in Hz is

PFD Frequency × 2^m

GFSK_DEVIATIONHz =

(

)

2¹²

where m is mod control (Bits MC1 to MC3 in the modulation

register).

PFD Frequency × Modulation Number

FSK_DEVIATIONHz =

(

)

2¹²

To set up the GFSK data rate

PFD Frequency

Divider Factor × Index Counter

The modulation number is a number from 1 to 127 (Bits D1–

D7 in modulation register). FSK is selected by setting Bits S1

and S2 to zero in the modulation register.

Data Rate bits/s =

(

)

Amplitude Shift Keying (ASK)

Amplitude shift keying is implemented by switching the output

stage between two discrete power levels. This is implemented by

toggling the DAC, which controls the output level between two

7-bit values set up in the modulation register. A zero TxDATA

bit sends Bits D1–D7 to the DAC. A high TxDATA bit sends

Bits P1–P7 to the DAC. A maximum modulation depth of 30 dB

is possible. ASK is selected by setting Bit S2 = 1 and Bit S1 = 0.

CHEAP AT CRYSTAL

INTERNAL VCO USING

SPIRAL INDUCTORS

GAIN 70 MHz/V–90 MHz/V

PA STAGE

،R

PFD/

CHARGE

PUMP

VCO

FSK DEVIATION

FREQUENCY

On-Off Keying (OOK)

On-off keying is implemented by switching the output stage to a

certain power level for a high TxDATA bit and switching the

output stage off for a zero. Due to feedthrough effects, a maximum

modulation depth of 33 dB is specified. For OOK, the transmitted

power for a high input is programmed using Bits P1–P7 in the

modulation register. OOK is selected by setting Bits S1 and S2

to 1 in the modulation register.

–F

DEV

THIRD ORDER

⌺-⌬

MODULATOR

+F

DEV

TxDATA

FRACTIONAL-N

INTEGER-N

Figure 13. FSK Implementation

CHOOSING CHANNELS FOR BEST SYSTEM

PERFORMANCE

The fractional-N PLL allows the selection of any channel within

868 MHz to 870 MHz to a resolution of <l00 Hz, as well as

facilitating frequency hopping systems.

Gaussian Frequency Shift Keying (GFSK)

Gaussian frequency shift keying reduces the bandwidth occupied

by the transmitted spectrum by digitally prefiltering the TxDATA.

A TxCLK output line is provided from the ADF7011 for syn-

chronization of TxDATA from the microcontroller. The TxCLK

line may be connected to the clock input of an external shift

register that clocks data to the transmitter at exact data rate.

Careful selection of the RF transmit channels must be made to

achieve best spurious performance. The architecture of frac-

tional-N results in some level of the nearest integer channel

moving through the loop to the RF output. These “beat-note”

spurs are not attenuated by the loop if the desired RF channel

and the nearest integer channel are separated by a frequency of

less than the loop BW.

SHIFT

ANTENNA

DATA FROM

REGISTER

TxDATA

MICROCONTROLLER

ADF7011

The occurrence of beat-note spurs is rare, as the integer frequen-

cies are at multiples of the reference, which is typically >4 MHz.

The beat-note spurs can be significantly reduced in amplitude

by avoiding very small or very large values in the fractional

register. By having a channel 1 MHz away from an integer fre-

quency, a 100 kHz loop filter will reduce the level to < –45 dBc.

When using an external VCO, the Fast Lock (bleed) function will

reduce the spurs to < –60 dBc for the same conditions above.

TxCLK

Figure 14. TxCLK Pin Synchronizing Data for GFSK

REV. 0

–19–

ADF7011

APPLICATION EXAMPLES

Application Example 1

In order to meet the ETSI requirement EN300-220, the maxi-

mum output power without using a filter is +3 dBm. This is

because the spurious levels scale with output power. Utilizing a

PFD frequency of 4.42 MHz will reduce the level of the refer-

ence spurs, and place the first spur in a –36 dBm bin, 4.4 MHz

below the carrier. ADIsimPLL should be used to design the

loop filter, aiming for a loop bandwidth of five times the data

rate for FSK. ASK modulation requires a loop BW > 1 MHz to

minimize spectral occupancy.

Operating Frequency

Output Power

Current Consumption

Modulation

433.92 MHz

+10 dBm

<30 mA

ASK/FSK

This system should be set up as shown Figure 15. The spurious

levels using a crystal frequency of 4 MHz are sufficiently low so

as not to require any band-pass filtering of the output. However,

2 dB of attenuation will be required at 541.50 MHz in order

to comply with ES-300-220. This can be achieved easily with

the harmonic filter. The harmonic filter can be designed at the

output of the matching network with 50 Ω impedance, or it

may be integrated into the matching network. The ADF7011

will allow multichannel operation in the 433 MHz band. If

FSK modulation is used, the BW should be about five times

the data rate. In the case of ASK modulation, a minimum

data rate of 1 MHz should be used to minimize the occupied

spectrum. The free design tool, ADIsimPLL, should be down-

loaded from www.analog.com/pll to ascertain the values of the

filter components.

Application Example 3

Operating Frequency

Output Power

Current Consumption

Modulation

868.3 MHz

+10 dBm

<40 mA

ASK/FSK

In order to meet the ETSI requirements at +10 dBm output

power, it is necessary to add an inexpensive GigaFILT from

Murata at the output. This will reduce the prescaler and refer-

ence spurious levels to –54 dBm, and also reduce the harmonic

levels to within the –30 dBm level. Given that the insertion

loss is 2 dB, it is necessary to use the maximum +12 dBm

power from the ADF7011 to achieve an antenna port level of

+10 dBm. The filter layout is important to ensure that there is

margin in the output spectrum; filter data sheet guidelines

should be adhered to.

Application Example 2

Operating Frequency

Output Power

868.3 MHz

+3 dBm

Current Consumption

Modulation

<25 mA

ASK/FSK

–20–

REV. 0

ADF7011

2.2ꢀF

220nF

DV

CPV

DD

C

REG

DD

VCO

R

SET

12nH

6.8nH

4.7kꢆ

10pF

RF

LC FILTER

3.9pF

OUT

VCO

CP

OUT

IN

VCO

IN

ADF7011

TxDATA

LE

CLK

DATA

CE

OSC2

OSC1

4MHz

33pF 33pF

MUXOUT CLK

TEST

GND

OUT

LOCK DETECT

2MHZ CLOCK

50ꢆ

DECOUPLING CAPACITORS HAVE

BEEN OMITTED FOR CLARITY.

Figure 15. Application Diagram—433 MHz Operation with +10 dBm Output Power

2.2ꢀF

220nF

DV

CPV

DD

C

REG

DD

VCO

R

SET

12nH

6.8nH

4.7kꢆ

10pF

RF

OUT

VCO

CP

OUT

IN

VCO

IN

ADF7011

TxDATA

LE

CLK

DATA

CE

OSC2

OSC1

R = 5

22.1184MHz

33pF 33pF

MUXOUT CLK

TEST

GND

OUT

LOCK DETECT

4.84MHZ CLOCK

50ꢆ

DECOUPLING CAPACITORS HAVE

BEEN OMITTED FOR CLARITY.

Figure 16. Application Diagram—868 MHz Operation with +3 dBm Output Power

REV. 0

–21–

ADF7011

2.2ꢀF

220nF

DV

CPV

DD

C

REG

DD

VCO

R

SET

12nH

6.8nH

4.7kꢆ

10pF

RF

OUT

VCO

CP

OUT

IN

VCO

IN

MURATA GigaFILT

DFCB2869MLEJAA-TT1

ADF7011

TxDATA

LE

CLK

DATA

CE

OSC2

OSC1

R = 5

22.1184MHz

33pF 33pF

MUXOUT CLK

TEST

GND

OUT

LOCK DETECT

4.84MHZ CLOCK

50ꢆ

DECOUPLING CAPACITORS HAVE

BEEN OMITTED FOR CLARITY.

Figure 17. Application Diagram—868 MHz Operation with +10 dBm Output Power

–22–

REV. 0

ADF7011

OUTLINE DIMENSIONS

24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

7.90

7.80

7.70

24

13

12

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20

MAX

0.15

0.05

0.75

0.60

0.45

8ꢃ

0ꢃ

0.30

0.19

0.20

0.09

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AD

REV. 0

–23–

–24–


型号：	ADF7011BRUZ-RL7
厂家：	Rochester Electronics
描述：	SPECIALTY TELECOM CIRCUIT, PDSO24, MO-153AD, TSSOP-24 光电二极管
文件：	总25页 (文件大小：1242K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADF7011BRUZ-RL7 [ROCHESTER]

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