AD7933BRU-REEL7 [ROCHESTER]
4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, MO-153-AE, TSSOP-28;
| 型号： | AD7933BRU-REEL7 |
| 厂家： | 
Rochester Electronics |
| 描述： | 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, MO-153-AE, TSSOP-28 光电二极管 转换器 |
| 文件： | 总33页 (文件大小：1577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-Channel, 1.5 MSPS, 10-Bit and 12-Bit
Parallel ADCs with a Sequencer
AD7933/AD7934
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Throughput rate: 1.5 MSPS
V
AGND
DD
Specified for VDD of 2.7 V to 5.25 V
Low power
AD7933/AD7934
V
REFIN/
V
REFOUT
2.5V
6 mW max at 1.5 MSPS with 3 V supplies
13.5 mW max at 1.5 MSPS with 5 V supplies
4 analog input channels with a sequencer
Software configurable analog inputs
4-channel single-ended inputs
2-channel fully differential inputs
2-channel pseudo differential inputs
Accurate on-chip 2.5 V reference
0.2ꢀ max @ 25°C, 25 ppm/°C max (AD7934)
70 dB SINAD at 50 kHz input frequency
No pipeline delays
VREF
V
V
0
IN
IN
CLKIN
12-/10-BIT
SAR ADC
AND
I/P
CONVST
T/H
MUX
CONTROL
BUSY
3
SEQUENCER
V
PARALLEL INTERFACE/CONTROL REGISTER
DRIVE
High speed parallel interface—word/byte modes
Full shutdown mode: 2 μA max
28-lead TSSOP package
DB0 DB11
CS RD WR W/B
DGND
Figure 1.
These parts use advanced design techniques to achieve very low
power dissipation at high throughput rates. They also feature
flexible power management options. An on-chip control
register allows the user to set up different operating conditions,
including analog input range and configuration, output coding,
power management, and channel sequencing.
GENERAL DESCRIPTION
The AD7933/AD7934 are 10-bit and 12-bit, high speed, low
power, successive approximation (SAR) analog-to-digital
converters (ADCs). The parts operate from a single 2.7 V to
5.25 V power supply and feature throughput rates to 1.5 MSPS.
The parts contain a low noise, wide bandwidth, differential track-
and-hold amplifier that handles input frequencies up to 50 MHz.
PRODUCT HIGHLIGHTS
1. High throughput with low power consumption.
2. Four analog inputs with a channel sequencer.
3. Accurate on-chip 2.5 V reference.
4. Single-ended, pseudo differential or fully differential analog
inputs that are software selectable.
The AD7933/AD7934 feature four analog input channels with a
channel sequencer that allow a preprogrammed selection of
channels to be sequentially converted. These parts can accept
either single-ended, fully differential, or pseudo differential
analog inputs.
5. Single-supply operation with VDRIVE function.
The VDRIVE function allows the parallel interface to connect
directly to 3 V or 5 V processor systems independent of VDD
6. No pipeline delay.
.
The conversion process and data acquisition are controlled
using standard control inputs that allow for easy interfacing to
microprocessors and DSPs. The input signal is sampled on the
7. Accurate control of the sampling instant via a
input
CONVST
falling edge of
, and the conversion is also initiated at
and once off conversion control.
CONVST
this point.
Table 1. Related Devices
Similar Device
Bits
Channels
Speed
The AD7933/AD7934 has an accurate on-chip 2.5 V reference
that is used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
AD7938/AD7939 12/10
AD7938-6
AD7934-6
8
8
4
1.5 MSPS
625 kSPS
625 kSPS
12
12
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD7933/AD7934
TABLE OF CONTENTS
Features .............................................................................................. 1
Converter Operation.................................................................. 17
ADC Transfer Function............................................................. 17
Typical Connection Diagram ................................................... 18
Analog Input Structure.............................................................. 18
Analog Inputs ............................................................................. 19
Analog Input Selection .............................................................. 21
Reference Section ....................................................................... 22
Parallel Interface......................................................................... 23
Power Modes of Operation....................................................... 26
Power vs. Throughput Rate....................................................... 27
Microprocessor Interfacing....................................................... 27
Application Hints........................................................................... 29
Grounding and Layout .............................................................. 29
Evaluating the AD7933/AD7934 Performance...................... 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Specifications..................................................................................... 3
AD7933 Specifications................................................................. 3
AD7934 Specifications................................................................. 5
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 13
Control Register.............................................................................. 15
Sequencer Operation ................................................................. 16
Circuit Information........................................................................ 17
REVISION HISTORY
12/05—Rev. 0 to Rev. A
Replaced Figures.................................................................Universal
Changes to General Description .................................................... 1
Changes to Product Highlights....................................................... 1
Added Table 1.................................................................................... 1
Changes to Specifications Section.................................................. 3
Changes to Table 5............................................................................ 9
Changes to Terminology Section.................................................. 13
Changes to Control Register Section ........................................... 15
Changes to Circuit Information Section ..................................... 17
Changes to Application Hints Section......................................... 29
1/05—Revision 0: Initial Version
Rev. A | Page 2 of 32
AD7933/AD7934
SPECIFICATIONS
AD7933 SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. FCLKIN = 25.5 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to
TMAX1, unless otherwise noted.
Table 2.
Parameter
B Version1
Unit
Test Conditions/Comments
FIN = 50 kHz sine wave
Differential mode
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
61
dB min
dB min
dB max
dB max
60
−70
−72
Single-ended mode
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation
Aperture Delay2
fa = 30 kHz, fb = 50 kHz
−86
−90
−75
5
72
50
dB typ
dB typ
dB typ
ns typ
FIN = 50 kHz, FNOISE = 300 kHz
Aperture Jitter2
Full Power Bandwidth2
ps typ
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
10
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity2
Differential Nonlinearity2
Single-Ended and Pseudo Differential Input
Offset Error2
Offset Error Match2
Gain Error2
Gain Error Match2
0.5
0.5
LSB max
LSB max
Guaranteed no missed codes to 10 bits
Straight binary output coding
2
LSB max
LSB max
LSB max
LSB max
0.5
1.5
0.5
Fully Differential Input
Positive Gain Error2
Positive Gain Error Match2
Zero-Code Error2
Zero-Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Twos complement output coding
1.5
0.5
2
0.5
1.5
0.5
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Single-Ended Input Range
0 toVREF
0 to 2 ×VREF
V
V
RANGE bit = 0
RANGE bit = 1
Pseudo Differential Input Range
VIN+
0 to VREF
V
V
V typ
V typ
RANGE bit = 0
RANGE bit = 1
VDD = 3 V
0 to 2 × VREF
−0.3 to +0.7
−0.3 to +1.8
VIN−
VDD = 5 V
Fully Differential Input Range
VIN+ and VIN−
VIN+ and VIN−
DC Leakage Current4
VCM VREF/2
VCM VREF
1
45
10
V
V
VCM = VREF/23, RANGE bit = 0
VCM = VREF3, RANGE bit = 1
μA max
pF typ
pF typ
Input Capacitance
When in track
When in hold
Rev. A | Page 3 of 32
AD7933/AD7934
Parameter
B Version1
Unit
Test Conditions/Comments
1ꢀ specified performance
0.2ꢀ max @ 25ꢁC
REFERENCE INPUT/OUTPUT
VREF Input Voltage5
DC Leakage Current4
VREFOUT Output Voltage
VREFOUT Temperature Coefficient
2.5
1
V
μA max
V
2.5
25
5
10
130
10
15
25
ppm/ꢁC max
ppm/ꢁC typ
μV typ
μV typ
Ω typ
VREF Noise
0.1 Hz to 10 Hz bandwidth
0.1 Hz to 1 MHz bandwidth
VREF Output Impedance
VREF Input Capacitance
pF typ
pF typ
When in track
When in hold
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
5
V min
V max
μA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
4
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
2.4
0.4
3
V min
ISOURCE = 200 μA
ISINK = 200 μA
V max
μA max
pF max
10
Straight (natural) binary
Twos complement
CODING bit = 0
CODING bit = 1
CONVERSION RATE
Conversion Time
t2 + 13 tCLK
ns
Track-and-Hold Acquisition Time
125
80
1.5
ns max
ns typ
MSPS max
Full-scale step input
Sinewave input
Throughput Rate
POWER REQUIREMENTS
VDD
2.7/5.25
2.7 /5.25
V min/max
V min/max
VDRIVE
6
IDD
Digital I/PS = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
FSAMPLE = 100 kSPS, VDD = 5 V
(Static)
Normal Mode (Static)
Normal Mode (Operational)
0.8
2.7
2.0
0.3
160
2
mA typ
mA max
mA max
mA typ
μA typ
Autostandby Mode
Full/Autoshutdown Mode (Static)
Power Dissipation
μA max
SCLK on or off
Normal Mode (Operational)
13.5
6
800
480
10/6
mW max
mW max
μW typ
μW typ
μW max
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V/3 V
Autostandby Mode (Static)
Full/Autoshutdown Mode
1 Temperature range for B Versions: −40ꢁC to +85ꢁC.
2 See Terminology section.
3 VCM is the common mode voltage. For full common-mode range, see Figure 25 and Figure 26. VIN+ and VIN− must always remain within GND/VDD
4 Sample tested during initial release to ensure compliance.
.
5 This device is operational with an external reference in the range of 0.1 V to VDD. See the Reference Section for more information.
6 Measured with a midscale dc analog input.
Rev. A | Page 4 of 32
AD7933/AD7934
AD7934 SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. FCLKIN = 25.5 MHz, FSAMPLE = 1.5 MSPS;
TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
B Version1
Unit
Test Conditions/Comments
FIN = 50 kHz sine wave
Differential mode
Single-ended mode
Differential mode
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
70
dB min
dB min
dB min
dB min
dB max
dB max
dB max
68
71
Signal-to-Noise Ratio (SNR)2
69
Single-ended mode
Total Harmonic Distortion (THD)2
−73
−70
−73
−85 dB typ, differential mode
−80 dB typ, single-ended mode
−82 dB typ
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
fa = 30 kHz, fb = 50 kHz
−86
−90
−85
5
72
50
dB typ
dB typ
dB typ
ns typ
Third-Order Terms
Channel-to-Channel Isolation
Aperture Delay2
Aperture Jitter2
Full Power Bandwidth2
FIN = 50 kHz, FNOISE = 300 kHz
ps typ
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
10
DC ACCURACY
Resolution
12
1
1.5
Bits
LSB max
LSB max
Integral Nonlinearity2
Differential mode
Single-ended mode
Differential Nonlinearity 2
Differential Mode
0.95
−0.95/+1.5
LSB max
LSB max
Guaranteed no missed codes to 12 bits
Guaranteed no missed codes to 12 bits
Straight binary output coding
Single-Ended Mode
Single-Ended and Pseudo Differential Input
Offset Error2
6
1
3
1
LSB max
LSB max
LSB max
LSB max
Offset Error Match2
Gain Error2
Gain Error Match2
Twos complement output coding
Fully Differential Input
Positive Gain Error2
3
1
6
1
3
1
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Positive Gain Error Match2
Zero-Code Error2
Zero-Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Single-Ended Input Range
0 to VREF
0 to 2 × VREF
V
V
RANGE bit = 0
RANGE bit = 1
Pseudo Differential Input Range
VIN+
0 to VREF, or
0 to 2 × VREF
−0.3 to +0.7
−0.3 to +1.8
V
V
V typ
V typ
RANGE bit = 0
RANGE bit = 1
VDD = 3 V
VIN−
VDD = 5 V
Fully Differential Input Range
VIN+ and VIN−
VIN+ and VIN−
VCM VREF/2
VCM VREF
V
V
V
V
CM = VREF/23, RANGE bit = 0
CM = VREF3, RANGE bit = 1
DC Leakage Current4
Input Capacitance
1
45
10
μA max
pF typ
pF typ
When in track
When in hold
Rev. A | Page 5 of 32
AD7933/AD7934
Parameter
REFERENCE INPUT/OUTPUT
VREF Input Voltage5
DC Leakage Current
VREFOUT Output Voltage
VREFOUT Temperature Coefficient
B Version1
Unit
Test Conditions/Comments
1ꢀ specified performance
0.2ꢀ max @ 25ꢁC
2.5
1
2.5
25
5
10
130
10
15
25
V
μA max
V
ppm/ꢁC max
ppm/ꢁC typ
μV typ
μV typ
Ω typ
VREF Noise
0.1 Hz to 10 Hz bandwidth
0.1 Hz to 1 MHz bandwidth
VREF Output Impedance
VREF Input Capacitance
pF typ
pF typ
When in track-and-hold
When in track-and-hold
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
5
V min
V max
μA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
4
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
2.4
0.4
3
V min
ISOURCE = 200 μA
ISINK = 200 μA
V max
μA max
pF max
10
Straight (natural) binary
Twos complement
CODING bit = 0
CODING bit = 1
CONVERSION RATE
Conversion Time
t2 + 13 tCLK
ns
Track-and-Hold Acquisition Time
125
80
1.5
ns max
ns typ
MSPS max
Full-scale step input
Sinewave input
Throughput Rate
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
6
IDD
Digital I/PS = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
FSAMPLE = 100 kSPS, VDD = 5 V
(Static)
Normal Mode (Static)
Normal Mode (Operational)
0.8
2.7
2.0
0.3
160
2
mA typ
mA max
mA max
mA typ
μA typ
Autostandby Mode
Full/Autoshutdown Mode (Static)
Power Dissipation
μA max
SCLK on or off
Normal Mode (Operational)
13.5
6
800
480
10/6
mW max
mW max
μW typ
μW typ
μW max
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V/3 V
Autostandby Mode (Static)
Full/Autoshutdown Mode
1 Temperature range for B Versions: −40ꢁC to +85ꢁC.
2 See the Terminology section.
3 VCM is the common mode voltage. For full common-mode range, see Figure 25 and Figure 26. VIN+ and VIN− must always remain within GND/VDD
4 Sample tested during initial release to ensure compliance.
.
5 This device is operational with an external reference in the range 0.1 V to VDD. See the Reference Section for more information.
6 Measured with a midscale dc analog input.
Rev. A | Page 6 of 32
AD7933/AD7934
TIMING SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. FCLKIN = 25.5 MHz, FSAMPLE = 1.5 MSPS;
TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
Parameter1 AD7933
AD7934
700
25.5
Unit
Description
2
fCLKIN
700
25.5
30
kHz min
MHz max
ns min
CLKIN frequency
tQUIET
30
Minimum time between end of read and start of next conversion, that is, the time
from when the data bus goes into three-state until the next falling edge of CONVST
t1
10
15
50
0
10
15
50
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
CONVST pulse width
t2
CONVST falling edge to CLKIN falling edge setup time
CLKIN falling edge to busy rising edge
CS to WR setup time
t3
t4
t5
0
0
CS to WR hold time
t6
10
10
10
10
0
10
10
10
10
0
WR pulse width
t7
Data setup time before WR
Data hold after WR
t8
t9
New data valid before falling edge of BUSY
CS to RD setup time
t10
t11
t12
0
0
CS to RD hold time
30
30
3
30
30
3
RD pulse width
3
t13
Data access time after RD
Bus relinquish time after RD
Bus relinquish time after RD
HBEN to RD setup time
4
t14
50
0
50
0
t15
t16
t17
t18
t19
t20
t21
t22
0
0
HBEN to RD hold time
10
0
10
0
Minimum time between reads/writes
HBEN to WR setup time
10
40
15.7
7.8
10
40
15.7
7.8
HBEN to WR hold time
CLKIN falling edge to busy falling edge
CLKIN low pulse width
CLKIN high pulse width
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10ꢀ to 90ꢀ of VDD) and timed from a voltage level of 1.6 V.
All timing specifications are with a 25 pF load capacitance (see Figure 35, Figure 36, Figure 37, and Figure 38).
2 Minimum CLKIN for specified performance; with slower SCLK frequencies, performance specifications apply typically.
3 The time required for the output to cross 0.4 V or 2.4 V.
4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
Rev. A | Page 7 of 32
AD7933/AD7934
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to AGND/DGND
−0.3 V to +7 V
VDRIVE to AGND/DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
VDRIVE to VDD
Digital Output Voltage to AGND
VREFIN to AGND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3V to VDRIVE + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +0.3 V
10 mA
AGND to DGND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Reflow Temperature (10 sec to 30 sec)
ESD
−40ꢁC to +85ꢁC
−65ꢁC to +150ꢁC
150ꢁC
97.9ꢁC/W (TSSOP)
14ꢁC/W (TSSOP)
255ꢁC
1.5 kV
1 Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 8 of 32
AD7933/AD7934
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
V
3
DD
IN
W/B
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
V
V
V
V
2
1
0
IN
IN
IN
3
4
AD7933/
AD7934
TOP VIEW
5
V
REFIN/ REFOUT
6
AGND
CS
(Not to Scale)
7
8
RD
9
WR
10
11
12
13
14
CONVST
CLKIN
BUSY
DB11
DB10
V
DRIVE
DGND
DB8/HBEN
DB9
Figure 2. Pin Configuration
Table 6. Pin Function Description
Pin No.
Mnemonic
Description
1
VDD
Power Supply Input. The VDD range for the AD7933/AD7934 is from 2.7 V to 5.25 V. Decouple the supply to
AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor.
2
W/B
Word/Byte Input. When this input is logic high, word transfer mode is enabled, and data is transferred to and
from the AD7933/AD7934 in 10-bit words on Pin DB2 to Pin DB11, or in 12-bit words on Pin DB0 to Pin DB11.
B
When W/ is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pin DB0 to
Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. When operating in byte transfer mode, tie off
unused data lines to DGND.
3 to 10
DB0 to DB7
Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result and allow
programming of the control register. These pins are controlled by CS, RD, and WR. The logic high/low voltage
levels for these pins are determined by the VDRIVE input. When reading from the AD7933, the two LSBs (DB0 and
DB1) are always 0, and the LSB of the conversion result is available on DB2.
11
12
13
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of
the AD7933/AD7934 operates. Decouple this pin to DGND. The voltage at this pin may be different to that at
VDD but should never exceed VDD by more than 0.3 V.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7933/AD7934. Connect this
pin to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and
must not be more than 0.3 V apart, even on a transient basis.
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled
by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte
of data written to or read from the AD7933/AD7934 is on DB0 to DB7. When HBEN is high, the top four bits of
the data being written to, or read from, the AD7933/AD7934 are on DB0 to DB3. When reading from the device,
DB4 and DB5 contain the ID of the channel to which the conversion result corresponds (see Channel Address
Bits in Table 9). DB6 and DB7 are always 0. When writing to the device, DB4 to DB7 of the high byte must be all
0s. Note that when reading from the AD7933, the two LSBs in the low byte are 0s, and the remaining 6 bits are
conversion data.
DGND
DB8/HBEN
14 to 16
17
DB9 to DB11
BUSY
Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and also allow
the control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic
high/low voltage levels for these pins are determined by the VDRIVE input.
Busy Output. This is the logic output indicating the status of the conversion. The BUSY output goes high
following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is
complete and the result is available in the output register, the BUSY output goes low. The track-and-hold
returns to track mode just prior to the falling edge of BUSY, on the 13th rising edge of SCLK, see Figure 34.
18
19
CLKIN
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7933/AD7934 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the
conversion time and achievable throughput rate. The CLKIN signal can be a continuous or burst clock.
Conversion Start Input. A falling edge on CONVST initiates a conversion. The track-and-hold goes from track to
hold mode on the falling edge of CONVST, and the conversion process is initiated at this point. Following
power-down, when operating in the autoshutdown or autostandby mode, a rising edge on CONVST is used to
power up the device.
CONVST
Rev. A | Page 9 of 32
AD7933/AD7934
Pin No.
20
Mnemonic
Description
WR
RD
Write Input. Active low logic input used in conjunction with CS to write data to the control register.
21
Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion
result is placed on the data bus following the falling edge of RD read while CS is low.
22
23
CS
Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or write data to
the control register.
Analog Ground. This is the ground reference point for all analog circuitry on the AD7933/AD7934. All analog
input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient
basis.
AGND
24
VREFIN/VREFOUT
Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC.
The nominal internal reference voltage is 2.5 V, and this appears at this pin. It is recommended to decouple the
VREFIN/VREFOUT pin to AGND with a 470 nF capacitor. This pin can be overdriven by an external reference. The input
voltage range for the external reference is 0.1 V to VDD; however, ensure that the analog input range does not
exceed VDD + 0.3 V. See the Reference Section.
25 to 28
VIN0 to VIN3
Analog Input 0 to Analog Input 3. Four analog input channels that are multiplexed into the on-chip track-and-
hold. The analog inputs can be programmed as four single-ended inputs, two fully differential pairs, or two
pseudo differential pairs by appropriately setting the MODE bits in the control register (see Table 9). Select the
analog input channel to be converted either by writing to Address Bit ADD1 and Address Bit ADD0 in the
control register prior to the conversion, or by using the on-chip sequencer. The input range for all input
channels can either be 0 V to VREF or 0 V to 2 × VREF, and the coding can be binary or twos complement,
depending on the states of the RANGE and CODING bits in the control register. To avoid noise pickup, connect
any unused input channels to AGND.
Rev. A | Page 10 of 32
AD7933/AD7934
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–60
100mV p-p SINE WAVE ON V AND/OR V
DD
NO DECOUPLING
DIFFERENTIAL/SINGLE-ENDED MODE
4096 POINT FFT
DRIVE
V
= 5V
DD
F
F
= 1.5MSPS
–70
–80
SAMPLE
= 49.62kHz
IN
SINAD = 70.94dB
THD = –90.09dB
DIFFERENTIAL MODE
INT REF
–90
EXT REF
–100
–110
–120
–100
–110
10
210
410
610
810
1010
SUPPLY RIPPLE FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 3. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
Figure 6. AD7934 FFT @ VDD = 5 V
1.0
0.8
0.6
–70
INTERNAL/EXTERNAL REFERENCE
V
= 5V
DD
V
= 5V
DIFFERENTIAL MODE
DD
–75
0.4
0.2
–80
–85
–90
–95
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
100
200
300
400
500
600
700
800
NOISE FREQUENCY (kHz)
Figure 4. Channel-to-Channel Isolation
Figure 7. AD7934 Typical DNL @ VDD = 5 V
80
70
60
50
40
30
20
1.0
0.8
0.6
V
= 5V
V
= 5V
DD
DD
DIFFERENTIAL MODE
V
= 3V
DD
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
F
= 1.5MSPS
SAMPLE
RANGE = 0 TO V
DIFFERENTIAL MODE
REF
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
Figure 8. AD7934 Typical INL @ VDD = 5 V
Figure 5. AD7934 SINAD vs. Analog Input Frequency for Various Supply Voltages
Rev. A | Page 11 of 32
AD7933/AD7934
4
10000
9000
8000
7000
6000
5000
4000
3000
9997
CODES
INTERNAL
REF
SINGLE-ENDED MODE
DIFFERENTIAL MODE
3
2
1
POSITIVE DNL
NEGATIVE DNL
0
2000
1000
0
3 CODES
2049 2050
–1
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75
2046
2047
2048
V
(V)
CODE
REF
Figure 9. AD7934 DNL vs. VREF for VDD = 3 V
Figure 12. AD7934 Histogram of Codes for
10k Samples @ VDD = 5 V with the Internal Reference
12
11
10
–60
–70
–80
DIFFERENTIAL MODE
V
= 5V
DD
DIFFERENTIAL MODE
V
= 5V
DD
SINGLE-ENDED MODE
9
8
–90
V
= 3V
DD
SINGLE-ENDED MODE
–100
V
= 3V
DD
DIFFERENTIAL MODE
7
6
–110
–120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
200
400
600
800
1000
1200
V
(V)
RIPPLE FREQUENCY (kHz)
REF
Figure 13. CMRR vs. Common-Mode Ripple with VDD = 5 V and 3 V
Figure 10. AD7934 ENOB vs. VREF
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
V
= 5V
DD
V
= 3V
DD
–4.0
–4.5
–5.0
SINGLE-ENDED MODE
2.5 3.0 3.5
0
0.5
1.0
1.5
V
2.0
(V)
REF
Figure 11. AD7934 Offset vs. VREF
Rev. A | Page 12 of 32
AD7933/AD7934
TERMINOLOGY
Integral Nonlinearity (INL)
Negative Gain Error
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, 1 LSB below the first code
transition, and full scale, 1 LSB above the last code transition.
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREF point. It is the deviation of the first
code transition (100 . . . 000) to (100 . . . 001) from the ideal (that is,
−VREFIN + 1 LSB) after the zero-code error has been adjusted out.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Negative Gain Error Match
The difference in negative gain error between any two channels.
Offset Error
Channel-to-Channel Isolation
The deviation of the first code transition (00 . . .000) to (00 . . .
001) from the ideal (that is, AGND + 1 LSB).
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale sine wave signal to the three nonselected input channels
and applying a 50 kHz signal to the selected channel. The
channel-to-channel isolation is defined as the ratio of the power
of the 50 kHz signal on the selected channel to the power of the
noise signal on the unselected channels that appears in the FFT
of this channel. The noise frequency on the unselected channels
varies from 40 kHz to 740 kHz. The noise amplitude is at
2 × VREF, while the signal amplitude is at 1 × VREF. See Figure 4.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
The deviation of the last code transition (111 . . .110) to (111 . . .
111) from the ideal (that is, VREF – 1 LSB) after the offset error
has been adjusted out.
Gain Error Match
The difference in gain error between any two channels.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency fS. The frequency
of the input varies from 1 kHz to 1 MHz.
Zero-Code Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to
+VREF biased about the VREFIN point. It is the deviation of the
midscale transition (all 0s to all 1s) from the ideal VIN voltage
(that is, VREF).
PSRR (dB) = 10log(Pf/PfS)
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Zero-Code Error Match
The difference in zero-code error between any two channels.
Common-Mode Rejection Ratio (CMRR)
Positive Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range with −VREF to +VREF
biased about the VREFIN point. It is the deviation of the last code
transition (011. . .110) to (011 .. . 111) from the ideal (that is, +VREF
– 1 LSB) after the zero-code error has been adjusted out.
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency fS as
CMRR (dB) = 10log (Pf/PfS)
Positive Gain Error Match
The difference in positive gain error between any two channels.
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Rev. A | Page 13 of 32
AD7933/AD7934
Track-and-Hold Acquisition Time
Peak Harmonic or Spurious Noise
The track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within 1/2 LSB, after the end of conversion.
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-noise and distortion at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the
quantization noise.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities create distortion products
at sum and difference frequencies of mfa nfb where m, n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
second-order terms include (fa + fb) and (fa − fb), while the
third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).
The theoretical signal-to-noise and distortion ratio for an ideal
N-bit converter with a sine wave input is given by
SINAD = (6.02 N + 1.76) dB
The AD7933/AD7934 is tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second-order terms are usually
distanced in frequency from the original sine waves, while the
third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
Thus, for a 12-bit converter, this is 74 dB, and for a 10-bit
converter, this is 62 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7933/AD7934, it is defined as
2
V22 +V32 +V42 +V52 +V6
THD
where:
dB = −20log
( )
V1
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Rev. A | Page 14 of 32
AD7933/AD7934
CONTROL REGISTER
The control register on the AD7933/AD7934 is a 12-bit, write-only register. Data is written to this register using the
and
pins. The
WR
CS
functions of the control register bits are described in Table 7. At power-up, the default bit settings in the control register are all 0s. When
writing to the control register between conversions, ensure that
returns high before performing the write.
CONVST
MSB
LSB
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PM1
PM0
CODING
REF
ZERO
ADD1
ADD0
MODE1
MODE0
SEQ1
SEQ0
RANGE
Table 7. Control Register Bit Function Description
Bit No. Mnemonic Description
11, 10
PM1, PM0
CODING
REF
Power Management Bits. Use these two bits to select the power mode of operation. The user can choose between
normal mode or various power-down modes of operation as shown in Table 8.
This bit selects the output coding of the conversion result. If the CODING bit is set to 0, the output coding is
straight (natural) binary. If the CODING bit is set to 1, the output coding is twos complement.
This bit selects whether the internal or external reference is used to perform the conversion. If the REF bit is
Logic 0, an external reference should be applied to the VREF pin, and if it is Logic 1, the internal reference is
selected. See the Reference Section.
9
8
7
ZERO
This bit is not used; therefore, it should always be set to Logic 0.
6, 5
ADD1,
ADD0
Use these two address bits to select which analog input channel is to be converted in the next conversion, if the
sequencer is not being used, or to select the final channel in a consecutive sequence when the sequencer is being
used (see Table 10 for more information). The selected input channel is decoded as shown in Table 9.
4, 3
2
MODE1,
MODE0
SEQ1
The two mode pins select the type of analog input on the four VIN pins. The AD7933/AD7934 have either four
single-ended inputs, two fully differential inputs, or two pseudo differential inputs (see Table 9).
The SEQ1 bit in the control register is used in conjunction with the SEQ0 bit to control the sequencer function
(see Table 10).
1
SEQ0
The SEQ0 bit in the control register is used in conjunction with the SEQ1 bit to control the sequencer function
(see Table 10).
0
RANGE
This bit selects the analog input range of the AD7933/AD7934. If RANGE is set to 0, the analog input range
extends from 0 V to VREF. If RANGE is set to 1, the analog input range extends from 0 V to 2 × VREF. When this range
is selected, AVDD must be 4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that
the analog input remains within the supply rails. See the Analog Inputs section for more information.
Table 8. Power Mode Selection Using the Power Management Bits in the Control Register
PM1 PM0 Mode
Description
0
0
0
1
Normal Mode
When operating in normal mode, all circuitry is fully powered up at all times.
Autoshutdown When operating in autoshutdown mode, the AD7933/AD7934 enters full shutdown mode at the end of
each conversion. In this mode, all circuitry is powered down.
1
0
Autostandby
When the AD7933/AD7934 enters this mode, the reference remains fully powered, the reference buffer is
partially powered down, and all other circuitry is fully powered down. This mode is similar to
autoshutdown mode, but it allows the part to power-up in 7 μs (or 600 ns if an external reference is used).
See the Power Modes of Operation section for more information.
1
1
Full Shutdown When the AD7933/AD7934 enters this mode, all circuitry is powered down. The information in the control
register is retained.
Rev. A | Page 15 of 32
AD7933/AD7934
Table 9. Analog Input Type Selection
MODE0 = 0, MODE1 = 0
MODE0 = 0, MODE1 = 1
MODE0 = 1, MODE1 = 0
MODE0 = 1, MODE1 = 1
Not Used
Four Single-Ended
I/P Channels
Two Fully Differential
I/P Channels
Two Pseudo Differential
I/P Channels
Channel Address
ADD1
ADD0
VIN+
VIN−
VIN+
VIN−
VIN+
VIN−
0
0
1
1
0
1
0
1
VIN0
VIN1
VIN2
VIN3
AGND
AGND
AGND
AGND
VIN0
VIN1
VIN2
VIN3
VIN1
VIN0
VIN3
VIN2
VIN0
VIN1
VIN2
VIN3
VIN1
VIN0
VIN3
VIN2
SEQUENCER OPERATION
The configuration of the SEQ0 and SEQ1 bits in the control register allow use of the sequencer function. Table 10 outlines the two
sequencer modes of operation.
Writing to the Control Register to Program the Sequencer
The AD7933 and AD7934 need 13 full CLKIN periods to perform a conversion. If the ADC does not receive the full 13 CLKIN periods,
CONVST
the conversion aborts. If a conversion is aborted after applying 12.5 CLKIN periods to the ADC, ensure that a rising edge of
or
a falling edge of CLKIN is applied to the part before writing to the control register to program the sequencer. If these conditions are not
met, the sequencer will not be in the correct state to handle being reprogrammed for another sequence of conversions and the
performance of the converter is not guaranteed.
Table 10. Sequence Selection Modes
SEQ0 SEQ1 Sequence Type
0
0
Select this configuration when the sequence function is not used. The analog input channel selected on each individual
conversion is determined by the contents of ADD1 and ADD0, the channel address bits, in each prior write operation. This
mode of operation reflects the normal operation of a multichannel ADC, without using the sequencer function, where
each write to the AD7933/AD7934 selects the next channel for conversion.
0
1
1
1
0
1
Not Used.
Not Used.
Use this configuration in conjunction with ADD1 and ADD0, the channel address bits, to program continuous conversions
on a consecutive sequence of channels. The sequence of channels extends from Channel 0 through to a selected final
channel as determined by the channel address bits in the control register. When in differential or pseudo differential mode,
inverse channels (for example, VIN1, VIN0) are not converted.
Rev. A | Page 16 of 32
AD7933/AD7934
CIRCUIT INFORMATION
The AD7933/AD7934 are fast, 4-channel, 10-bit and12-bit,
single-supply, successive approximation analog-to-digital
converters. The parts operate from a 2.7 V to 5.25 V power
supply and feature throughput rates up to 1.5 MSPS.
When the ADC starts a conversion (Figure 15), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the output code of the ADC. The output impedances
of the sources driving the VIN+ and the VIN− pins must match;
otherwise, the two inputs have different settling times, resulting
in errors.
The AD7933/AD7934 provide the user with an on-chip track-
and-hold, an internal accurate reference, an analog-to-digital
converter, and a parallel interface housed in a 28-lead TSSOP
package.
The AD7933/AD7934 have four analog input channels that
can be configured to be four single-ended inputs, two fully
differential pairs, or two pseudo differential pairs. There is
an on-chip channel sequencer that allows the user to select a
consecutive sequence of channels through which the ADC can
CAPACITIVE
DAC
COMPARATOR
cycle with each falling edge of
.
CONVST
C
B
A
S
V
V
IN+
SW1
CONTROL
LOGIC
The analog input range for the AD7933/AD7934 is 0 to VREF or
0 to 2 × VREF, depending on the status of the RANGE bit in the
control register. The output coding of the ADC can be either
binary or twos complement, depending on the status of the
CODING bit in the control register.
SW3
SW2
A
B
IN–
C
S
V
REF
CAPACITIVE
DAC
Figure 15. ADC Conversion Phase
The AD7933/AD7934 provide flexible power management
options to allow users to achieve the best power performance
for a given throughput rate. These options are selected by
programming PM1 and PM0, the power management bits, in
the control register.
ADC TRANSFER FUNCTION
The output coding for the AD7933/AD7934 is either straight
binary or twos complement, depending on the status of the
CODING bit in the control register. The designed code transitions
occur at successive LSB values (1 LSB, 2 LSBs, and so on), and
the LSB size is VREF/1024 for the AD7933 and VREF/4096 for the
AD7934. The ideal transfer characteristics of the AD7933/AD7934
for both straight binary and twos complement output coding are
shown in Figure 16 and Figure 17, respectively.
CONVERTER OPERATION
The AD7933/AD7934 are successive approximation ADCs
based around two capacitive digital-to-analog converters (DACs).
Figure 14 and Figure 15 show simplified schematics of the ADC
in acquisition and conversion phase, respectively. The ADC
comprises control logic, a SAR, and two capacitive DACs. Both
figures show the operation of the ADC in differential/pseudo
differential modes. Single-ended mode operation is similar but
VIN− is internally tied to AGND. In acquisition phase, SW3 is
closed, SW1 and SW2 are in Position A, the comparator is held
in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
111...111
111...110
111...000
011...111
1 LSB = V
1 LSB = V
/4096 (AD7934)
/1024 (AD7933)
REF
REF
CAPACITIVE
DAC
000...010
000...001
000...000
COMPARATOR
C
B
A
S
V
V
IN+
SW1
1 LSB
+V –1 LSB
REF
CONTROL
LOGIC
SW3
0V
SW2
ANALOG INPUT
A
B
IN–
C
S
NOTE: V
REF
IS EITHER V OR 2 × V
REF REF
V
REF
CAPACITIVE
DAC
Figure 16. AD7933/AD7934 Ideal Transfer Characteristic
with Straight Binary Output Coding
Figure 14. ADC Acquisition Phase
Rev. A | Page 17 of 32
AD7933/AD7934
ANALOG INPUT STRUCTURE
1 LSB = 2
1 LSB = 2
×
×
V
V
/4096 (AD7934)
/1024 (AD7933)
REF
REF
Figure 19 shows the equivalent circuit of the analog input
structure of the AD7933/AD7934 in differential/pseudo
differential modes. In single-ended mode, VIN− is internally
tied to AGND. The four diodes provide ESD protection for the
analog inputs. Ensure that the analog input signals never exceed
the supply rails by more than 300 mV; doing so causes these
diodes to become forward-biased and start conducting into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
–V
+ 1 LSB
V
+V – 1 LSB
REF
The C1 capacitors in Figure 19 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the sampling capacitors of the ADC and
typically have a capacitance of 45 pF.
REF
REF
Figure 17. AD7933/AD7934 Ideal Transfer Characteristic
with Twos Complement Output Coding and 2 × VREF Range
TYPICAL CONNECTION DIAGRAM
Figure 18 shows a typical connection diagram for the
AD7933/AD7934. The AGND and DGND pins are connected
together at the device for good noise suppression. If the internal
reference is used, the VREFIN/VREFOUT pin is decoupled to AGND
with a 0.47 μF capacitor to avoid noise pickup. Alternatively,
VREFIN/VREFOUT can be connected to an external reference source.
In this case, decouple the reference pin with a 0.1 μF capacitor.
In both cases, the analog input range can either be 0 V to VREF
(RANGE bit = 0) or 0 V to 2 × VREF (RANGE bit = 1). The
analog input configuration can be either four single-ended
inputs, two differential pairs, or two pseudo differential pairs
(see Table 9). The VDD pin is connected to either a 3 V or 5 V
supply. The voltage applied to the VDRIVE input controls the
voltage of the digital interface. As shown in Figure 18, it is
connected to the same 3 V supply of the microprocessor to
allow a 3 V logic interface (see the Digital Inputs section).
For ac applications, removing high frequency components from
the analog input signal is recommended by using an RC low-
pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
drive the analog input from a low impedance source. Large
source impedances significantly affect the ac performance of the
ADC. This may necessitate the use of an input buffer amplifier.
The choice of the op amp is a function of the particular
application.
V
DD
D
R1
C2
V
+
IN
D
C1
3V/5V
SUPPLY
V
DD
0.1μF
10μF
D
D
R1
C2
V
–
IN
V
V
DD
AD7933/AD7934
C1
W/B
0
CLKIN
CS
IN
0 TO V
/
REF
Figure 19. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
RD
0 TO 2 × V
REF
V
3
μC/μP
IN
WR
BUSY
CONVST
When no amplifier is used to drive the analog input, limit the
source impedance to low values. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD increases as the source impedance increases
and performance degrades. Figure 20 and Figure 21 show a
graph of the THD vs. source impedance with a 50 kHz input
tone for both VDD = 5 V and 3 V in single-ended mode and
differential mode, respectively.
DB0
AGND
DGND
DB11/DB9
V
/V
REFIN REFOUT
V
DRIVE
0.1μF
10μF
3V
2.5V
SUPPLY
V
REF
0.1μF EXTERNAL V
REF
0.47μF INTERNAL V
REF
Figure 18. Typical Connection Diagram
Rev. A | Page 18 of 32
AD7933/AD7934
–40
ANALOG INPUTS
F
= 50kHz
IN
–45
–50
–55
–60
–65
–70
–75
–80
The AD7933/AD7934 have software selectable analog input
configurations. Users can choose from among the following
configurations: four single-ended inputs, two fully differential
pairs, or two pseudo differential pairs. The analog input
configuration is chosen by setting the MODE0/MODE1 bits in
the internal control register (see Table 9).
V
= 3V
DD
Single-Ended Mode
V
= 5V
DD
The AD7933/AD7934 can have four single-ended analog input
channels by setting the MODE0 and MODE1 bits in the control
register to 0. In applications where the signal source has a high
impedance, it is recommended to buffer the analog input before
applying it to the ADC. An amplifier suitable for this function is
the AD8021. The analog input range of the AD7933/AD7934
–85
–90
10
100
1k
R
(Ω)
SOURCE
Figure 20. THD vs. Source Impedance in Single-Ended Mode
can be programmed to be either 0 to VREF or 0 to 2 × VREF
.
–60
F
= 50kHz
IN
–65
–70
–75
–80
–85
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it the correct format for the ADC.
Figure 23 shows a typical connection diagram when operating
the ADC in single-ended mode. This diagram shows a bipolar
signal of amplitude 1.25 V being preconditioned before it is
applied to the AD7933/AD7934. In cases where the analog
input amplitude is 2.5 V, the 3R resistor can be replaced with a
resistor of value R. The resultant voltage on the analog input of
the AD7933/AD7934 is a signal ranging from 0 V to 5 V. In this
case the 2 × VREF mode can be used.
V
= 3V
DD
–90
–95
V
= 5V
DD
–100
10
100
1k
R
(Ω)
SOURCE
+2.5V
R
Figure 21. THD vs. Source Impedance in Differential Mode
+1.25V
0V
R
0V
–1.25V
V
IN
Figure 22 shows a graph of the THD vs. the analog input fre-
quency for various supplies, while sampling at 1.5 MHz with an
SCLK of 25.5 MHz. In this case, the source impedance is 10 Ω.
V
IN0
IN7
3R
AD7933/
AD79341
R
V
–50
V
REFOUT
V
= 3V
DD
SINGLE-ENDED MODE
–60
–70
0.47μF
V
= 5V
DD
SINGLE-ENDED MODE
1
ADDITIONAL PINS OMITTED FOR CLARITY.
–80
–90
Figure 23. Single-Ended Mode Connection Diagram
V
= 5V/3V
DD
DIFFERENTIAL MODE
Differential Mode
–100
The AD7933/AD7934 can have two differential analog input
pairs by setting the MODE0 and MODE1 bits in the control
register to 0 and 1, respectively.
–110
–120
F
= 1.5MSPS
SAMPLE
RANGE = 0 TO V
REF
200
INPUT FREQUENCY (kHz)
0
100
300
400
500
600
700
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 24 defines the fully differential analog
input of the AD7933/AD7934.
Figure 22. THD vs. Analog Input Frequency for Various Supply Voltages
Rev. A | Page 19 of 32
AD7933/AD7934
4.5
4.0
T
= 25°C
A
V
REF
p-p
V
V
IN+
AD7933/
AD79341
3.5
3.0
V
REF
p-p
IN–
COMMON-MODE
VOLTAGE
2.5
2.0
1.5
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 24. Differential Input Definition
1.0
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN− pins in each
differential pair (that is, VIN+ − VIN−). VIN+ and VIN− should be
simultaneously driven by two signals, each of amplitude
VREF (or 2 × VREF depending on the range chosen) that are
180° out of phase. The amplitude of the differential signal is,
therefore, −VREF to +VREF peak-to-peak (that is, 2 × VREF). This is
regardless of the common mode (CM). The common mode is
the average of the two signals (that is (VIN+ + VIN−)/2) and is,
therefore, the voltage on which the two inputs are centered.
This results in the span of each input being CM VREF/2. This
voltage has to be set up externally and its range varies with the
reference value, VREF. As the value of VREF increases, the
common-mode range decreases. When driving the inputs with
an amplifier, the actual common-mode range is determined by
the output voltage swing of the amplifier.
0.5
0
0.1
0.6
1.1
1.6
2.1
2.6
V
(V)
REF
Figure 26. Input Common-Mode Range vs.
VREF (2 × VREF Range, VDD = 5 V)
Driving Differential Inputs
Differential operation requires that VIN+ and VIN− be
simultaneously driven with two equal signals that are 180° out
of phase. The common mode must be set up externally and has
a range that is determined by VREF, the power supply, and the
particular amplifier used to drive the analog inputs. Differential
modes of operation with either an ac or dc input provide the
best THD performance over a wide frequency range. Since not
all applications have a signal preconditioned for differential
operation, there is often a need to perform single-ended-to-
differential conversion.
Figure 25 and Figure 26 show how the common-mode range
typically varies with VREF for a 5 V power supply using the 0 to
VREF range or 2 × VREF range, respectively. The common mode
must be in this range to guarantee the functionality of the
AD7933/AD7934.
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential
signal to one of the analog input pairs of the AD7933/AD7934.
The circuit configurations shown in Figure 27 and Figure 28
show how a dual op amp converts a single-ended signal into a
differential signal for both a bipolar and unipolar input signal,
respectively.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise free signal of amplitude −VREF to
+VREF corresponding to the digital codes of 0 to 1024 for the
AD7933, and 0 to 4096 for the AD7934. If the 2 × VREF range is
used, then the input signal amplitude would extend from
The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. The AD8022 is a
suitable dual op amp that can be used in this configuration to
provide differential drive to the AD7933/AD7934.
−2 VREF to +2 VREF
.
3.5
T
= 25
°
C
A
3.0
2.5
2.0
1.5
1.0
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 27 and Figure 28 are optimized for
dc coupling applications requiring best distortion performance.
The circuit configuration shown in Figure 27 is configured to
convert and level shift a single-ended, ground-referenced
(bipolar) signal to a differential signal centered at the VREF level
of the ADC.
0.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
(V)
REF
The circuit in Figure 28 converts a unipolar, single-ended signal
into a differential signal.
Figure 25. Input Common-Mode Range vs.
REF (0 to VREF Range, VDD = 5 V)
V
Rev. A | Page 20 of 32
AD7933/AD7934
220Ω
V+
V
p-p
REF
2
×
V
p-p
REF
V
IN+
440Ω
3.75V
GND
27Ω
AD7933/
AD79341
2.5V
1.25V
V
V–
IN–
V
IN+
220Ω
V
REF
220Ω
220Ω
V+
AD7933/
AD7934
DC INPUT
VOLTAGE
0.47μF
V
IN–
V
REF
3.75V
2.5V
1.25V
27Ω
1
A
ADDITIONAL PINS OMITTED FOR CLARITY.
V–
Figure 29. Pseudo Differential Mode Connection Diagram
0.47μF
10kΩ
20kΩ
ANALOG INPUT SELECTION
As shown in Table 9, users can set up their analog input
configuration by setting the values in the MODE0 and MODE1
bits in the control register. Assuming the configuration has been
chosen, there are two different ways of selecting the analog
input to be converted depending on the state of the SEQ0 and
SEQ1 bits in the control register.
Figure 27. Dual Op Amp Circuit to Convert a Single-Ended
Bipolar Signal into a Unipolar Differential Signal
220Ω
V
p-p
REF
V
V+
REF
440Ω
3.75V
27Ω
2.5V
GND
1.25V
V–
V
V
IN+
Traditional Multichannel Operation (SEQ0 = SEQ1 = 0)
220Ω
220Ω
V+
AD7933/
AD7934
Any one of four analog input channels or two pairs of channels
may be selected for conversion in any order by setting the SEQ0
and SEQ1 bits in the control register both to 0. The channel to
be converted is selected by writing to the address bits, ADD1
and ADD0, in the control register to program the multiplexer
prior to the conversion. This mode of operation is that of a
traditional multichannel ADC where each data write selects the
next channel for conversion. Figure 30 shows a flowchart of this
mode of operation. The channel configurations are shown in
Table 9.
IN–
V
REF
3.75V
2.5V
1.25V
27Ω
A
V–
0.47μF
10kΩ
Figure 28. Dual Op Amp Circuit to Convert a Single-EndedUnipolar
Signal into a Differential Signal
Another method of driving the AD7933/AD7934 is to use the
AD8138 differential amplifier. The AD8138 can be used as a
single-ended-to-differential amplifier, or differential-to-differential
amplifier. The device is as easy to use as an op amp and greatly
simplifies differential signal amplification and driving.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
SET SEQ0 = SEQ1 = 0. SELECT THE DESIRED
CHANNEL TO CONVERT ON (ADD1 TO ADD0).
Pseudo Differential Mode
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
The AD7933/AD7934 can have two pseudo differential pairs by
setting the MODE0 and MODE1 bits in the control register to
1, 0, respectively. VIN+ is connected to the signal source and
must have an amplitude of VREF (or 2 × VREF depending on the
range chosen) to make use of the full dynamic range of the part.
A dc input is applied to the VIN− pin. The voltage applied to this
input provides an offset from ground or a pseudo ground for
the VIN+ input. The benefit of pseudo differential inputs is that
they separate the analog input signal ground from the ADC
ground, allowing the cancellation of dc common-mode
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED ON BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SEQ0 = SEQ1 = 0.
Figure 30. Traditional Multichannel Operation Flow Chart
Using the Sequencer: Consecutive Sequence (SEQ0 = 1,
SEQ1 = 1)
A sequence of consecutive channels can be converted beginning
with Channel 0 and ending with a final channel selected by
writing to the ADD1 and ADD0 bits in the control register. This
is done by setting the SEQ0 and SEQ1 bits in the control
register both to 1. Once the control register is written to, the
next conversion is on Channel 0, then Channel 1, and so on
until the channel selected by the Address Bit ADD1 and Address
voltages. Typically, this range can extend to −0.3 V to +0.7 V
when VDD = 3 V or −0.3 V to +1.8 V when VDD = 5 V. Figure 29
shows a connection diagram for pseudo differential mode.
Rev. A | Page 21 of 32
AD7933/AD7934
Bit ADD0 is reached. The ADC then returns to Channel 0 and
using the 0 to VREF range, or when using the 2 × VREF range that
2 × VREF +(VIN−) ≤ VDD.
starts the sequence again. The
input must be kept high to
WR
ensure that the control register is not accidentally overwritten
and the sequence interrupted. This pattern continues until such
time as the AD7933/AD7934 is written to. Figure 31 shows the
flowchart of the consecutive sequence mode.
In all cases, the specified reference is 2.5 V.
The performance of the part with different reference values is
shown in Figure 9 to Figure 11. The value of the reference sets
the analog input span and the common-mode voltage range.
Errors in the reference source result in gain errors in the
AD7933/AD7934 transfer function and add to the specified
full-scale errors on the part.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION SELECT
FINAL CHANNEL (ADD1 AND ADD0) IN
CONSECUTIVE SEQUENCE.
Table 11 lists suitable voltage references available from Analog
Devices that can be used. Figure 33 shows a typical connection
diagram for an external reference.
SET SEQ0 = 1 SEQ1 = 1.
CONTINUOUSLY CONVERT ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0
UP TO AND INCLUDING THE PREVIOUSLY
SELECTED FINAL CHANNEL ON ADD1 AND ADD0
WITH EACH CONVST PULSE.
Table 11. Examples of Suitable Voltage References
Output
Reference Voltage
Initial Accuracy Operating
Figure 31. Consecutive Sequence Mode Flow Chart
(ꢀ max)
Current (μA)
AD780
ADR421
ADR420
2.5/3
2.5
2.048
0.04
0.04
0.05
1000
500
500
REFERENCE SECTION
The AD7933/AD7934 can operate with either the on-chip or an
external reference. The internal reference is selected by setting the
REF bit in the internal control register to 1. A block diagram of
the internal reference circuitry is shown in Figure 32. The
internal reference circuitry includes an on-chip 2.5 V band gap
reference and a reference buffer. When using the internal reference,
decouple the VREFIN/VREFOUT pin to AGND with a 0.47 μF capacitor.
This internal reference not only provides the reference for the
analog-to-digital conversion, but it can also be used externally in
the system. It is recommended that the reference output is
buffered using an external precision op amp before applying it
anywhere in the system.
AD7933/
AD79341
AD780
V
NC
1
2
3
4
O/PSELECT
8
7
6
5
NC
NC
REF
V
+V
IN
DD
2.5V
TEMP
GND
V
OUT
0.1μF
10nF
0.1μF
0.1μF
TRIM
NC
NC = NO CONNECT
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 33. Typical VREF Connection Diagram
BUFFER
REFERENCE
V
/
REFIN
Digital Inputs
V
REFOUT
The digital inputs applied to the AD7933/AD7934 are not
limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the AVDD + 0.3 V limit that is on the analog inputs.
AD7933/
AD7934
ADC
Figure 32. Internal Reference Circuit Block Diagram
Another advantage of the digital inputs not being restricted by
the AVDD + 0.3 V limit is the fact that power supply sequencing
issues are avoided. If any of these inputs are applied before AVDD,
then there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V was applied prior to AVDD.
Alternatively, an external reference can be applied to the
VREFIN/VREFOUT pin of the AD7933/AD7934. An external
reference input is selected by setting the REF bit in the internal
control register to 0. The external reference input range is 0.1 V
to VDD. It is important to ensure that, when choosing the
reference value, the maximum analog input range (VIN MAX) is
never greater than VDD + 0.3 V to comply with the maximum
ratings of the device. For example, if operating in differential
mode and the reference is sourced from VDD, then the 0 to 2 ×
VREF range cannot be used. This is because the analog input
signal range would now extend to 2 × VDD, which would exceed
the maximum rating conditions. In the pseudo differential
modes, the user must ensure that VREF + (VIN−) ≤ VDD when
VDRIVE Input
The AD7933/AD7934 have a VDRIVE feature. VDRIVE controls the
voltage at which the parallel interface operates. VDRIVE allows the
ADC to easily interface to 3 V, and 5 V processors.
For example, if the AD7933/AD7934 are operated with an AVDD
of 5 V, and the VDRIVE pin is powered from a 3 V supply, the
AD7933/AD7934 have better dynamic performance with an
AVDD of 5 V while still being able to interface to 3 V processors.
Rev. A | Page 22 of 32
AD7933/AD7934
Ensure VDRIVE does not exceed AVDD by more than 0.3 V (see the
Absolute Maximum Ratings section).
At the end of the conversion, BUSY goes low and can be used to
activate an interrupt service routine. The
and
lines are
CS
RD
then activated in parallel to read the 10 bits or 12 bits of
conversion data. When power supplies are first applied to the
PARALLEL INTERFACE
The AD7933/AD7934 have a flexible, high speed, parallel
interface. This interface is 10-bits (AD7933) or 10-bits (AD7934)
wide and is capable of operating in either word (W/ tied high)
device, a rising edge on
is necessary to put the track-
CONVST
and-hold into track. The acquisition time of 125 ns minimum
must be allowed before is brought low to initiate a
B
CONVST
conversion. The ADC then goes into hold on the falling edge of
and back into track on the 13th rising edge of CLKIN
or byte (W/ tied low) mode. The
signal is used to
CONVST
B
initiate conversions and when operating in autoshutdown or
autostandby mode, it is used to initiate power up.
CONVST
after this (see Figure 34). When operating the device in
autoshutdown or autostandby mode, where the ADC powers
down at the end of each conversion, a rising edge on the
A falling edge on the
signal is used to initiate
CONVST
conversions, and it also puts the ADC track-and-hold into
track. Once the signal goes low, the BUSY signal goes
signal is used to power up the device.
CONVST
CONVST
high for the duration of the conversion. In between conversions,
must be brought high for a minimum time of t1. This
CONVST
must happen after the 14th falling edge of CLKIN; otherwise, the
conversion is aborted and the track-and-hold goes back into track.
B
t1
A
CONVST
tCONVERT
1
2
3
4
5
12
13
14
t2
CLKIN
BUSY
t20
t3
t9
INTERNAL
TRACK/HOLD
tAQUISITION
CS
RD
t10
t11
t12
t13
t14
THREE-STATE
tQUIET
DB0 TO DB11
DATA
THREE-STATE
WITH CS AND RD TIED LOW
OLD DATA
DB0 TO DB11
DATA
B
Figure 34. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle in Word Mode (W/ = 1)
Rev. A | Page 23 of 32
AD7933/AD7934
Reading Data from the AD7933/AD7934
The
and
signals are gated internally and level triggered
RD
CS
active low. In either word mode or byte mode,
and
may
RD
CS
With the W/ pin tied logic high, the AD7933/AD7934
B
be tied together as the timing specifications for t10 and t11 are
0 ns minimum. This means the bus is constantly driven by the
AD7933/AD7934.
interface operates in word mode. In this case, a single read
operation from the device accesses the conversion data-word on
Pin DB0 to Pin DB11 (12-bit word) and Pin DB2 to DB11
(10-bit word). The DB8/HBEN pin assumes its DB8 function.
The data is placed onto the data bus a time t13 after both
and
CS
rising edge can be used to latch data out of
RD
With the W/ pin tied to logic low, the AD7933/AD7934
B
go low. The
RD
interface operates in byte mode. In this case, the DB8/HBEN
pin assumes its HBEN function.
the device. After a time, t14, the data lines become three-stated.
Alternatively, and can be tied permanently low, and the
conversion data is valid and placed onto the data bus a time, t9,
before the falling edge of BUSY.
CS
RD
Conversion data from the AD7933/ AD7934 must be accessed
in two read operations with eight bits of data provided on DB0
to DB7 for each of the read operations. The HBEN pin
determines whether the read operation accesses the high byte or
the low byte of the 12-or 10-bit word. For a low byte read, DB0
to DB7 provide the eight LSBs of the 12-bit word. For 10-bit
operation, the two LSBs of the low byte are 0s and are followed
by six bits of conversion data. For a high byte read, DB0 to DB3
provide the four MSBs of the 12-/10-bit word. DB4 and DB5 of the
high byte provide the Channel ID. DB6 and DB7 are always 0.
Note that if
is pulsed during the conversion time then this
RD
causes a degradation in linearity performance of approximately
0.25 LSB. Reading during conversion, by way of tying and
CS
low, does not cause any degradation.
RD
Figure 34 shows the read cycle timing diagram for a 12- or 10-
bit transfer. When operated in word mode, the HBEN input
does not exist and only the first read operation is required to
access data from the device. When operated in byte mode, the
two read cycles shown in Figure 35 are required to access the
full data word from the device.
HBEN/DB8
t15
t16
t15
t16
CS
t10
t11
t17
t12
RD
t13
t14
DB0 TO DB7
LOW BYTE
HIGH BYTE
B
Figure 35. AD7933/AD7934 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/ = 0)
Rev. A | Page 24 of 32
AD7933/AD7934
Writing Data to the AD7933/AD7934
Figure 36 shows the write cycle timing diagram of the
AD7933/AD7934. When operated in word mode, the HBEN
input does not exist and only one write operation is required to
write the word of data to the device. Provide data on DB0 to
DB11. When operated in byte mode, the two write cycles shown
in Figure 37 are required to write the full data-word to the
AD7933/AD7934. In Figure 37, the first write transfers the
lower eight bits of the data-word from DB0 to DB7, and the
second write transfers the upper four bits of
With W/ tied logic high, a single write operation transfers the
B
full data-word on DB0 to DB11 to the control register on the
AD7933/AD7934. The DB8/HBEN pin assumes its DB8
function. Data written to the AD7933/AD7934 should be
provided on the DB0 to DB11 inputs, with DB0 being the LSB
of the data-word. With W/ tied logic low, the AD7933/AD7934
B
requires two write operations to transfer a full 12-bit word.
DB8/HBEN assumes its HBEN function. Data written to the
AD7933/AD7934 should be provided on the DB0 to DB7
inputs. HBEN determines whether the byte written is high byte
or low byte data. The low byte of the data-word has DB0 being
the LSB of the full data-word. For the high byte write, HBEN
should be high and the data on the DB0 input should be data
bit 8 of the 12 bit word.
the data-word.
When writing to the AD7933/AD7934, the top four bits in the
high byte must be 0s.
The data is latched into the device on the rising edge of
.
WR
The data needs to be setup a time, t7, before the
rising edge
WR
and held for a time, t8, after the
rising edge. The
and
WR
and
WR
CS
CS
may be tied
signals are gated internally.
WR
together as the timing specifications for t4 and t5 are 0 ns
minimum (assuming
and
have not already been tied
CS
RD
together).
CS
t4
t5
WR
t6
t8
t7
DATA
DB0 TO DB11
B
Figure 36. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/ = 1)
HBEN/DB8
t18
t19
t18
t19
CS
t4
t5
t17
t6
WR
t7
LOW BYTE
t8
DB0 TO DB7
HIGH BYTE
B
Figure 37. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/ = 0)
Rev. A | Page 25 of 32
AD7933/AD7934
Autostandby (PM1 = 1; PM0 = 0)
POWER MODES OF OPERATION
In this mode of operation, the AD7933/AD7934 automatically
enter standby mode at the end of each conversion, shown as
Point A in Figure 34. When this mode is entered, all circuitry
on the AD7933/AD7934 is powered down except for the
reference and reference buffer. The track-and-hold goes into
hold at this point and remains in hold as long as the device is in
standby. The part remains in standby until the next rising edge
The AD7933/AD7934 have four different power modes of
operation. These modes are designed to provide flexible power
management options. Different options can be chosen to optimize
the power dissipation/throughput rate ratio for differing applica-
tions. The mode of operation is selected by PM1 and PM0, the
power management bits, in the control register (see Table 8 for
details). When power is first applied to the AD7933/AD7934, an
on-chip, power-on reset circuit ensures the default power-up
condition is normal mode.
of
powers up the device. The power-up time required
CONVST
depends on whether the internal or external reference is used.
With an external reference, the power-up time required is a
minimum of 600 ns, while using the internal reference, the
power-up time required is a minimum of 7 μs. The user should
ensure this power-up time has elapsed before initiating another
Note that, after power-on, track-and-hold is in hold mode, and
the first rising edge of
places the track-and-hold into
CONVST
track mode.
conversion as shown in Figure 38. This rising edge of
also places the track-and-hold back into track mode.
CONVST
Normal Mode (PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate performance
wherein the user does not have to worry about any power-up
times because the AD7933/AD7934 remain fully powered up at
all times. At power-on reset, this mode is the default setting in
the control register.
Full Shutdown Mode (PM1 = 1; PM0 = 1)
When this mode is entered, all circuitry on the AD7933/AD7934
is powered down upon completion of the write operation, that
is, on rising edge of
. The track-and-hold enters hold mode
WR
at this point. The part retains the information in the control
register while in shutdown. The AD7933/AD7934 remain in full
shutdown mode, and the track-and-hold in hold mode, until
the power management bits (PM1 and PM0) in the control
register are changed. If a write to the control register occurs
while the part is in full shutdown mode, and the power
management bits are changed to PM0 = PM1 = 0 (normal
Autoshutdown (PM1 = 0; PM0 = 1)
In this mode of operation, the AD7933/AD7934 automatically
enter full shutdown at the end of each conversion, shown at
Point A in Figure 34 and Figure 38. In shutdown mode, all
internal circuitry on the device is powered down. The part
retains information in the control register during shutdown.
The track-and-hold also goes into hold at this point and remains in
hold as long as the device is in shutdown. The AD7933/AD7934
mode), the part begins to power up on the
rising edge, and
WR
the track-and-hold returns to track. To ensure the part is fully
powered up before a conversion is initiated, the power-up time
remains in shutdown mode until the next rising edge of
CONVST
(see Point B in Figure 34 and Figure 38). In order to keep the
device in shutdown for as long as possible, should
of 10 ms minimum should be allowed before the
CONVST
CONVST
falling edge; otherwise, invalid data is read.
idle low between conversions as shown in Figure 38. On this
rising edge, the part begins to power-up and the track-and-hold
returns to track mode. The power-up time required is 10 ms
minimum regardless of whether the user is operating with the
internal or external reference. The user should ensure that the
power-up time has elapsed before initiating a conversion.
Note that all power-up times quoted apply with a 470 nF
capacitor on the VREFIN pin.
tPOWER-UP
B
A
CONVST
1
14
1
14
CLKIN
BUSY
Figure 38. Autoshutdown/Autostandby Mode
Rev. A | Page 26 of 32
AD7933/AD7934
POWER VS. THROUGHPUT RATE
10
A considerable advantage of powering the ADC down after a
conversion is that the power consumption of the part is
T
= 25°C
A
9
8
7
6
5
4
3
significantly reduced at lower throughput rates. When using the
different power modes, the AD7933/AD7934 are only powered
up for the duration of the conversion. Therefore, the average
power consumption per cycle is significantly reduced. Figure 39
shows a plot of power vs. throughput rate when operating in
autostandby mode for both VDD = 5 V and 3 V. For example if
the device runs at a throughput rate of 10 kSPS, then the overall
cycle time would be 100 μs. If the maximum CLKIN frequency
of 25.5 MHz is used, the conversion time accounts for only
0.525 μs of the overall cycle time while the AD7933/AD7934
remains in standby mode for the remainder of the cycle.
V
= 5V
DD
V
= 3V
DD
2
1
0
0
200
400
600
800
1000
1200
1400
1600
THROUGHPUT (kSPS)
Figure 40 shows a plot of the power vs. the throughput rate
when operating in normal mode for both VDD = 5 V and 3 V.
In both plots, the figures apply when using the internal
reference. If an external reference is used, the power-up time
reduces to 600 ns; therefore, the AD7933/AD7934 remains in
standby for a greater time in every cycle. Additionally, the
current consumption, when converting, should be lower than
the specified maximum of 2.7 mA or 2.0 mA with VDD = 5 V
or 3 V, respectively.
Figure 40. Power vs. Throughput in Normal Mode Using Internal Reference
MICROPROCESSOR INTERFACING
AD7933/AD7934 to ADSP-21xx Interface
Figure 41 shows the AD7933/AD7934 interfaced to the
ADSP-21xx series of DSPs as a memory mapped device.
A single wait state may be necessary to interface the AD7933/
AD7934 to the ADSP-21xx, depending on the clock speed of
the DSP. The wait state can be programmed via the data memory
wait state control register of the ADSP-21xx (see the ADSP-21xx
family user’s manual for details). The following instruction
reads from the AD7933/AD7934:
1.8
T
= 25°C
A
1.6
1.4
1.2
1.0
0.8
0.6
0.4
V
= 5V
MR = DM (ADC)
DD
where ADC is the address of the AD7933/AD7934.
DSP/USER SYSTEM
CONVST
A0 TO A15
ADDRESS BUS
V
= 3V
DD
AD7933/
AD79341
ADSP-21xx1
DMS
ADDRESS
DECODER
CS
0.2
0
IRQ2
WR
BUSY
WR
0
20
40
60
80
100
120
140
THROUGHPUT (kSPS)
RD
RD
Figure 39. Power vs. Throughput in
Autostandby Mode Using Internal Reference
DB0 TO DB11
D0 TO D23
DATA BUS
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 41. Interfacing to the ADSP-21xx
Rev. A | Page 27 of 32
AD7933/AD7934
AD7933/AD7934 to ADSP-21065L Interface
DSP/USER SYSTEM
CONVST
Figure 42 shows a typical interface between the AD7933/
AD7934 and the ADSP-21065L SHARC® processor. This
interface is an example of one of three DMA handshake modes.
A0 TO A15
ADDRESS BUS
ADDRESS
TMS32020/
AD7933/
AD79341
The
control line is actually three memory select lines.
MSx
TMS320C25/
TMS320C501
Internal ADDR25:24 are decoded into
, these lines are then
MS3:0
IS
EN
CS
DECODER
asserted as chip selects. The
in this setup as the interrupt to signal the end of the conversion.
The rest of the interface is standard handshaking operation.
(DMA Request 1) is used
DMAR1
READY
TMS320C25
ONLY
MSC
STRB
WR
RD
DSP/USER SYSTEM
R/W
CONVST
ADDR TO ADDR
23
ADDRESS BUS
0
INT
X
BUSY
ADDRESS
LATCH
DMD0 TO DMD15
DB11 TO DB0
DATA BUS
AD7933/
AD79341
MS
X
1
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS BUS
ADSP-21065L1
DMAR
ADDRESS
DECODER
Figure 43. Interfacing to the TMS32020/C25/C5x
CS
BUSY
RD
1
AD7933/AD7934 to 80C186 Interface
RD
Figure 44 shows the AD7933/AD7934 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent, high speed DMA channels where data transfers
can occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7933/AD7934 finish a conversion,
the BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA READ
operation, which also resets the interrupt latch. Sufficient
priority must be assigned to the DMA channel to ensure that
the DMA request is serviced before the completion of the next
conversion.
WR
WR
DB0 TO DB11
D0 TO D31
DATA BUS
1
ADDITIONAL PINS REMOVED FOR CLARITY.
Figure 42. Interfacing to the ADSP-21065L
AD7933/AD7934 to TMS32020, TMS320C25, and
TMS320C5x Interface
Parallel interfaces between the AD7933/AD7934 and the
TMS32020, TMS320C25 and TMS320C5x family of DSPs are
shown in Figure 43. Select the memory mapped address for the
AD7933/AD7934 to fall in the I/O memory space of the DSPs.
The parallel interface on the AD7933/AD7934 is fast enough to
interface to the TMS32020 with no extra wait states. If high
μP/USER SYSTEM
CONVST
AD0 TO AD15
A16 TO A19
ADDRESS/DATA BUS
speed glue logic, such as 74AS devices, are used to drive the
RD
ADDRESS
LATCH
AD7933/
AD79341
ALE
and the
lines when interfacing to the TMS320C25, then
WR
ADDRESS BUS
again, no wait states are necessary. However, if slower logic is
used, data accesses may be slowed sufficiently when reading
from, and writing to, the part to require the insertion of one
wait state. Extra wait states are necessary when using the
TMS320C5x at their fastest clock speeds (see the TMS320C5x
user’s guide for details).
80C1861
DRQ1
ADDRESS
DECODER
CS
Q
R
S
BUSY
RD
RD
WR
WR
DATA BUS
DB0 TO DB11
Data is read from the ADC using the following instruction:
1
ADDITIONAL PINS OMITTED FOR CLARITY.
IN D, ADC
where:
Figure 44. Interfacing to the 80C186
D is the data memory address.
ADC is the AD7933/AD7934 address.
Rev. A | Page 28 of 32
AD7933/AD7934
APPLICATION HINTS
GROUNDING AND LAYOUT
Good decoupling is also important. Decouple all analog
supplies with 10 μF tantalum capacitors in parallel with 0.1 μF
capacitors to GND. To achieve the best performance from these
decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 ꢀF capacitors should have a low effective series resistance
(ESR) and effective series inductance (ESI), such as the
common ceramic types or surface-mount types. These types of
capacitors provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
Design the printed circuit board that houses the AD7933/AD7934
so that the analog and digital sections are separated and con-
fined to certain areas of the board. This facilitates the use of
ground planes that can be easily separated. Generally, a minimum
etch technique is best for ground planes because it offers
optimum shielding. Join digital and analog ground planes in
only one place, establishing a star ground point connection as
close as possible to the ground pins on the AD7933/AD7934.
Avoid running digital lines under the device because this
couples noise onto the die. However, the analog ground plane
should be allowed to run under the AD7933/AD7934 to avoid
noise coupling. To provide low impedance paths and reduce the
effects of glitches on the power supply line, use as large a trace
as possible on the power supply lines to the AD7933/AD7934.
EVALUATING THE AD7933/AD7934
PERFORMANCE
The recommended layout for the AD7933/AD7934 is outlined
in the evaluation board documentation. The evaluation board
package includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from the
PC via the evaluation board controller. The evaluation board
controller can be used in conjunction with the AD7933/AD7934
evaluation board, as well as many other ADI evaluation boards
ending in the CB designator, to demonstrate and evaluate the ac
and dc performance of the AD7933/AD7934.
Shield fast switching signals, such as clocks, with digital ground
to avoid radiating noise to other sections of the board, and
never run clock signals near the analog inputs. Avoid crossover
of digital and analog signals. To reduce the effects of
feedthrough through the board, run traces on opposite sides of
the board at right angles to each other. A microstrip technique
is by far the best, but it is not always possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes, while signals are placed on the
solder side.
The software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7933/AD7934. The
software and documentation are on the CD that ships with the
evaluation board.
Rev. A | Page 29 of 32
AD7933/AD7934
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 45. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7933BRU
AD7933BRU-REEL
AD7933BRU-REEL7
AD7933BRUZ2
AD7933BRUZ-REEL72
AD7934BRU
AD7934BRU-REEL
AD7934BRU-REEL7
AD7934BRUZ2
AD7934BRUZ-REEL72
EVAL-AD7933CB3
EVAL-AD7934CB3
EVAL-CONTROL BRD24
Temperature Range
Linearity Error (LSB)1
Package Description
Package Option
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
−40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
−40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
–40ꢁC to +85ꢁC
1
1
1
1
1
1
1
1
1
1
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
Evaluation Board
Evaluation Board
Controller Board
RU-28
RU-28
1 Linearity error here refers to integral linearity error.
2 Z = Pb-free part.
3 This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.
4 The evaluation board controller is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB
designators. The following needs to be ordered to obtain a complete evaluation kit: the ADC evaluation board (for example, EVAL-AD7934CB), the EVAL-CONTROL
BRD2, and a 12 V ac transformer. See relevant evaluation board technical note for more details.
Rev. A | Page 30 of 32
AD7933/AD7934
NOTES
Rev. A | Page 31 of 32
AD7933/AD7934
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03713-0-12/05(A)
Rev. A | Page 32 of 32
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