AD7934-6BRU [ADI]
IC 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, TSSOP-28, Analog to Digital Converter;
| 型号： | AD7934-6BRU |
| 厂家： | 
ADI |
| 描述： | IC 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, TSSOP-28, Analog to Digital Converter |
| 文件： | 总28页 (文件大小：924K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-Channel, 625 kSPS, 12-Bit
Parallel ADC with a Sequencer
AD7934-6
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Throughput rate: 625 kSPS
V
AGND
DD
Specified for VDD of 2.7 V to 5.25 V
Power consumption
AD7934-6
V
REFIN/
V
REFOUT
2.5V
3.6 mW max at 625 kSPS with 3 V supplies
7.5 mW max at 625 kSPS with 5 V supplies
4 analog input channels with a sequencer
Software configurable analog inputs
4-channel single-ended inputs
2-channel fully differential inputs
2-channel pseudo differential inputs
Accurate on-chip 2.5 V reference
0.2ꢀ max @ 25°C, 25 ppm/°C max
70 dB SINAD at 50 kHz input frequency
No pipeline delays
VREF
V
V
0
IN
IN
CLKIN
12-BIT
SAR ADC
AND
I/P
CONVST
T/H
MUX
CONTROL
BUSY
3
SEQUENCER
V
PARALLEL INTERFACE/CONTROL REGISTER
DRIVE
High speed parallel interface—word/byte modes
Full shutdown mode: 2 µA max
28-lead TSSOP package
DB0 DB11
CS RD WR W/B
DGND
Figure. 1
GENERAL DESCRIPTION
The AD7934-6 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. The part also
features flexible power management options. An on-chip control
register allows the user to set up different operating conditions,
including analog input range and configuration, output coding,
power management, and channel sequencing.
The AD7934-6 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter (ADC). The
part operates from a single 2.7 V to 5.25 V power supply and
features throughput rates up to 625 kSPS. The part contains a
low noise, wide bandwidth, differential track-and-hold
amplifier that handles input frequencies up to 50 MHz.
PRODUCT HIGHLIGHTS
The AD7934-6 features four analog input channels with a channel
sequencer that allows a preprogrammed selection of channels to
be converted sequentially. This part can accept either single-
ended, fully differential, or pseudo differential analog inputs.
1. High throughput with low power consumption.
2. Four analog inputs with a channel sequencer.
3. Accurate on-chip 2.5 V reference.
4. Single-ended, pseudo differential, or fully differential analog
inputs that are software selectable.
Data acquisition and conversion are controlled by standard control
inputs, which allow for easy interfacing to microprocessors and
5. No pipeline delay.
DSPs. The input signal is sampled on the falling edge of
,
CONVST
6. Accurate control of the sampling instant via a
and once off conversion control.
input
CONVST
which is also the point where the conversion is initiated.
The AD7934-6 has an accurate on-chip 2.5 V reference that
can be used as the reference source for the analog-to-digital
Table 1. Related Devices
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
Similar
Device
Number
of Bits
Number of
Channels
Speed
AD7938/39
AD7933/34
AD7938-6
12/10
10/12
12
8
4
8
1.5 MSPS
1.5 MSPS
625 kSPS
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices.Trademarks and registered trademarks are theproperty of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD7934-6
TABLE OF CONTENTS
Features .............................................................................................. 1
Converter Operation.................................................................. 15
ADC Transfer Function............................................................. 15
Typical Connection Diagram ................................................... 16
Analog Input Structure.............................................................. 16
Analog Input Configurations ................................................... 17
Analog Input Selection.............................................................. 19
Reference Section ....................................................................... 20
Parallel Interface......................................................................... 21
Power Modes of Operation ....................................................... 24
Power vs. Throughput Rate....................................................... 25
Microprocessor Interfacing....................................................... 25
Application Hints ........................................................................... 27
Grounding and Layout .............................................................. 27
Evaluating the AD7934-6 Performance .................................. 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 11
Control Register.............................................................................. 13
Sequencer Operation ................................................................. 14
Note on Writing to the Control Register to
Program the Sequencer ............................................................. 14
Circuit Information........................................................................ 15
REVISION HISTORY
10/05—Rev. 0 to Rev. A
Changes to Product Highlights....................................................... 1
Inserted Table 1................................................................................. 1
Changes to Specifications................................................................ 3
Changes to Timing Specifications.................................................. 5
Changes to Pin Function Descriptions.......................................... 7
Added Writing to the Control Register to
Program the Sequencer Section.................................................... 14
Changes to the Analog Inputs Section......................................... 17
Changes to the Grounding and Layout Section ......................... 27
1/05—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD7934-6
SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted, FCLKIN = 10 MHz, FSAMPLE = 625 kSPS;
TA = TMIN to TMAX1, unless otherwise noted.
Table 2.
Parameter
B Version1
Unit
Test Conditions/Comments
FIN = 50 kHz sine wave
Differential mode
Single-ended mode
Differential mode
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
70
dB min
dB min
dB min
dB min
dB max
dB max
dB max
68
71
Signal-to-Noise Ratio (SNR)2
69
Single-ended mode
Total Harmonic Distortion (THD)2
−73
−70
−73
−85 dB typ, differential mode
−80 dB typ, single-ended mode
−82 dB typ
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation
Aperture Delay2
fa = 30 kHz, fb = 50 kHz
−86
−90
−85
5
72
50
dB typ
dB typ
dB typ
ns typ
FIN = 50 kHz, FNOISE = 300 kHz
Aperture Jitter2
Full Power Bandwidth2
ps typ
MHz typ
MHz typ
@ 3 dB
@ 0.1 dB
10
DC ACCURACY
Resolution
Integral Nonlinearity2
12
1
1.5
Bits
LSB max
LSB max
Differential mode
Single-ended mode
Differential Nonlinearity2
Differential Mode
0.95
−0.95/+1.5
LSB max
LSB max
Guaranteed no missed codes to 12 bits
Guaranteed no missed codes to 12 bits
Straight binary output coding
Single-Ended Mode
Single-Ended and Pseudo Differential Input
Offset Error2
6
1
3
1
LSB max
LSB max
LSB max
LSB max
Offset Error Match2
Gain Error2
Gain Error Match2
Fully Differential Input
Positive Gain Error2
Positive Gain Error Match2
Zero-Code Error2
Zero-Code Error Match2
Negative Gain Error2
Negative Gain Error Match2
ANALOG INPUT
Twos complement output coding
3
1
6
1
3
1
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Single-Ended Input Range
0 to VREF
0 to 2 × VREF
0 to VREF
0 to 2 × VREF
−0.3 to +0.7
−0.3 to +1.8
VCM VREF/2
VCM VREF
1
V
V
V
V
V typ
V typ
V
RANGE bit = 0
RANGE bit = 1
RANGE bit = 0
RANGE bit = 1
VDD = 3 V
VDD = 5 V
VCM = VREF/23, RANGE bit = 0
VCM = VREF3, RANGE bit = 1
Pseudo Differential Input Range: VIN+
VIN−
Fully Differential Input Range: VIN+ and VIN−
VIN+ and VIN−
DC Leakage Current4
V
µA max
pF typ
pF typ
Input Capacitance
45
10
When in track
When in hold
Rev. A | Page 3 of 28
AD7934-6
Parameter
B Version1
Unit
Test Conditions/Comments
1ꢀ for specified performance
0.2ꢀ max @ 25ꢁC
REFERENCE INPUT/OUTPUT
VREF Input Voltage5
DC Leakage Current4
VREFOUT Output Voltage
VREFOUT Temperature Coefficient
2.5
1
2.5
25
5
10
130
10
15
25
V
µA max
V
ppm/ꢁC max
ppm/ꢁC typ
µV typ
µV typ
Ω typ
VREF Noise
0.1 Hz to 10 Hz bandwidth
0.1 Hz to 1 MHz bandwidth
VREF Output Impedance
VREF Input Capacitance
pF typ
pF typ
When in track
When in hold
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
5
V min
V max
µA max
pF max
Typically 10 nA, VIN = 0 V or VDRIVE
4
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance4
Output Coding
2.4
0.4
3
V min
ISOURCE = 200 µA
ISINK = 200 µA
V max
µA max
pF max
10
Straight (natural) binary
CODING bit = 0
CODING bit = 1
Twos complement
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
t2 + 13 tCLK
125
ns
ns max
Full-scale step input
Sine wave input
80
ns typ
Throughput Rate
625
kSPS max
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
V min/max
V min/max
VDRIVE
6
IDD
Digital I/PS = 0 V or VDRIVE
VDD = 2.7 V to 5.25 V, SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
FSAMPLE = 100 kSPS, VDD = 5 V
Static, VDD = 3 V
Normal Mode (Static)
Normal Mode (Operational)
0.8
1.5
1.2
0.3
160
2
mA typ
mA max
mA max
mA typ
µA typ
Autostandby Mode
Full/Autoshutdown Mode (Static)
Power Dissipation
µA max
SCLK on or off
Normal Mode (Operational)
7.5
3.6
800
480
10/6
mW max
mW max
µW typ
µW typ
µW max
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V/3 V
Autostandby Mode (Static)
Full/Autoshutdown Mode
1 Temperature range is as follows: B Version: –40ꢁC to +85ꢁC.
2 See the Terminology section.
3 VCM is the common-mode voltage. For full common-mode range, see Figure 25 and Figure 26. VIN+ and VIN− must always remain within GND/VDD
.
4 Sample tested during initial release to ensure compliance.
5 This device is operational with an external reference in the range 0.1 V to VDD. See the Reference Section for more information.
6 Measured with a midscale dc analog input.
Rev. A | Page 4 of 28
AD7934-6
TIMING SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. FCLKIN = 10 MHz, FSAMPLE = 625 kSPS,
TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1 Limit at TMIN, TMAX
Unit
Description
2
fCLKIN
700
10
kHz min
MHz max
ns min
CLKIN Frequency
tQUIET
30
Minimum time between end of read and start of next conversion, that is, time from
when the data bus goes into three-state until the next falling edge of CONVST
t1
10
15
50
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
CONVST Pulse Width
t2
CONVST Falling Edge to CLKIN Falling Edge Setup Time
CLKIN Falling Edge to BUSY Rising Edge
CS to WR Setup Time
t3
t4
t5
0
CS to WR Hold Time
t6
10
10
10
10
0
WR Pulse Width
t7
Data Setup Time Before WR
Data Hold after WR
t8
t9
New Data Valid Before Falling Edge of BUSY
CS to RD Setup Time
t10
t11
t12
0
CS to RD Hold Time
30
30
3
RD Pulse Width
3
t13
Data Access Time After RD
Bus Relinquish Time After RD
Bus Relinquish Time After RD
HBEN to RD Setup Time
4
t14
50
0
t15
t16
t17
t18
t19
t20
t21
t22
0
HBEN to RD Hold Time
10
0
Minimum Time Between Reads/Writes
HBEN to WR Setup Time
10
40
15.7
7.8
HBEN to WR Hold Time
CLKIN Falling Edge to BUSY Falling Edge
CLKIN Low Pulse Width
CLKIN High Pulse Width
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10ꢀ to 90ꢀ of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given above are with a 25 pF load capacitance. See Figure 34, Figure 35, Figure 36, and Figure 37.
2 Minimum CLKIN for specified performance. With slower CLKIN frequencies, performance specifications apply typically.
3 The time required for the output to cross 0.4 V or 2.4 V.
4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
Rev. A | Page 5 of 28
AD7934-6
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to AGND/DGND
−0.3 V to +7 V
VDRIVE to AGND/DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
VDRIVE to VDD
Digital Output Voltage to DGND
VREFIN to AGND
−0.3 V to VDD +0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3V to VDRIVE + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +0.3 V
10 mA
AGND to DGND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Reflow Temperature (10 sec to 30 sec)
ESD
−40ꢁC to +85ꢁC
−65ꢁC to +150ꢁC
150ꢁC
97.9ꢁC/W (TSSOP)
14ꢁC/W (TSSOP)
255ꢁC
1.5 kV
1 Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 28
AD7934-6
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
V
3
DD
IN
W/B
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
V
V
V
V
2
1
0
IN
IN
IN
3
4
AD7934-6
TOP VIEW
(Not to Scale)
5
/V
REFIN REFOUT
6
AGND
CS
7
8
RD
9
WR
10
11
12
13
14
CONVST
CLKIN
BUSY
DB11
DB10
V
DRIVE
DGND
DB8/HBEN
DB9
Figure 2. Pin Configuration
Table 5. Pin Function Description
Pin No.
Mnemonic
Description
1
VDD
Power Supply Input. The VDD range for the AD7934-6 is from 2.7 V to 5.25 V. The supply should be decoupled
to AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.
2
B
W/
Word/Byte Input. When this input is logic high, word transfer mode is enabled, and data is transferred to and
B
from the AD7934-6 in 12-bit words on Pin DB0 to Pin DB11. When W/ is logic low, byte transfer mode is
enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN
functionality. When operating in byte transfer mode, unused data lines should be tied off to DGND.
3 to 10
11
DB0 to DB7
VDRIVE
Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result, and allow the control
register to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for
these pins are determined by the VDRIVE input.
Logic Power Supply Input. The voltage supplied at this pin determines what voltage the parallel interface of
the AD7934-6 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that
at VDD, but should never exceed VDD by more than 0.3 V.
12
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7934-6. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same
potential, and must not be more than 0.3 V apart, even on a transient basis.
13
DB8/HBEN
B
Data Bit 8/High Byte Enable. When W/ is high, this pin acts as Data Bit 8, a three-state I/O pin that is
CS RD WR B
. When W/ is low, this pin acts as the high byte enable pin. When HBEN is low,
controlled by
,
, and
the low byte of data written to or read from the AD7934-6 is on DB0 to DB7. When HBEN is high, the top four
bits of the data being written to or read from the AD7934-6 are on DB0 to DB3. When reading from the device,
DB4 and DB5 of the high byte contain the ID of the channel corresponding to the conversion result (see the
channel address bits in Table 9). DB6 and DB7 are always 0. When writing to the device, DB4 to DB7 of the high
byte must all be 0s.
14 to 16
17
DB9 to DB11
BUSY
Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and allow the control
register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low
voltage levels for these pins are determined by the VDRIVE input.
Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the
falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete
and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track
mode just prior to the falling edge of BUSY, on the 13th rising edge of SCLK (see Figure 34).
18
19
CLKIN
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7934-6 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the
conversion time and achievable throughput rate. The CLKIN signal can be a continuous or burst clock.
Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes
from track to hold mode on the falling edge of CONVST, and the conversion process is initiated at this point.
Following power-down, when operating in the autoshutdown or autostandby mode, a rising edge on
CONVST is used to power up the device.
CONVST
20
WR
Write Input. Active low logic input used in conjunction with CS to write data to the control register.
Rev. A | Page 7 of 28
AD7934-6
Pin No.
Mnemonic
Description
21
RD
Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion
result is placed on the data bus following the falling edge of RD read while CS is low.
22
23
CS
Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or write data
to the control register.
Analog Ground. This is the ground reference point for all analog circuitry on the AD7934-6. All analog input
signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient
basis.
AGND
24
VREFIN/VREFOUT
Reference Input/Output. This pin is connected to the internal reference, and is the reference source for the
ADC. The nominal internal reference voltage is 2.5 V, and it appears at this pin. It is recommended that this pin
be decoupled to AGND with a 470 nF capacitor. This pin can be overdriven by an external reference. The input
voltage range for the external reference is 0.1 V to VDD; however, care must be taken to ensure that the analog
input range does not exceed VDD + 0.3 V. See the Reference Section.
25 to 28
VIN0 to VIN3
Analog Input 0 to Analog Input 3. Four analog input channels that are multiplexed into the on-chip track-and-
hold. The analog inputs can be programmed to be four single-ended inputs, two fully differential pairs, or two
pseudo differential pairs by setting the MODE bits in the control register appropriately (see Table 9). The
analog input channel to be converted can be selected either by writing to the address bits (ADD1 and ADD0)
in the control register prior to the conversion, or by using the on-chip sequencer. The input range for all input
channels can be either 0 V to VREF, or 0 V to 2 × VREF, and the coding can be binary or twos complement,
depending on the states of the RANGE and CODING bits in the control register. Any unused input channels
should be connected to AGND to avoid noise pickup.
Rev. A | Page 8 of 28
AD7934-6
TERMINOLOGY
Integral Nonlinearity (INL)
Negative Gain Error
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range, with −VREF to
+VREF biased about the VREF point. It is the deviation of the first
code transition (100 … 000) to (100 … 001) from the ideal
(that is, −VREF + 1 LSB) after the zero-code error has been
adjusted out.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Negative Gain Error Match
This is the difference in negative gain error between any two
channels.
Offset Error
This is the deviation of the first code transition (00 … 000) to
(00 … 001) from the ideal (that is, AGND + 1 LSB).
Channel-to-Channel Isolation
This is a measure of the level of crosstalk between channels.
It is measured by applying a full-scale sine wave signal to the
three, nonselected input channels and applying a 50 kHz signal
to the selected channel. The channel-to-channel isolation is
defined as the ratio of the power of the 50 kHz signal on the
selected channel to the power of the noise signal on the unse-
lected channels that appears in the fast Fourier transform (FFT)
of this channel. The noise frequency on the unselected channels
varies from 40 kHz to 740 kHz. The noise amplitude is at
2 × VREF, while the signal amplitude is at 1 × VREF. See Figure 4.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 … 110) to
(111 … 111) from the ideal (that is, VREF – 1 LSB) after the
offset error has been adjusted out.
Gain Error Match
This is the difference in gain error between any two channels.
Power Supply Rejection Ratio (PSRR)
Zero-Code Error
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency (f) to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency fS. The frequency
of the noise varies from 1 kHz to 1 MHz.
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range, with −VREF to
+VREF biased about the VREF point. It is the deviation of the
midscale transition (all 0s to all 1s) from the ideal VIN voltage
(that is, VREF).
PSRR (dB) = 10log(Pf/PfS)
where:
Zero-Code Error Match
This is the difference in zero-code error between any two
channels.
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Positive Gain Error
Common-Mode Rejection Ratio (CMRR)
This applies when using the twos complement output coding
option, in particular to the 2 × VREF input range, with −VREF to
+VREF biased about the VREF point. It is the deviation of the last
code transition (011 … 110) to (011 … 111) from the ideal (that
is, +VREF – 1 LSB) after the zero-code error has been adjusted out.
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency (f) to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency fS.
CMRR (dB) = 10log(Pf/PfS)
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
where:
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Rev. A | Page 9 of 28
AD7934-6
Track-and-Hold Acquisition Time
Peak Harmonic or Spurious Noise
The track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±± LSB, after the end of conversion.
This is defined as the ratio of the rms value of the next largest
component in the ADC output spectrum (up to fS/2 and
excluding dc) to the rms value of the fundamental. Normally,
the value of this specification is determined by the largest
harmonic in the spectrum, but for ADCs where the harmonics
are buried in the noise floor, it is a noise peak.
Signal-to-Noise and Distortion Ratio (SINAD)
This is the measured ratio of signal-to-noise and distortion at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa − fb),
while the third-order terms include (2fa + fb), (2fa − fb), (fa +
2fb), and (fa − 2fb).
The theoretical SINAD ratio for an ideal N-bit converter with a
sine wave input is given by:
SINAD = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, SINAD is 74 dB.
The AD7934-6 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second-order terms are usually distanced
in frequency from the original sine waves, while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals, expressed in dBs.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7934-6, it is defined as:
V22 +V32 +V42 +V52 +V6
2
THD
(
dB = −20log
)
V1
where :
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Rev. A | Page 10 of 28
AD7934-6
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–60
100mV p-p SINE WAVE ON V AND/OR V
DD
NO DECOUPLING
DIFFERENTIAL/SINGLE-ENDED MODE
4096 POINT FFT
DRIVE
V
= 5V
DD
F
= 625kSPS
SAMPLE
–70
–80
F
= 49.62kHz
IN
SINAD = 70.94dB
THD = –90.09dB
DIFFERENTIAL MODE
INT REF
–90
EXT REF
–100
–110
–120
–100
–110
10
210
410
610
810
1010
SUPPLY RIPPLE FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 3. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
Figure 6. FFT @ VDD = 5 V
1.0
0.8
0.6
–70
V
= 5V
INTERNAL/EXTERNAL REFERENCE
DD
DIFFERENTIAL MODE
V
= 5V
DD
–75
0.4
0.2
–80
–85
0
–0.2
–0.4
–0.6
–0.8
–1.0
–90
–195
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
100
200
300
400
500
600
700
800
NOISE FREQUENCY (kHz)
Figure 4. Channel-to-Channel Isolation
Figure 7. Typical DNL @ VDD = 5 V
1.0
0.8
0.6
80
70
60
50
40
30
20
V
= 5V
DD
V
= 5V
DD
DIFFERENTIAL MODE
V
= 3V
0.4
0.2
DD
0
–0.2
–0.4
–0.6
–0.8
–1.0
F
= 625kSPS
SAMPLE
RANGE = 0 TO V
DIFFERENTIAL MODE
REF
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
Figure 8. Typical INL @ VDD = 5 V
Figure 5. SINAD vs. Analog Input Frequency for Various Supply Voltages
Rev. A | Page 11 of 28
AD7934-6
4
10000
9000
8000
7000
6000
5000
4000
3000
9997
CODES
INTERNAL
REF
SINGLE-ENDED MODE
DIFFERENTIAL MODE
3
2
1
POSITIVE DNL
NEGATIVE DNL
0
2000
1000
0
3 CODES
2049 2050
–1
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75
2046
2047
2048
V
(V)
CODE
REF
Figure 9. DNL vs. VREF for VDD = 3 V
Figure 12. Histogram of Codes for 10 k Samples @ VDD = 5 V
with the Internal Reference
12
–60
DIFFERENTIAL MODE
11
10
–70
–80
V
= 5V
DD
DIFFERENTIAL MODE
V
= 5V
DD
SINGLE-ENDED MODE
9
8
–90
V
= 3V
DD
SINGLE-ENDED MODE
–100
V
= 3V
DD
DIFFERENTIAL MODE
7
6
–110
–120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
200
400
600
800
1000
1200
V
(V)
RIPPLE FREQUENCY (kHz)
REF
Figure 10. ENOB vs. VREF
Figure 13. CMRR vs. Input Frequency with VDD = 5 V and 3 V
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
V
= 5V
DD
V
= 3V
DD
–4.0
–4.5
–5.0
SINGLE-ENDED MODE
2.5 3.0 3.5
0
0.5
1.0
1.5
V
2.0
(V)
REF
Figure 11. Offset vs. VREF
Rev. A | Page 12 of 28
AD7934-6
CONTROL REGISTER
The control register on the AD7934-6 is a 12-bit, write-only register. Data is written to this register using the
and
pins. The
WR
CS
control register is shown in Table 6 and the functions of the bits are described in Table 7. At power-up, the default bit settings in the
control register are all 0s.
Table 6. Control Register Bits
MSB
DB11
PM1
LSB
DB10
PM0
DB9
CODING
DB8
REF
DB7
ZERO
DB6
ADD1
DB5
ADD0
DB4
MODE1
DB3
MODE0
DB2
SEQ1
DB1
SEQ0
DB0
RANGE
Table 7. Control Register Bit Function Description
Bit No.
Mnemonic Description
11, 10
PM1, PM0
CODING
REF
Power management bits used to select the power mode of operation. The user can choose between normal mode
and various power-down modes of operation as shown in Table 8.
Selects the output coding of the conversion result. If set to 0, the output coding is straight (natural) binary. If set to
1, the output coding is twos complement.
Selects whether the internal or external reference is used to perform the conversion. If this bit is Logic 0, an
external reference should be applied to the VREF pin. If this bit is Logic 1, the internal reference is selected. See the
Reference Section.
9
8
7
ZERO
Not used. This bit should always be set to Logic 0.
6, 5
ADD1,
ADD0
Two address bits that either select which analog input channel is to be converted in the next conversion, if the
sequencer is not used, or select the final channel in a consecutive sequence when the sequencer is used as
described in Table 10. The selected input channel is decoded as shown in Table 9.
4, 3
MODE1,
MODE0
Two mode pins that select the type of analog input on the four VIN pins. The AD7934-6 has four single-ended
inputs, two fully differential inputs, or two pseudo differential inputs. See Table 9.
2
1
0
SEQ1
SEQ0
RANGE
Used in conjunction with the SEQ0 bit to control the sequencer function. See Table 10.
Used in conjunction with the SEQ1 bit to control the sequencer function. See Table 10.
Selects the analog input range of the AD7934-6. If set to 0, the analog input range extends from 0 V to VREF. If it
is set to 1, the analog input range extends from 0 V to 2 × VREF. When this range is selected, AVDD must be 4.75 V to
5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that the analog input remains within
the supply rails. See the Analog Input Configurations section for more information.
Table 8. Power Mode Selection Using the Power Management Bits in the Control Register
PM1 PM0 Mode
Description
0
0
0
1
Normal Mode
When operating in normal mode, all circuitry is fully powered up at all times.
Autoshutdown When operating in autoshutdown mode, the AD7934-6 enters full shutdown mode at the end of each
conversion. In this mode, all circuitry is powered down.
1
0
Autostandby
When the AD7934-6 enters this mode, the reference remains fully powered, the reference buffer is partially
powered down, and all other circuitry is fully powered down. This mode is similar to autoshutdown mode,
but it allows the part to power-up in 7 µs (or 600 ns if an external reference is used). See the Power Modes
of Operation section for more information.
1
1
Full Shutdown When the AD7934-6 enters this mode, all circuitry is powered down. The information in the control register
is retained.
Table 9. Analog Input Type Selection
MODE0 = 0, MODE1 = 0
MODE0 = 0, MODE1 = 1
MODE0 = 1, MODE1 = 0
MODE0 = 1, MODE1 = 1
Not Used
Four Single-Ended I/P
Channels
Two Fully Differential
I/P Channels
Two Pseudo Differential
I/P Channels
Channel Address
ADD1
ADD0
VIN+
VIN−
VIN+
VIN−
VIN+
VIN−
0
0
1
1
0
1
0
1
VIN0
VIN1
VIN2
VIN3
AGND
AGND
AGND
AGND
VIN0
VIN1
VIN2
VIN3
VIN1
VIN0
VIN3
VIN2
VIN0
VIN1
VIN2
VIN3
VIN1
VIN0
VIN3
VIN2
Rev. A | Page 13 of 28
AD7934-6
SEQUENCER OPERATION
The configuration of the SEQ0 and SEQ1 bits in the control register allow the user to use the sequencer function. Table 10 outlines the
two sequencer modes of operation.
Table 10. Sequence Selection Modes
SEQ0 SEQ1 Sequence Type
0
0
This configuration is selected when the sequence function is not used. The analog input channel selected on each
individual conversion is determined by the contents of the channel address bits, ADD1 and ADD0, in each prior write
operation. This mode of operation reflects the normal operation of a multichannel ADC, without the sequencer function
being used, where each write to the AD7934-6 selects the next channel for conversion.
0
1
1
1
0
1
Not used.
Not used.
This configuration is used in conjunction with the channel address bits, ADD1 and ADD0, to program continuous
conversions on a consecutive sequence of channels from Channel 0 to a selected final channel, as determined by
the channel address bits in the control register. When in differential or pseudo-differential mode, inverse channels
(for example, VIN1, VIN0) are not converted in this mode.
NOTE ON WRITING TO THE CONTROL REGISTER TO PROGRAM THE SEQUENCER
The AD7933 and AD7934 need 13 full CLKIN periods to perform a conversion. If the ADC does not receive the full 13 CLKIN periods,
CONVST
the conversion is aborted. If a conversion is aborted after applying 12.5 CLKIN periods to the ADC, ensure that a rising edge of
or a falling edge of CLKIN is applied to the part before writing to the control register to program the sequencer. If these conditions are not
met, then the sequencer is not in the correct state to handle being reprogrammed for another sequence of conversions. As a result, the
performance of the converter is not guaranteed.
Rev. A | Page 14 of 28
AD7934-6
CIRCUIT INFORMATION
The AD7934-6 is a fast, 4-channel, 12-bit, single-supply,
successive approximation analog-to-digital converter.
The part operates from a 2.7 V to 5.25 V power supply
and features throughput rates up to 625 kSPS.
When the ADC starts a conversion (Figure 15), SW3 opens, and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the output code of the ADC. The output impedances
of the sources driving the VIN+ and the VIN− pins must match;
otherwise, the two inputs have different settling times,
resulting in errors.
The AD7934-6 provides the user with an on-chip track-and-
hold, an accurate internal reference, an analog-to-digital
converter, and a parallel interface housed in a 28-lead TSSOP
package.
The AD7934-6 has four analog input channels that can be
configured to be four single-ended inputs, two fully differential
pairs or two pseudo differential pairs. An on-chip channel
sequencer allows the user to select a consecutive sequence of
channels through which the ADC can cycle with each falling
CAPACITIVE
DAC
COMPARATOR
edge of
.
CONVST
C
B
A
S
V
V
IN+
SW1
CONTROL
LOGIC
The analog input range for the AD7934-6 is 0 to VREF or 0 to
2 × VREF, depending on the status of the RANGE bit in the
control register. The output coding of the ADC can be either
straight binary or twos complement, depending on the status of
the CODING bit in the control register.
SW3
SW2
A
B
IN–
C
S
V
REF
CAPACITIVE
DAC
Figure 15. ADC Conversion Phase
The AD7934-6 provides flexible power management options to
allow users to achieve the best power performance for a given
throughput rate. These options are selected by programming
the power management bits, PM1 and PM0, in the control
register.
ADC TRANSFER FUNCTION
The output coding for the AD7934-6 is either straight binary or
twos complement, depending on the status of the CODING bit
in the control register. The designed code transitions occur at
successive LSB values (that is, 1 LSB, 2 LSBs, and so on), and the
LSB size is VREF/4096. The ideal transfer characteristics of the
AD7934-6 for both straight binary and twos complement output
coding are shown in Figure 16 and Figure 17, respectively.
CONVERTER OPERATION
The AD7934-6 is a successive approximation ADC based on
two capacitive digital-to-analog converters (DACs). Figure 14
and Figure 15 show simplified schematics of the ADC in
acquisition and conversion phase, respectively. The ADC
comprises control logic, SAR, and two capacitive DACs. Both
figures show the operation of the ADC in differential/pseudo
differential mode. Single-ended mode operation is similar but
VIN− is internally tied to AGND. In the acquisition phase, SW3
is closed, SW1 and SW2 are in Position A, the comparator is
held in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
111...111
111...110
111...000
011...111
1 LSB = V
/4096
REF
000...010
000...001
000...000
CAPACITIVE
DAC
COMPARATOR
C
B
A
S
1 LSB
+V – 1 LSB
REF
0V
V
V
IN+
SW1
ANALOG INPUT
CONTROL
LOGIC
SW3
SW2
NOTE: V
REF
IS EITHER V OR 2 × V
REF REF
A
B
IN–
C
S
Figure 16. Ideal Transfer Characteristic with Straight Binary Output Coding
V
REF
CAPACITIVE
DAC
Figure 14. ADC Acquisition Phase
Rev. A | Page 15 of 28
AD7934-6
ANALOG INPUT STRUCTURE
1 LSB = 2 × V
/4096
REF
Figure 19 shows the equivalent circuit of the analog input
structure of the AD7934-6 in differential/pseudo differential
mode. In single-ended mode, VIN− is internally tied to AGND.
The four diodes provide ESD protection for the analog inputs.
Care must be taken to ensure that the analog input signals never
exceed the supply rails by more than 300 mV. This causes the
diodes to become forward-biased and start conducting into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
–V
+ 1 LSB
V
REF
+V – 1 LSB
REF
The C1 capacitors in Figure 19 are typically 4 pF, and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the sampling capacitors of the ADC and
typically have a capacitance of 45 pF.
REF
Figure 17. Ideal Transfer Characteristic
with Twos Complement Output Coding and 2 x VREF Range
TYPICAL CONNECTION DIAGRAM
Figure 18 shows a typical connection diagram for the
AD7934-6. The AGND and DGND pins are connected
together at the device for good noise suppression. The
VREFIN/VREFOUT pin is decoupled to AGND with a 0.47 µF
capacitor to avoid noise pickup if the internal reference is
used. Alternatively, VREFIN/VREFOUT can be connected to an
external reference source. In this case, the reference pin
should be decoupled with a 0.1 µF capacitor. In both cases, the
analog input range can either be 0 V to VREF (RANGE bit = 0)
or 0 V to 2 × VREF (RANGE bit = 1). The analog input configu-
ration is either four single-ended inputs, two differential pairs
or two pseudo differential pairs (see Table 9). The VDD pin
connects to either a 3 V or 5 V supply. The voltage applied to
the VDRIVE input controls the voltage of the digital interface.
Here in Figure 18 it is connected to the same 3 V supply of the
microprocessor to allow a 3 V logic interface (see the Digital
Inputs section).
V
DD
D
R1
C2
V
+
IN
D
C1
V
DD
D
D
R1
C2
V
–
IN
C1
Figure 19. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC low-
pass filter on the relevant analog input pins. In applications where
harmonic distortion and signal-to-noise ratio are critical, the
analog input should be driven from a low impedance source.
Large source impedances significantly affect the ac performance
of the ADC. This can necessitate the use of an input buffer
amplifier. The choice of the op amp is a function of the
particular application.
3V/5V
SUPPLY
0.1µF
10µF
V
V
DD
AD7934-6
W/B
CLKIN
CS
0
IN
IN
0 TO V
/
REF
RD
0 TO 2 × V
REF
V
3
µC/µP
WR
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of THD that can be
tolerated. The THD increases as the source impedance increases
and performance degrades. Figure 20 and Figure 21 show a
graph of the THD vs. source impedance with a 50 kHz input
tone for both VDD = 5 V and 3 V, in single-ended mode and
differential mode, respectively.
BUSY
CONVST
DB0
AGND
DGND
DB11/DB9
V
/V
REFIN REFOUT
V
DRIVE
0.1µF
10µF
3V
SUPPLY
2.5V
V
REF
0.1µF EXTERNAL V
REF
0.47µF INTERNAL V
REF
Figure 18. Typical Connection Diagram
Rev. A | Page 16 of 28
AD7934-6
–40
ANALOG INPUT CONFIGURATIONS
F
= 50kHz
IN
–45
–50
–55
–60
–65
The AD7934-6 has software selectable analog input
configurations. The user can choose either four single-
ended inputs, two fully differential pairs, or two pseudo
differential pairs. The analog input configuration is chosen
by setting the MODE0/MODE1 bits in the internal control
register (see Table 9).
V
= 3V
DD
–70
–75
–80
Single-Ended Mode
V
= 5V
DD
The AD7934-6 can have four single-ended analog input
channels by setting the MODE0 and MODE1 bits in the control
register to 0. In applications where the signal source has a high
impedance, it is recommended to buffer the analog input before
applying it to the ADC. An op amp suitable for this function is
the AD8021. The analog input range of the AD7934-6 can be
–85
–90
10
100
1k
R
(Ω)
SOURCE
Figure 20. THD vs. Source Impedance in Single-Ended Mode
programmed to be either 0 to VREF or 0 to 2 × VREF
.
–60
F
= 50kHz
IN
–65
–70
–75
–80
–85
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it the correct format for the ADC.
Figure 23 shows a typical connection diagram when operating
the ADC in single-ended mode. This diagram shows a bipolar
signal of amplitude ±1.25 V being preconditioned before it is
applied to the AD7934-6. In cases where the analog input
amplitude is ±2.5 V, the 3R resistor can be replaced with a
resistor of value R. The resultant voltage on the analog input of
the AD7934-6 is a signal ranging from 0 V to 5 V. In this case,
the 2 × VREF mode can be used.
V
= 3V
DD
–90
–95
V
= 5V
DD
–100
10
100
1k
R
(Ω)
SOURCE
+2.5V
R
Figure 21. THD vs. Source Impedance in Differential Mode
+1.25V
0V
R
0V
V
IN
Figure 22 shows a graph of the THD vs. the analog input
frequency for various supplies, while sampling at 625 kHz with
an SCLK of 10 MHz. In this case, the source impedance is 10 Ω.
V
V
–1.25V
IN0
IN7
3R
AD7934-61
R
–50
V
REFOUT
V
= 3V
DD
SINGLE-ENDED MODE
–60
–70
0.47µF
V
= 5V
DD
SINGLE-ENDED MODE
1
ADDITIONAL PINS OMITTED FOR CLARITY.
–80
–90
Figure 23. Single-Ended Mode Connection Diagram
V
= 5V/3V
DD
DIFFERENTIAL MODE
Differential Mode
–100
The AD7934-6 can have two differential analog input pairs by
setting the MODE0 and MODE1 bits in the control register to
0 and 1, respectively.
–110
–120
F
= 625kSPS
SAMPLE
RANGE = 0 TO V
REF
200
INPUT FREQUENCY (kHz)
0
100
300
400
500
600
700
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection, and improvements in distortion
performance. Figure 24 defines the fully differential analog
input of the AD7934-6.
Figure 22. THD vs. Analog Input Frequency for Various Supply Voltages
Rev. A | Page 17 of 28
AD7934-6
4.5
4.0
T
= 25°C
A
V
REF
p-p
V
V
IN+
AD7934-6*
3.5
3.0
V
REF
p-p
IN–
COMMON-MODE
VOLTAGE
2.5
2.0
1.5
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. Differential Input Definition
1.0
The amplitude of the differential signal is the difference between
the signals applied to the VIN+ and VIN− pins in each differential
pair (that is, VIN+ − VIN−). VIN+ and VIN− should be simultaneously
driven by two signals, each of amplitude VREF (or 2 × VREF
depending on the range chosen), which are 180° out of phase.
The amplitude of the differential signal is therefore −VREF to +VREF
peak-to-peak (that is, 2 × VREF), regardless of the common mode
(CM). The common mode is the average of the two signals,
(VIN+ + VIN−)/2, and is therefore the voltage on which the two
inputs are centered. This results in the span of each input being
CM ± VREF/2. This voltage must be set up externally, and its
range varies with the reference value VREF. As the value of VREF
increases, the common-mode range decreases. When driving the
inputs with an amplifier, the actual common-mode range is
determined by the amplifier’s output voltage swing.
0.5
0
0.1
0.6
1.1
1.6
2.1
2.6
V
(V)
REF
Figure 26. Input Common-Mode Range vs. VREF (2 × VREF Range, VDD = 5 V)
Driving Differential Inputs
Differential operation requires that VIN+ and VIN− be
simultaneously driven with two equal signals that are 180° out
of phase. The common mode must be set up externally and has
a range that is determined by VREF, the power supply, and the
particular amplifier used to drive the analog inputs. Differential
modes of operation with either an ac or a dc input provide the
best THD performance over a wide frequency range. Not all
applications have a signal preconditioned for differential
operation, so there is often a need to perform single-ended-to-
differential conversion.
Figure 25 and Figure 26 show how the common-mode range
typically varies with VREF for a 5 V power supply using the
0 to VREF range or 0 to 2 × VREF range, respectively. The common
mode must be in this range to guarantee the functionality of the
AD7934-6.
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential
signal to one of the analog input pairs of the AD7934-6. The
circuit configurations shown in Figure 27 and Figure 28 show
how a dual op amp can be used to convert a single-ended signal
into a differential signal for both a bipolar and unipolar input
signal, respectively.
When a conversion takes place, the common mode is rejected.
This results in a virtually noise-free signal of amplitude −VREF
to +VREF, corresponding to the digital codes 0 to 4096. If the 0 to
2 × VREF range is used, then the input signal amplitude extends
from −2 VREF to +2 VREF
.
The voltage applied to Point A sets up the common-mode
voltage. In both diagrams, it is connected in some way to the
reference, but any value in the common-mode range can be
input here to set up the common mode. A suitable dual op amp
for use in this configuration to provide differential drive to the
AD7934-6 is the AD8022.
3.5
T
= 25°C
A
3.0
2.5
2.0
1.5
1.0
It is advisable to take care when choosing the op amp; the
selection depends on the required power supply and system
performance objectives. The driver circuits in Figure 27 and
Figure 28 are optimized for dc coupling applications requiring
best distortion performance. The circuit configuration in
Figure 27 converts and level shifts a single-ended, ground-
referenced, bipolar signal to a differential signal centered at
the VREF level of the ADC. The circuit configuration shown in
Figure 28 converts a unipolar, single-ended signal into a
differential signal.
0.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
(V)
REF
Figure 25. Input Common-Mode Range vs. VREF (0 to VREF Range, VDD = 5 V)
Rev. A | Page 18 of 28
AD7934-6
220Ω
V+
V
p-p
REF
2
×
V
p-p
REF
V
V
IN+
440Ω
3.75V
GND
27Ω
AD7934-6*
2.5V
1.25V
V–
IN–
V
IN+
220Ω
V
REF
220Ω
220Ω
V+
AD7934-6
DC INPUT
VOLTAGE
0.47µF
V
IN–
V
REF
3.75V
2.5V
1.25V
27Ω
A
*ADDITIONAL PINS OMITTED FOR CLARITY
V–
Figure 29. Pseudo Differential Mode Connection Diagram
0.47µF
10kΩ
20kΩ
ANALOG INPUT SELECTION
As shown in Table 9, users can set up their analog input con-
figuration by setting the values in the MODE0 and MODE1 bits
in the control register. Assuming the configuration has been
chosen, there are two different ways of selecting the analog
input to be converted, depending on the state of the SEQ0 and
SEQ1 bits in the control register.
Figure 27. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal
into a Differential Unipolar Signal
220Ω
V
p-p
REF
V
V+
REF
440Ω
3.75V
27Ω
2.5V
1.25V
GND
Traditional Multichannel Operation (SEQ0 = SEQ1 = 0)
V–
V
IN+
Any one of four analog input channels or two pairs of channels
can be selected for conversion in any order by setting the SEQ0
and SEQ1 bits in the control register to 0. The channel to be
converted is selected by writing to the address bits, ADD1 and
ADD0, in the control register to program the multiplexer prior to
the conversion. This mode of operation is that of a traditional
multichannel ADC, where each data write selects the next
channel for conversion. Figure 30 shows a flow chart of this mode
of operation. The channel configurations are shown in Table 9.
220Ω
220Ω
V+
AD7934-6
V
IN–
V
REF
3.75V
2.5V
1.25V
27Ω
A
V–
0.47µF
10kΩ
Figure 28. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
into a Differential Signal
POWER ON
Another method of driving the AD7934-6 is to use the AD8138
differential amplifier. The AD8138 can be used as a single-
ended-to-differential amplifier or as a differential-to-differential
amplifier. The device is as easy to use as an op amp and greatly
simplifies differential signal amplification and driving.
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT,
AND OUTPUT CONFIGURATION.
SET SEQ0 = SEQ1 = 0. SELECT THE DESIRED
CHANNEL TO CONVERT ON (ADD1 TO ADD0).
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
Pseudo Differential Mode
The AD7934-6 can have two pseudo differential pairs by setting
the MODE0 and MODE1 bits in the control register to 1 and 0,
respectively. VIN+ is connected to the signal source, which must
have an amplitude of VREF (or 2 × VREF depending on the range
chosen) to make use of the full dynamic range of the part. A dc
input is applied to the VIN− pin. The voltage applied to this input
provides an offset from ground or a pseudo ground for the VIN+
input.
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED ON BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SET SEQ0 = SEQ1 = 0.
Figure 30. Traditional Multichannel Operation Flow Chart
Using the Sequencer: Consecutive Sequence
(SEQ0 = SEQ1 = 1)
A sequence of consecutive channels can be converted beginning
with Channel 0, and ending with a final channel selected by
writing to the ADD1 and ADD0 bits in the control register. This
is done by setting the SEQ0 and SEQ1 bits in the control
register to 1. In this mode, once the control register is written
to, the next conversion is on Channel 0, then Channel 1, and so
on, until the channel selected by the address bits (ADD1 and
ADD0) is reached.
The benefit of pseudo differential inputs is that they separate the
analog input signal ground from the ADC ground, allowing dc
common-mode voltages to be cancelled. Typically, the voltage
range for the VIN− pin while in pseudo differential mode can
extend from −0.3 V to +0.7 V when VDD = 3 V, or from −0.3 V to
+1.8V when VDD = 5 V. Figure 29 shows a connection diagram for
the pseudo differential mode.
Rev. A | Page 19 of 28
AD7934-6
The ADC then returns to Channel 0 and starts the sequence
In all cases, the specified reference is 2.5 V.
again. The
input must be kept high to ensure that the control
WR
The performance of the part with different reference values is
shown in Figure 9 , Figure 10, and Figure 11. The value of the
reference sets the analog input span and the common-mode
voltage range. Errors in the reference source result in gain
errors in the AD7934-6 transfer function and add to the
specified full-scale errors on the part.
register is not accidentally overwritten and the sequence inter-
rupted. This pattern continues until the AD7934-6 is written to.
Figure 31 shows the flowchart of the consecutive sequence mode.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT,
AND OUTPUT CONFIGURATION. SELECT
FINAL CHANNEL (ADD1 AND ADD0) IN
CONSECUTIVE SEQUENCE.
Table 11 lists suitable voltage references available from Analog
Devices that can be used. Figure 33 shows a typical connection
diagram for an external reference.
SET SEQ0 = SEQ1 = 1.
Table 11. Examples of Suitable Voltage References
CONTINUOUSLY CONVERT ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0
UP TO AND INCLUDING THE PREVIOUSLY
SELECTED FINAL CHANNEL ON ADD1 AND ADD0
WITH EACH CONVST PULSE.
Output
Initial Accuracy Operating
Reference Voltage
(ꢀ max)
Current (µA)
AD780
ADR421
ADR420
2.5/3
2.5
2.048
0.04
0.04
0.05
1000
500
500
Figure 31. Consecutive Sequence Mode Flow Chart
REFERENCE SECTION
The AD7934-6 can operate with either the on-chip reference or
external reference. The internal reference is selected by setting
the REF bit in the internal control register to 1. A block diagram
of the internal reference circuitry is shown in Figure 32. The
internal reference circuitry includes an on-chip 2.5 V band gap
reference and a reference buffer. When using the internal refer-
ence, the VREFIN/VREFOUT pin should be decoupled to AGND with
a 0.47 µF capacitor. This internal reference not only provides
the reference for the analog-to-digital conversion, but it can also
be used externally in the system. It is recommended that the
reference output is buffered using an external precision op amp
before applying it anywhere in the system.
AD7934-6*
AD780
V
NC
1
2
3
4
O/PSELECT
8
7
6
5
NC
NC
REF
V
+V
IN
DD
2.5V
TEMP
GND
V
OUT
0.1µF
10nF
0.1µF
0.1µF
TRIM
NC
NC = NO CONNECT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 33. Typical VREF Connection Diagram
Digital Inputs
The digital inputs applied to the AD7934-6 are not limited by
the maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V. They are not restricted by
the AVDD + 0.3 V limit that is on the analog inputs.
BUFFER
REFERENCE
V
/
REFIN
V
REFOUT
ADC
AD7934-6
Another advantage of the digital inputs not being restricted by
the AVDD + 0.3 V limit is that the power supply sequencing issues
are avoided. If any of these inputs are applied before AVDD, then
there is no risk of latch-up as there is on the analog inputs if a
Figure 32. Internal Reference Circuit Block Diagram
Alternatively, an external reference can be applied to the
REFIN/VREFOUT pin of the AD7934-6. An external reference
signal greater than 0.3 V is applied prior to AVDD
.
V
input is selected by setting the REF bit in the internal control
register to 0. The external reference input range is 0.1 V to VDD
VDRIVE Input
.
The AD7934-6 also has a VDRIVE feature. VDRIVE controls the
voltage at which the parallel interface operates. VDRIVE allows the
ADC to easily interface to 3 V and 5 V processors. For example,
if the AD7934-6 is operated with an AVDD of 5 V, and the VDRIVE
pin is powered from a 3 V supply, the AD7934-6 has better
dynamic performance with an AVDD of 5 V while still being able
to interface to 3 V processors. Care should be taken to ensure
VDRIVE does not exceed AVDD by more than 0.3 V (see the
Absolute Maximum Ratings section).
It is important to ensure that when choosing the reference value,
the maximum analog input range (VIN MAX) is never greater than
VDD + 0.3 V, in order to comply with the maximum ratings of the
device. For example, if operating in differential mode and the
reference is sourced from VDD, then the 0 to 2 × VREF range cannot
be used. This is because the analog input signal range would now
extend to 2 × VDD, which would exceed maximum rating condi-
tions. In the pseudo differential modes, the user must ensure that
(VREF + VIN−) ≤ VDD when using the 0 to VREF range, or that (2 ×
VREF + VIN−) ≤ VDD when using the 2 × VREF range.
Rev. A | Page 20 of 28
AD7934-6
At the end of the conversion, BUSY goes low and can be used to
PARALLEL INTERFACE
activate an interrupt service routine. The
and
lines are
CS
RD
The AD7934-6 has a flexible, high speed, parallel interface. This
interface is 12-bits wide and is capable of operating in either
then activated in parallel to read the 12 bits of conversion data.
When power supplies are first applied to the device, a rising
word (W/ tied high) or byte (W/ tied low) mode. The
B
B
edge on
is necessary to put the track-and-hold into
CONVST
track. The acquisition time of 125 ns minimum must be allowed
before is brought low to initiate a conversion. The
signal is used to initiate conversions, and when
CONVST
operating in autoshutdown or autostandby mode, it is used to
initiate power up.
CONVST
ADC then goes into hold on the falling edge of
back into track on the 13th rising edge of CLKIN (see Figure 34).
When operating the device in autoshutdown or autostandby
mode, where the ADC powers down at the end of each
, and
CONVST
A falling edge on the
signal is used to initiate conver-
CONVST
sions, and it also puts the ADC track-and-hold into track. Once
the signal goes low, the BUSY signal goes high for the
CONVST
duration of the conversion. Between conversions,
conversion, a rising edge on the
signal is used to
CONVST
must
CONVST
power up the device.
be brought high for a minimum time of t1. This must occur after
the 14th falling edge of CLKIN; otherwise, the conversion is
aborted and the track-and-hold goes back into track.
B
t1
A
CONVST
tCONVERT
1
2
3
4
5
12
13
14
t2
CLKIN
BUSY
t20
t3
t9
INTERNAL
TRACK/HOLD
tAQUISITION
CS
RD
t10
t11
t14
t12
t13
THREE-STATE
tQUIET
DB0 TO DB11
DB0 TO DB11
DATA
THREE-STATE
WITH CS AND RD TIED LOW
OLD DATA
DATA
B
Figure 34. AD7934-6 Parallel Interface—Conversion and Read Cycle in Word Mode (W/ = 1)
Rev. A | Page 21 of 28
AD7934-6
Reading Data from the AD7934-6
The
and
signals are gated internally and level triggered
RD
CS
active low. In either word mode or byte mode,
and
can
RD
CS
With the W/ pin tied logic high, the AD7934-6 interface
B
be tied together as the timing specification t10 and t11 are 0 ns
minimum. This means the bus is constantly driven by the
AD7934-6.
operates in word mode. In this case, a single read operation
from the device accesses the conversion data-word on Pins DB0
to DB11. The DB8/HBEN pin assumes its DB8 function. With
the W/ pin tied to logic low, the AD7934-6 interface operates
in byte mode. In this case, the DB8/HBEN pin assumes its
HBEN function.
B
The data is placed onto the data bus a time, t13, after both
CS
and
go low. The
RD
rising edge can be used to latch data
RD
out of the device. After a time, t14, the data lines become three-
stated.
Conversion data from the AD7934-6 must be accessed in two
read operations with 8 bits of data provided on DB0 to DB7 for
each of the read operations. The HBEN pin determines whether
the read operation accesses the high byte or the low byte of the
12-bit word. For a low byte read, DB0 to DB7 provide the eight
LSBs of the 12-bit word. For a high byte read, DB0 to DB3
provide the 4 MSBs of the 12-bit word. DB4 and DB5 of the
high byte provide the channel ID. DB6 and DB7 are always 0.
Figure 34 shows the read cycle timing diagram for a 12-bit
transfer. When operated in word mode, the HBEN input does
not exist and only the first read operation is required to access
data from the device. When operated in byte mode, the two
read cycles shown in Figure 35 are required to access the full
data-word from the device.
Alternatively,
and
can be tied permanently low, and the
RD
CS
conversion data is valid and placed onto the data bus a time, t9,
before the falling edge of BUSY.
Note that if
is pulsed during the conversion time then this
RD
causes a degradation in linearity performance of approximately
0.25 LSB. Reading during conversion by way of tying and
CS
low does not cause any degradation.
RD
HBEN/DB8
t15
t16
t15
t16
CS
t10
t11
t17
t12
RD
t13
t14
DB0 TO DB7
LOW BYTE
HIGH BYTE
B
Figure 35. AD7934-6 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/ = 0)
Rev. A | Page 22 of 28
AD7934-6
When operated in byte mode, the two write cycles shown in
Writing Data to the AD7934-6
Figure 37 are required to write the full data-word to the
AD7934-6. In Figure 37, the first write transfers the lower 8 bits
of the data-word from DB0 to DB7, and the second write
transfers the upper 4 bits of the data-word.
With W/ tied logic high, a single write operation transfers the
B
full data-word on DB0 to DB11 to the control register on the
AD7934-6. The DB8/HBEN pin assumes its DB8 function. Data
written to the AD7934-6 should be provided on the DB0 to
DB11 inputs, with DB0 being the LSB of the data-word. With
When writing to the AD7934-6, the top 4 bits in the high byte
must be 0s.
W/ tied logic low, the AD7934-6 requires two write operations
B
to transfer a full 12-bit word. DB8/HBEN assumes its HBEN
function. Data written to the AD7934-6 should be provided on
the DB0 to DB7 inputs. HBEN determines whether the byte
written is high byte or low byte data. The low byte of the data-
word has DB0 being the LSB of the full data-word. For the high
byte write, HBEN should be high, and the data on the DB0
input should be data Bit 8 of the 12-bit word.
The data is latched into the device on the rising edge of
. The
WR
data needs to be set up a time, t7, before the
rising edge and
WR
held for a time, t8, after the
signals are gated internally.
rising edge. The
and
WR
WR
and
CS
can be tied together as
WR
CS
the timing specification for t4, and t5 is 0 ns minimum (assuming
and
have not already been tied together).
CS
RD
Figure 36 shows the write cycle timing diagram of the AD7934-6.
When operated in word mode, the HBEN input does not exist,
and only one write operation is required to write the word of
data to the device. Data should be provided on DB0 to DB11.
CS
t4
t5
WR
t6
t8
t7
DATA
DB0 TO DB11
B
Figure 36. AD7934-6 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/ = 1)
HBEN/DB8
t18
t19
t18
t19
CS
t4
t5
t17
t6
WR
t7
LOW BYTE
t8
DB0 TO DB7
HIGH BYTE
B
Figure 37. AD7934-6 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/ = 0)
Rev. A | Page 23 of 28
AD7934-6
Autostandby Mode (PM1 = 1; PM0 = 0)
POWER MODES OF OPERATION
In this mode, the AD7934-6 automatically enters standby mode
at the end of each conversion, shown as Point A in Figure 34.
When this mode is entered, all circuitry on the AD7934-6 is
powered down except for the reference and reference buffer.
The track-and-hold also goes into hold at this point and
remains in hold as long as the device is in standby. The part
The AD7934-6 has four different power modes of operation.
These modes are designed to provide flexible power manage-
ment options. Different options can be chosen to optimize
the power dissipation/throughput rate ratio for differing
applications. The mode of operation is selected by the power
management bits, PM1 and PM0, in the control register (see
Table 8). When power is first applied to the AD7934-6, an on-
chip, power-on reset circuit ensures that the default power-up
condition is normal mode.
remains in standby until the next rising edge of
CONVST
powers up the device. The power-up time required depends on
whether the internal or external reference is used. With an
external reference, the power-up time required is a minimum of
600 ns. When using the internal reference, the power-up time
required is a minimum of 7 µs. The user should ensure this
power-up time has elapsed before initiating another conversion
Note that, after power-on, the track-and-hold is in hold mode,
and the first rising edge of
places the track-and-hold
CONVST
into track mode.
as shown in Figure 38. This rising edge of
the track-and-hold back into track mode.
also places
CONVST
Normal Mode (PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate perform-
ance because the user does not have to allow for power-up times
associated with the AD7934-6. It remains fully powered up at all
times. At power-on reset, this mode is the default setting in the
control register.
Full Shutdown Mode (PM1 = 1; PM0 = 1)
When this mode is entered, all circuitry on the AD7934-6 is
powered down upon completion of the write operation, that is,
on rising edge of
. The track-and-hold enters hold mode at
WR
this point. The part retains the information in the control
register while the part is in shutdown. The AD7934-6 remains
in full shutdown mode, and the track-and-hold in hold mode,
until the power management bits (PM1 and PM0) in the control
register are changed. If a write to the control register occurs
while the part is in full shutdown mode, and the power
management bits are changed to PM0 = PM1 = 0 (normal
Autoshutdown Mode (PM1 = 0; PM0 = 1)
In this mode of operation, the AD7934-6 automatically enters
full shutdown at the end of each conversion, shown at Point A
in Figure 34 and Figure 38. In shutdown mode, all internal
circuitry on the device is powered down. The part retains
information in the control register during shutdown. The track-
and-hold also goes into hold at this point, and remains in hold
as long as the device is in shutdown. The AD7934-6 remains in
mode), the part begins to power up on the
rising edge, and
WR
the track-and-hold returns to track. To ensure the part is fully
powered up before a conversion is initiated, the power-up time
shutdown mode until the next rising edge of
(see
CONVST
Point B in Figure 34 and Figure 38). To keep the device in
shutdown for as long as possible, should idle low
of 10 ms minimum should be allowed before the
CONVST
CONVST
falling edge; otherwise, invalid data is read.
between conversions as shown in Figure 38. On this rising edge,
the part begins to power-up and the track-and-hold returns to
track mode. The power-up time required is 10 ms minimum
regardless of whether the user is operating with the internal or
external reference. The user should ensure that the power-up
time has elapsed before initiating a conversion.
Note that all power-up times quoted apply with a 470 nF
capacitor on the VREFIN pin.
tPOWER-UP
B
A
CONVST
1
14
1
14
CLKIN
BUSY
Figure 38. Autoshutdown/Autostandby Modes
Rev. A | Page 24 of 28
AD7934-6
POWER VS. THROUGHPUT RATE
7
6
5
4
3
2
1
0
A considerable advantage of powering the ADC down after a
conversion is that the part’s power consumption is significantly
reduced at lower throughput rates. When using the different
power modes, the AD7934-6 is only powered up for the
duration of the conversion. Therefore, the average power
consumption per cycle is significantly reduced. Figure 39 shows
a plot of the power vs. the throughput rate when operating in
autostandby mode for both VDD = 5 V and 3 V.
T
= 25°C
A
V
= 5V
DD
V
= 3V
DD
For example, if the device runs at a throughput rate of 10 kSPS,
then the overall cycle time would be 100 µs. If the maximum
CLKIN frequency of 10 MHz is used, the conversion time
accounts for only 1.315 µs of the overall cycle time while the
AD7938-6 stays in standby mode for the remainder of the cycle.
0
100
200
300
400
500
600
700
THROUGHPUT (kSPS)
Figure 40. Power vs. Throughput in Normal Mode Using Internal Reference
If an external reference is used, the power-up time reduces to
600 ns; therefore, the AD7934-6 remains in standby for a
greater time in every cycle. Additionally, the current
consumption when converting should be lower than the
specified maximum of 1.5 mA or 1.2 mA with VDD = 5 V or 3 V,
respectively.
MICROPROCESSOR INTERFACING
AD7934-6 to ADSP-21xx Interface
Figure 41 shows the AD7934-6 interfaced to the ADSP-21xx
series of DSPs as a memory-mapped device. A single wait state
could be necessary to interface the AD7934-6 to the ADSP-
21xx, depending on the clock speed of the DSP. The wait state
can be programmed via the data memory wait state control
register of the ADSP-21xx (see the ADSP-21xx family User’s
Manual for details). The following instruction reads from the
AD7934-6:
Figure 40 shows a plot of the power vs. the throughput rate
when operating in normal mode for both VDD = 5 V and 3 V.
Again, when using an external reference, the current
consumption when converting is lower than the specified
maximum. In both plots, the figures apply when using the
internal reference.
MR = DM (ADC)
2.0
where:
T
= 25°C
A
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
ADC is the address of the AD7934-6.
DSP/USER SYSTEM
V
= 5V
DD
CONVST
A0 TO A15
ADDRESS BUS
AD7934-61
ADSP-21xx1
DMS
ADDRESS
DECODER
CS
V
= 3V
DD
IRQ2
WR
BUSY
WR
RD
RD
DB0 TO DB11
0
20
40
60
80
100
120
D0 TO D23
DATA BUS
THROUGHPUT (kSPS)
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 39. Power vs. Throughput in Autostandby Mode
Using Internal Reference
Figure 41. Interfacing to the ADSP-21xx
Rev. A | Page 25 of 28
AD7934-6
DSP/USER SYSTEM
AD7934-6 to ADSP-21065L Interface
Figure 42 shows a typical interface between the AD7934-6 and
the ADSP-21065L SHARC processor. This interface is an
CONVST
A0 TO A15
ADDRESS BUS
ADDRESS
TMS32020/
AD7934-61
TMS320C25/
TMS320C501
example of one of three DMA handshake modes. The
MSx
control line is actually three memory select lines. Internal
ADDR25–24 are decoded into . These lines are then asserted
IS
EN
CS
DECODER
MS3-0
(DMA request 1) is used in this
READY
as chip selects. The
DMAR1
TMS320C25
ONLY
MSC
setup as the interrupt to signal the end of the conversion. The
rest of the interface is a standard handshaking operation.
STRB
WR
RD
R/W
DSP/USER SYSTEM
INT
X
BUSY
CONVST
ADDR TO ADDR
ADDRESS BUS
0
23
DMD0 TO DMD15
DB11 TO DB0
DATA BUS
1
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDRESS
LATCH
AD7934-61
MS
X
Figure 43. Interfacing to the TMS32020/C25/C5x
ADDRESS BUS
ADSP-21065L1
DMAR
AD7934-6 to 80C186 Interface
ADDRESS
DECODER
CS
Figure 44 shows the AD7934-6 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer can
occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other to
store data. After the AD7934-6 has finished a conversion, the
BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA READ
operation that also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request is serviced before the completion of the next conversion.
BUSY
RD
1
RD
WR
WR
DB0 TO DB11
D0 TO D31
DATA BUS
1
ADDITIONAL PINS REMOVED FOR CLARITY.
Figure 42. Interfacing to the ADSP-21065L
AD7934-6 to TMS32020, TMS320C25, and TMS320C5x
Interface
Parallel interfaces between the AD7934-6 and the TMS32020,
TMS320C25, and TMS320C5x family of DSPs are shown in
Figure 43. The memory-mapped address chosen for the
µP/USER SYSTEM
CONVST
AD0 TO AD15
A16 TO A19
ADDRESS/DATA BUS
AD7934-6 should be chosen to fall in the I/O memory space of
the DSPs. The parallel interface on the AD7934-6 is fast enough
to interface to the TMS32020 with no extra wait states. If high
speed glue logic devices, such as the 74AS, are used to drive the
ADDRESS
LATCH
AD7934-61
ALE
ADDRESS BUS
80C1861
DRQ1
ADDRESS
DECODER
CS
and the
lines when interfacing to the TMS320C25, no
RD
WR
wait states are necessary. However, if slower logic is used, data
accesses could be slowed sufficiently when reading from, and
writing to, the part to require the insertion of one wait state.
Extra wait states are necessary when using the TMS320C5x at
their fastest clock speeds (see the TMS320C5x User’s Guide for
details).
Q
R
S
BUSY
RD
RD
WR
WR
DATA BUS
DB0 TO DB11
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 44. Interfacing to the 80C186
Data is read from the ADC using the following instruction:
IN D, ADC
where:
D is the data memory address.
ADC is the AD7934-6 address.
Rev. A | Page 26 of 28
AD7934-6
APPLICATION HINTS
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to GND. To achieve the best from these
decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 µF capacitors should have low effective series resistance
(ESR) and effective series inductance (ESI), such as the
common ceramic types or surface-mount types, which provide
a low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
GROUNDING AND LAYOUT
The printed circuit board that houses the AD7934-6 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. Generally, a
minimum etch technique is best for ground planes since it gives
the best shielding. Digital and analog ground planes should be
joined in only one place, and the connection should be a star
ground point established as close to the ground pins on the
AD7934-6 as possible. Avoid running digital lines under the
device as this couples noise onto the die. The analog ground
plane should be allowed to run under the AD7934-6 to avoid
noise coupling. The power supply lines to the AD7934-6 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line.
EVALUATING THE AD7934-6 PERFORMANCE
The recommended layout for the AD7934-6 is outlined in the
evaluation board documentation. The evaluation board package
includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from the
PC via the evaluation board controller. The evaluation board
controller can be used in conjunction with the AD7934-6
evaluation board, as well as with many other ADI evaluation
boards ending in the CB designator, to demonstrate/evaluate
the ac and dc performance of the AD7934-6.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog
inputs. Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best but is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to ground planes,
while signals are placed on the solder side.
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7934-6.
The software and documentation are on the CD that ships with
the evaluation board.
Rev. A | Page 27 of 28
AD7934-6
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 45. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7934BRU-6
AD7934BRU-6REEL7
AD7934BRUZ-62
AD7934BRUZ-6REEL72
EVAL-AD7934-6CB3
EVAL-CONTROL BRD24
Temperature Range
Linearity Error (LSB)1
Package Descriptions
Package Option
RU-28
RU-28
RU-28
RU-28
−40ꢁC to +85ꢁC
−40ꢁC to +85ꢁC
−40ꢁC to +85ꢁC
−40ꢁC to +85ꢁC
1
1
1
1
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
Evaluation Board
Controller Board
1 Linearity error here refers to integral linearity error.
2 Z = Pb-free part.
3 This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.
4 The Evaluation Board Controller is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB
designators. The following needs to be ordered to obtain a complete evaluation kit: the ADC Evaluation Board (e.g. EVAL-AD7934CB), the EVAL-CONTROL BRD2, and a
12 V ac transformer. See the relevant evaluation board technical note for more details.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04752-0-10/05(A)
Rev. A | Page 28 of 28
相关型号：
AD7934BRU
4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, MO-153-AE, TSSOP-28
ROCHESTER
AD7934BRU-REEL
4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, MO-153-AE, TSSOP-28
ROCHESTER
AD7934BRUZ
4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28, LEAD FREE, MO-153-AE, TSSOP-28
ROCHESTER
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