AD7868BNZ [ROCHESTER]
SPECIALTY ANALOG CIRCUIT, PDIP24, 0.300 INCH, PLASTIC, DIP-24;
| 型号： | AD7868BNZ |
| 厂家： | 
Rochester Electronics |
| 描述： | SPECIALTY ANALOG CIRCUIT, PDIP24, 0.300 INCH, PLASTIC, DIP-24 光电二极管 |
| 文件： | 总17页 (文件大小：1019K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
a
Complete, 12-Bit Analog I/O System
AD7868
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Com plete 12-Bit I/ O System , Com prising:
12-Bit ADC w ith Track/ Hold Am plifier
83 kHz Throughout Rate
72 dB SNR
12-Bit DAC w ith Output Am plifier
3 s Settling Tim e
V
DD
RI DAC
R
R
72 dB SNR
V
OUT
12-BIT
DAC
On-Chip Voltage Reference
Operates from ؎5 V Supplies
Low Pow er – 130 m W typ
Sm all 0.3" Wide DIP
LDAC
TFS
TCLK
DT
DAC 3V
REFERENCE
RO DAC
RO ADC
DAC SERIAL
INTERFACE
ADC 3V
REFERENCE
CONTROL
APPLICATIONS
RFS
RCLK
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modem s
DSP Servo Control
ADC SERIAL
INTERFACE
DR
R
R
CLK
CLOCK
12-BIT
ADC
V
IN
CONVST
TRACK/HOLD
AGND
AD7868
V
DGND
GENERAL D ESCRIP TIO N
SS
T he AD7868 is a complete 12-bit I/O system containing a DAC
and an ADC . T he ADC is a successive approximation type
with a track-and-hold amplifier having a combined throughput
rate of 83 kHz. T he DAC has an output buffer amplifier with a
settling time of 3 µs to 12 bits. T emperature compensated 3 V
buried Zener references provide precision references for the
DAC and ADC.
P RO D UCT H IGH LIGH TS
1. Complete 12-Bit I/O System.
T he AD7868 contains a 12-bit ADC with a track-and-hold
amplifier and a 12-bit DAC with output amplifier. Also
included are separate on-chip voltage references for the DAC
and the ADC.
Interfacing to both the DAC and ADC is serial, minimizing pin
count and giving a small 24-pin package size. Standard control
signals allow serial interfacing to most DSP machines. Asyn-
chronous ADC conversion control and DAC updating is made
possible with the CONVST and LDAC logic inputs.
2. Dynamic Specifications for DSP Users.
In addition to traditional dc specifications, the AD7868 is
specified for ac parameters including signal-to-noise ratio
and harmonic distortion. T hese parameters along with im-
portant timing parameters are tested on every device.
T he AD7868 operates from ±5 V power supplies, the analog in-
put/output range of the ADC/DAC is ±3 V. T he part is fully
specified for dynamic parameters such as signal-to-noise ratio
and harmonic distortion as well as traditional dc specifications.
3. Small Package.
T he AD7868 is available in a 24-pin DIP and a 28-pin SOIC
package.
T he part is available in a 24-pin, 0.3" wide, plastic or hermetic
dual-in-line package (DIP) and in a 28-pin, plastic SOIC
package.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD7868–SPECIFICATIONS
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = 0 V, fCLK = 2.0 MHz external. All specifications TMIN to T
MAX-
DD
SS
unless otherwise noted.)
ADC SECTION
A
B
T
P aram eter
Version1 Version1 Version1 Units
Test Conditions/Com m ents
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio3, 4 (SNR) @ +25°C
T MIN to T MAX
70
70
–78
72
71
–78
70
70
–76
dB min
dB min
dB max
VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
T ypically 71.5 dB for 0 < VIN < 41.5 kHz
VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
T ypically 71.5 dB for 0 < VIN < 41.5 kHz
VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
T ypically 71.5 dB for 0 < VIN < 41.5 kHz
T otal Harmonic Distortion (T HD)
Peak Harmonic or Spurious Noise
–78
–78
–76
dB max
Intermodulation Distortion (IMD)
Second Order T erms
T hird Order T erms
–78
–80
2
–78
–80
2
–76
–78
2
dB max
dB max
µs max
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
T rack/Hold Acquisition T ime
DC ACCURACY
Resolution
12
12
12
Bits
Minimum Resolution
Integral Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
Positive Gain Error5
Negative Gain Error5
12
±12
12
±12
±1
±0.9
±5
±5
12
±12
±1
±0.9
±5
±5
Bits
No Missing Codes Are Guaranteed
LSB typ
LSB max
LSB max
LSB max
LSB max
LSB max
±0.9
±5
±5
±5
±5
±5
ANALOG INPUT
Input Voltage Range
Input Current
±3
±1
±3
±1
±3
±1
Volts
mA max
REFERENCE OUT PUT6
RO ADC @ +25°C
2.99/3.01 2.99/3.01 2.99/3.01 V min/V max
RO ADC T C
RO ADC T C
Reference Load Sensitivity (∆RO ADC vs. ∆I)
±25
±25
±40
–1.5
±25
±50
–1.5
ppm/°C typ
ppm/°C max
mV max
–1.5
Reference Load Current Change (0 µA–500 µA),
Reference Load Should Not Be Changed
During Conversion
LOGIC INPUTS (CONVST, CLK, CONTROL)
Input High Voltage, VINH
Input Low Voltage, VINL
2.4
0.8
±10
±10
10
2.4
0.8
±10
±10
10
2.4
0.8
±10
±10
10
V min
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VIN = 0 V to VDD
VIN = VSS to DGND
V max
µA max
µA max
pF max
Input Current, IIN
Input Current7 (CONT ROL Input Only)
8
Input Capacitance, CIN
LOGIC OUT PUT S
DR, RFS Outputs
Output Low Voltage, VOL
RCLK Output
Output Low Voltage, VOL
DR, RFS, RCLK Outputs
Floating-State Leakage Current
Floating-State Output Capacitance8
0.4
0.4
0.4
0.4
0.4
0.4
V max
V max
ISINK = 1.6 mA, Pull-Up Resistor = 4.7 kΩ
ISINK = 2.6 mA, Pull-Up Resistor = 2 kΩ
±10
15
±10
15
±10
15
µA max
pF max
CONVERSION T IME
External Clock
Internal Clock
10
10
10
10
10
10
µs max
µs max
T he Internal Clock Has a Nominal Value of 2.0 MHz
POWER REQUIREMENT S
For Both DAC and ADC
VDD
VSS
IDD
ISS
+5
–5
22
12
+5
–5
22
12
+5
–5
25
13
V nom
V nom
mA max
mA max
±5% for Specified Performance
±5% for Specified Performance
Cumulative Current from the T wo VDD Pins
Cumulative Current from the T wo VSS Pins
T otal Power Dissipation
170
170
190
mW max
T ypically 130 mW
NOT ES
1T emperature ranges are as follows: A/B Versions, –40°C to +85°C; T Version, –55°C to +125°C.
2VIN = ±3 V
3SNR calculation includes distortion and noise components.
4SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.
5Measured with respect to internal reference.
6For capacitive loads greater than 50 pF a series resistor is required (see INT ERNAL REFERENCE section).
7T ying the CONT ROL input to VDD places the device in a factory test mode where normal operation is not exhibited.
8Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. B
AD7868
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = 0 V, RI DAC = +3 V and decoupled as shown in Figure 2, V
OUT
DD
SS
DAC SECTION
Load to AGND; R = 2 kΩ, C = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
L
L
A
B
T
P aram eter
Version1 Version1 Version1
Units
Test Conditions/Com m ents
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio3 (SNR) @ +25°C
T MIN to T MAX
70
70
–78
72
71
–78
70
70
–76
dB min
dB min
dB max
VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz
T ypically 71.5 dB at +25°C for 0 < VOUT < 20 kHz4
VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz
T otal Harmonic Distortion (T HD)
T ypically –84 dB at +25°C for 0 < VOUT < 20 kHz4
VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz
Peak Harmonic or Spurious Noise
–78
–78
–76
dB max
T ypically –84 dB at +25°C for 0 < VOUT < 20 kHz4
DC ACCURACY
Resolution
12
12
12
Bits
Integral Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
±1/2
±1/2
±1
±0.9
±5
±5
±5
±1/2
±1
±0.9
±5
±5
±5
LSB typ
LSB max
LSB max
LSB max
LSB max
LSB max
±0.9
±5
±5
Guaranteed Monotonic
Positive Full-Scale Error5
Negative Full-Scale Error5
±5
REFERENCE OUT PUT6
RO ADC @ +25°C
RO ADC T C
RO ADC T C
Reference Load Change (∆RO DAC vs. ∆I)
2.99/3.01 2.99/3.01 2.99/3.01
V min/V max
ppm/°C typ
ppm/°C max
mV max
±25
±25
±40
–1.5
±25
±50
–1.5
–1.5
Reference Load Current Change (0–500 µA)
REFERENCE INPUT
RI DAC Input Range
Input Current
2.85/3.15 2.85/3.15 2.85/3.15
V min/V max 3 V ± 5%
µA max
1
1
1
LOGIC INPUT S (LDAC, TFS, T CLK, DT )
Input High Voltage, VINH
Input Low Voltage, VINL
2.4
0.8
±10
10
2.4
0.8
±10
10
2.4
0.8
±10
10
V min
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VIN = 0 V to VDD
V max
µA max
pF max
Input Current, IIN
Input Capacitance, CIN
7
ANALOG INPUT
Output Voltage Range
dc Output Impedance
Short-Circuit Current
±3
0.3
20
±3
0.3
20
±3
0.3
20
V nom
Ω typ
mA typ
AC CHARACT ERIST ICS7
Voltage Output Settling-T ime
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Settling T ime to Within ±1/2 LSB of Final Value
T ypically 2 µs
T ypically 2.5 µs
3
3
10
2
100
3
3
10
2
100
3
3
10
2
100
µs max
µs max
nV secs typ
nV secs typ
dB typ
DAC Code Change All 1s to All 0s
VIN to VOUT Isolation
VIN = ±3 V, 41.5 kHz Sine Wave
POWER REQUIREMENT S
As per ADC Section
NOT ES
1T emperature ranges are as follows: A/B Versions, –40°C to +85°C; T Version, –55°C to +125°C.
2VOUT (pk–pk) = ±3 V.
3SNR calculation includes distortion and noise components.
4Using external sample and hold.
O RD ERING GUID E
Relative
5Measured with respect to RI DAC and includes bipolar offset error.
6For capacitive loads greater than 50 pF a series resistor is required
(see INT ERNAL REFERENCE section).
Tem perature
Range
Accuracy P ackage
(LSB)
7Sample tested @ +25°C to ensure compliance.
Model
SNR
O ption*
Specifications subject to change without notice.
AD7868AN
–40°C to +85°C 70 dB
–40°C to +85°C 70 dB
–40°C to +85°C 72 dB
–40°C to +85°C 72 dB
–40°C to +85°C 70 dB
–40°C to +85°C 72 dB
±1/2 typ
±1/2 typ
±1 max
±1 max
±1/2 typ
±1 max
N-24
Q-24
N-24
Q-24
R-28
R-28
AD7868AQ
AD7868BN
AD7868BQ
AD7868AR
AD7868BR
*N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline IC).
REV. B
–3–
AD7868
TIMING CHARACTERISTICS
1, 2
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = 0 V)
DD
SS
Lim it at TMIN, TMAX
(A, B Versions)
Lim it at TMIN, TMAX
(T Version)
P aram eter
Units
Conditions/Com m ents
ADC T IMING
t1
t2
t3
t4
50
440
100
20
100
155
4
100
50
440
100
20
100
155
4
100
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns typ
CONVST Pulse Width
3
RCLK Cycle T ime, Internal Clock
RFS to RCLK Falling Edge Setup T ime
RCLK Rising Edge to RFS
4
t5
RCLK to Valid Data Delay, CL = 35 pF
Bus Relinquish T ime after RCLK
t6
5
t13
2 RCLK +200 to
3 RCLK + 200
2 RCLK +200 to
3 RCLK + 200
CONVST to RFS Delay
DAC T IMING
t7
t8
t9
t10
t11
t12
50
75
150
30
75
40
50
ns min
ns min
ns min
ns min
ns min
ns min
TFS to T CLK Falling Edge
T CLK Falling Edge to TFS
T CLK Cycle T ime
Data Valid to T CLK Setup T ime
Data Valid to T CLK Hold T ime
LDAC Pulse Width
100
200
40
100
40
6
NOT ES
1T iming specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
voltage level of 1.6 V.
2Serial timing is measured with a 4.7 kΩ pull-up resistor on DR and RFS and a 2 kΩ pull-up resistor on RCLK . T he capacitance on all three output is 35 pF.
3When using internal clock, RCLK mark/space ratio (measured from a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space ratio =
external clock mark/space ratio.
4DR will drive higher capacitance loads but this will add to t 5 since it increases the external RC time constant (4.7 kΩ/CL) and hence the time to reach 2.4 V.
5T ime 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.
6T CLK mark/space ratio is 40/60 to 60/40.
ABSO LUTE MAXIMUM RATINGS*
P IN CO NFIGURATIO NS
(T A = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
D IP
SO IC
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD
VIN to AGND . . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V
RO ADC to AGND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
RO DAC to AGND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
RI DAC to AGND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Inputs to AGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to AGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating T emperature Range
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
T Version . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
1
CONTROL
28
27
1
2
24
23
22
21
CONVST
CLK
CONTROL
VDD
CONVST
CLK
2
V
DD
V
3
4
5
26
25
24
23
SS
RFS
VSS
VIN
3
RFS
NC
NC
4
RCLK
DR
V
RCLK
IN
5
20 RO ADC
RO ADC
DR
6
7
6
19
DGND
VDD
AD7868
TOP VIEW
(Not to Scale)
AGND
AD7868
TOP VIEW
22
21
DGND
AGND
DGND
18
7
NC
(Not to Scale)
V
8
9
DD
17 DGND
16 TCLK
8
AGND
VOUT
VSS
TCLK
20
AGND
9
V
10
19
18
17
16
OUT
NC
NC
DT
15
10
11
12
DT
11
12
NC
RO DAC
RI DAC
14
TFS
V
SS
13
LDAC
RO DAC 13
TFS
14
15
RI DAC
LDAC
NC = NO CONNECT
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
NC = NO CONNECT
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7868 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–4–
AD7868
P IN FUNCTIO N D ESCRIP TIO N
D IP P in
Num ber
Mnem onic
Function
POWER SUPPLY
7 & 23
10 & 22
8 & 19
6 &17
VDD
Positive Power Supply, 5 V ± 5%. Both VDD pins must be tied together.
Negative Power Supply, –5 V ± 5%. Both VSS pins must be tied together.
Analog Ground. Both AGND pins must be tied together.
VSS
AGND
DGND
Digital Ground. Both DGND pins must be tied together.
ANALOG SIGNAL AND REFERENCE
21
VIN
ADC Analog Input. T he ADC input range is ±3 V.
9
VOUT
Analog Output Voltage from DAC. T his output comes from a buffer amplifier. T he range is
bipolar, ±3 V with RI DAC = +3 V.
20
11
12
RO ADC
RO DAC
RI DAC
Voltage Reference Output. T he internal ADC 3 V reference is provided at this pin. T his output may be
used as a reference for the DAC by connecting it to the RI DAC input. T he external load capability of
this reference is 500 µA.
DAC Voltage Reference Output. T his is one of two internal voltage references. T o operate the DAC
with this internal reference, RO DAC should be connected to RI DAC. T he external load capability of
the reference is 500 µA.
DAC Voltage Reference Input. T he voltage reference for the DAC must be applied to this pin. It is
internally buffered before being applied to the DAC. T he nominal reference voltage for correct
operation of the AD7868 is 3 V.
ADC INT ERFACE AND CONT ROL
2
3
4
CLK
Clock Input. An external T T L-compatible clock may be applied to this input. Alternatively, tying pin to
VSS enables the internal laser-trimmed oscillator.
RFS
Receive Frame Synchronization, Logic Output. T his is an active low open-drain output which provides
a framing pulse for serial data. An external 4.7 kΩ pull-up resistor is required on RFS.
RCLK
Receive Clock, Logic Output. RCLK is the gated serial clock output which is derived from the internal
or external ADC clock. If the CONT ROL input is at VSS the clock runs continuously. With the
CONT ROL input at DGND the RCLK output is gated off (three-stated) after serial transmission is
complete. RCLK is an open-drain output and requires an external 2 kΩ pull-up resistor.
5
DR
Receive Data, Logic Output. T his is an open-drain data output used in conjunction with RFS and
RCLK to transmit data from the ADC. Serial data is valid on the falling edge of RCLK when RFS is
low. An external 4.7 kΩ resistor is required on the DR output.
1
CONVST
Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into
the hold mode and starts an ADC conversion. T his input in asynchronous to the CLK input.
24
CONT ROL
Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the
RCLK is continuous. Note, tying this pin to VDD places the part in a factory test mode where normal
operation is not exhibited.
DAC INT ERFACE AND CONT ROL
14
TFS
T ransmit Frame Synchronization, Logic Input. T his is a frame or synchronization signal for the DAC
with serial data expected after the falling edge of this signal.
15
DT
T ransmit Data, Logic Input. T his is the data input which is used in conjunction with TFS and T CLK
to transfer serial data to the input latch.
16
13
T CLK
T ransmit Clock, Logic Input. Serial data bits are latched on the falling edge of T CLK when TFS is low.
LDAC
Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the
falling edge of this signal.
No Connect.
18
NC
REV. B
–5–
AD7868
CO NVERTER D ETAILS
T he operation of the track/hold amplifier is essentially transpar-
ent to the user. T he track/hold amplifier goes from its track
mode to its hold mode at the start of conversion on the rising
edge of CONVST.
T he AD7868 is a complete 12-bit I/O port, the only external
components required for normal operation are pull-up resistors
for the ADC data outputs and power supply decoupling capaci-
tors. It is comprised of a 12-bit successive approximation ADC
with a track/hold amplifier, a 12-bit DAC with a buffered output
and two 3 V buried Zener references, a clock oscillator and con-
trol logic.
INTERNAL REFERENCES
T he AD7868 has two on-chip temperature compensated buried
Zener references which are factory trimmed to 3 V ± 10 mV.
One reference provides the appropriate biasing for the ADC,
while the other is available as a reference of the DAC. Both ref-
erence outputs are available (labeled RO DAC and RO ADC)
and are capable of providing up to 500 µA to an external load.
AD C CLO CK
T he AD7868 has an internal clock oscillator which can be used
for the ADC conversion procedure. T he oscillator is enabled by
tying the CLK input to VSS. T he oscillator in laser trimmed at
the factory to give a conversion time of between 8.5 and 10 µs.
T he mark/space ratio can vary from 40/60 to 60/40. Alterna-
tively, an external T T L compatible clock may be applied to this
input. T he allowable mark/space ratio of an external clock is
40/60 to 60/40. RCLK is a clock output, used for the serial in-
terface. T his output is derived directly from the ADC clock
source and can be switched off at the end of conversion with the
CONT ROL input.
T he DAC input reference (RI DAC) can be stored externally or
connected to any of the two on-chip references. Applications
requiring good full-scale error matching between the DAC and
the ADC should use the ADC reference as shown in Figure 4.
T he maximum recommended capacitance on either of the refer-
ence output pins for normal operation is 50 pF. If either of the
reference outputs is required to drive a capacitive load greater
than 50 pF, then a 200 Ω resistor must be placed in series with
the capacitive load. T he addition of decoupling capacitors,
10 µF in parallel with 0.1 µF, as shown in Figure 2, improves
noise performance. T he improvement in noise performance can
be seen from the graph in Figure 3. Note, this applies for the
DAC output only; reference decoupling components do not af-
fect ADC performance. So, a typical application will have just
the DAC reference source decoupled with the other one open
circuited.
AD C CO NVERSIO N TIMING
T he conversion time for both external clock and continuous in-
ternal clock can vary from 19 to 20 rising clock edges depending
on the conversion start to ADC clock synchronization. If a con-
version is initiated within 30 ns prior to a rising edge of the ADC
clock, the conversion time will consist of 20 rising clock edges,
i.e., 9.5 µs conversion time. For noncontinuous internal clock,
the conversion time is always 19 rising clock edges.
200Ω
RO DAC
or
RO ADC*
EXT LOAD
AD C TRACK-AND -H O LD AMP LIFIER
GREATER THAN 50pF
T he track-and-hold amplifier on the analog input of the AD7868
allows the ADC to accurately convert an input sine wave of 6 V
peak–peak amplitude to 12-bit accuracy. T he input impedance is
typically 9 kΩ, an equivalent circuit is shown in Figure 1. T he
input bandwidth of the track/hold amplifier is much greater than
the Nyquist rate of the ADC, even when the ADC is operated at
its maximum throughput rate. T he 0.1 dB cutoff frequency oc-
curs typically at 500 kHz. T he track/hold amplifier acquires an
input signal to 12-bit accuracy in less than 2 µs.
0.1µF
10µF
RI DAC
*RO DAC/RO ADC CAN BE LEFT
OPEN CIRCUIT IF NOT USED
Figure 2. Reference Decoupling Circuitry
D AC O UTP UT AMP LIFIER
T he output from the voltage-mode DAC is buffered by a nonin-
verting amplifier. T he buffer amplifier is capable of developing
±3 V across 2 kΩ and 100 pF load to ground and can produce
6 V peak-to-peak sine wave signals to a frequency of 20 kHz.
T he output is updated on the falling edge of the LDAC input.
T he output voltage settling time, to within 1/2 LSB of its final
value, is typically less than 2 µs.
TRACK/HOLD
AMPLIFIER
4.5kΩ
TO INTERNAL
COMPARATOR
VIN
AD7868*
4.5kΩ
TO INTERNAL
3V REFERENCE
T he small signal (200 mV p-p) bandwidth of the output buffer
amplifier is typically 1 MHz. T he output noise from the ampli-
fier is low with a figure of 30 nV/√Hz at a frequency of 1 kHz.
T he broadband noise from the amplifier exhibits a typical peak-
to-peak figure of 150 µV for a 1 MHz output bandwidth. Fig-
ure 3 shows a typical plot of noise spectral density versus fre-
quency for the output buffer amplifier and for either of the
on-chip references.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 1. ADC Analog Input
T he overall throughput rate is equal to the conversion time plus
the track/hold amplifier acquisition time. For a 2.0 MHz input
clock the throughput time is 12 µs max.
REV. B
–6–
AD7868
the input signal is within the full dynamic range of the ADC. For
applications which require that the input signal range match the
full analog input dynamic range of the ADC, offset and full-scale
errors have to be adjusted to zero.
500
TA = +25°C
VDD = +5V
VSS = –5V
200
100
REF OUT
AD C AD JUSTMENT
Figure 6 has signal conditioning at the input and output of the
AD7868 for trimming the end points of the transfer functions of
both the ADC and the DAC. Offset error must be adjusted be-
fore full-scale error. For the ADC, this is achieved by trimming
the offset of A1 while the input voltage, V1, is 1/2 LSB below
ground. T he trim procedure is as follows: apply a voltage of
–0.73 mV (–1/2 LSB) at V1 in Figure 6 and adjust the offset
voltage of A1 until the ADC output code flickers between 1111
1111 1111 (FFF HEX) and 0000 0000 0000 (000 HEX).
50
DAC OUTPUT
WITH ALL 0s
LOADED
REF OUT DECOUPLED
AS SHOWN IN
FIGURE 2
20
10
50
100
200
10k
100k
1k
2k
20k
FREQUENCY – Hz
Figure 3. Noise Spectral Density vs. Frequency
ADC gain error can be adjusted at either the first code transi-
tion (ADC negative full scale) or the last code transition (ADC
positive full scale). T he trim procedures for both cases are as
follows (see Figure 6).
INP UT/O UTP UT TRANSFER FUNCTIO NS
A bipolar circuit for the AD7868 is shown in Figure 4. T he ana-
log input/output voltage range of the AD7868 is ±3 V. T he de-
signed code transitions for the ADC occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB, 5/2 LSB
. . . FS – 3/2 LSBs). T he input/output code is 2s complement
binary with 1 LSB = FS/4096 = 1.46 mV. T he ideal transfer
function is shown in Figure 5.
AD C P ositive Full-Scale Adjustm ent
Apply a voltage of 2.9978 V (FS/2 – 3/2 LSBs) at V1. Adjust R2
until the ADC output code flickers between 0111 1111 1110
(7FE HEX) and 0111 1111 1111 (7FF HEX).
AD C Negative Full-Scale Adjustm ent
Apply a voltage of –2.9993 V (–FS/2 + 1/2 LSB) at V1 and
adjust R2 until the ADC output code flickers between 1000
0000 0000 (800 HEX) and 1000 0000 0001 (801 HEX).
AD7868*
ANALOG OUTPUT
RANGE = ±3V
V
IN
V
OUT
ANALOG INPUT
RANGE = ±3V
RI DAC
D AC AD JUSTMENT
R1
200
Op amp A2 is included in Figure 6 for the DAC transfer func-
tion adjustment. Again offset must be adjusted before full scale.
T o adjust offset: load the DAC with 0000 0000 0000 (000
HEX) and trim the offset of A2 to 0 V. As with the ADC adjust-
ment, gain error can be adjusted at either the first code transi-
tion (DAC negative full scale) or the last code transition (DAC
positive full scale). T he trim procedures for both cases are as
follows:
RO ADC
C2
0.1µF
C1
10µF
AGND
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 4. AD7868 Basic Bipolar Operation Using RO ADC
as a Reference Input for the DAC
D AC P ositive Full-Scale Adjustm ent
OUTPUT
CODE
Load the DAC with 0111 1111 1111 (7FF HEX) and adjust R7
until the op amp output voltage is equal to 2.9985 V, (FS/2 –
1 LSB).
011...111
011...110
D AC Negative Full-Scale Adjustm ent
Load the DAC with 1000 0000 0000 (800 HEX) and adjust R7
until the op amp output voltage is equal to 3.0 V (–FS/2).
000...010
-FS
000...001
2
V1
000...000
+
FS
INPUT VOLTAGE
RANGE = ±3V
-1LSB
111...111
2
111...110
FS = 6V
FS
4096
R1
10k
1LSB =
100...001
100...000
R2
500
A1
VIN
VOUT
R3
10k
0V
R6
10k
R4
10k
INPUT VOLTAGE
AD7868*
R5
10k
V0
OUTPUT VOLTAGE
RANGE = ± 3V
Figure 5. AD7868 Input/Output Transfer Function
R7
500
A2
AGND
R8
10k
O FFSET AND FULL-SCALE AD JUSTMENT
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale errors do not cause problems as long as
R9
10k
R10
10k
*ADDITIONAL PINS
OMITTED FOR CLARITY
Figure 6. AD7868 with Input/Output Adjustm ent
REV. B
–7–
AD7868
TIMING AND CO NTRO L
serial clock which runs continuously. Both options are available
on the AD7868 ADC. With the CONTROL input at 0 V, RCLK
is noncontinuous and when it is at –5 V, RCLK is continuous.
Communication with the AD7868 is managed by 6 dedicated
pins. T hese consist of separate serial clocks, word framing or
strobe pulses and data signals for both receiving and transmit-
ting data. Conversion starts and DAC updating are controlled
by two digital inputs; CONVST and LDAC. T hese inputs can
be asserted independently of the microprocessor by an external
timer when precise sampling intervals are required. Alterna-
tively, the LDAC and CONVST can be driven from a decoded
address bus allowing the microprocessor control over conversion
start and DAC updating as well as data communication to the
AD7868.
D AC Tim ing
T he AD7868 DAC contains two latches, an input latch and a
DAC latch. Data must be loaded to the input latch under the
control of the T CLK, TFS and DT serial logic inputs. Data is
then transferred from the input latch to the DAC latch under
the control of the LDAC signal. Only the data in the DAC latch
determines the analog output of the AD7868.
Data is loaded to the input latch under control of T CLK, TFS
and DT . T he AD7868 DAC expects a 16-bit stream of serial
data on its DT input. Data must be valid on the falling edge of
T CLK. T he TFS input provides the frame synchronization sig-
nal which tells the AD7868 DAC that valid serial data will be
available for the next 16 falling edges of T CLK. Figure 8 shows
the timing diagram for the serial data format.
AD C Tim ing
Conversion control is provided by the CONVST input. A low to
high transition on CONVST input starts conversion and drives
the track/hold amplifier into its hold mode. Serial data then be-
comes available while conversion is in progress. T he correspond-
ing timing diagram is shown in Figure 7. T he word length is 16
bits; 4 leading zeros, followed by the 12-bit conversion result
starting with the MSB. T he data is synchronized to the serial
clock output (RCLK) and is framed by the serial strobe (RFS).
Data is clocked out on a low to high transition of the serial clock
and is valid on the falling edge of this clock while the RFS out-
put is low. RFS goes low at the start of conversion and the first
serial data bit (which is the first leading zero) is valid on the first
falling edge of RCLK. All the ADC serial lines are open-drain
outputs and require external pull-up resistors.
Although 16 bits of data are clocked into the input latch, only
12 bits are transferred into the DAC latch. T herefore, 4 bits in
the stream are don’t cares since their value does not affect the
DAC latch data. T he bit positions are 4 don’t cares followed by
the 12-bit DAC data starting with the MSB.
T he LDAC signal controls the transfer of data to the DAC
latch. Normally, data is loaded to the DAC latch on the falling
edge of LDAC. However, if LDAC is held low, then serial data
is loaded to the DAC latch on the sixteenth falling edge of
T CLK. If LDAC goes low during the loading of serial data to
the input latch, no DAC latch update takes place on the falling
edge of LDAC. If LDAC stays low until the serial transfer is
completed, then the update takes place on the sixteenth falling
edge of T CLK. If LDAC returns high before the serial data
transfer is completed, no DAC latch update takes place.
T he serial clock out is derived from the ADC master clock
source which may be internal or external. Normally, RCLK is
required during the serial transmission only. In these cases it can
be shut down (i.e., placed into high impedance) at the end of
conversion to allow multiple ADCs to share a common serial
bus. However, some serial systems (e.g., T MS32020) require a
CONVERSION TIME
t1
CONVST
t13
1
RFS
t3
t2
t4
2, 3
RCLK
t5
t6
1
DB11
DB10
DB9
DB1
DB0
DR
NOTES
1
EXTERNAL 4.7k
Ω
PULL-UP RESISTOR
2
3
EXTERNAL 2k
Ω PULL-UP RESISTOR
CONTINUOUS RCLK (DASHED LINE) WHEN THE CONTROL INPUT = –5V AND
NONCONTINUOUS WHEN THE CONTROL INPUT = 0V
Figure 7. ADC Control Tim ing Diagram
t
t
7
8
TFS
t
9
TCLK
DT
t
11
t
10
DON'T DON'T DON'T DON'T
CARE CARE CARE CARE
DB11 DB10
DB1
DB0
Figure 8. DAC Control Tim ing Diagram
–8–
REV. B
AD7868
AD 7868 D YNAMIC SP ECIFICATIO NS
Figure 10 shows a typical plot of effective number of bits versus
frequency for an AD7868BQ with a sampling frequency of
83 kHz. T he effective number of bits typically falls between 11.7
and 11.85 corresponding to SNR figures of 72.2 and 73.1 dB.
T he AD7868 is specified and 100% tested for dynamic perfor-
mance specifications as well as traditional dc specifications such
as integral and differential nonlinearity. T hese ac specifications
are required for signal processing applications such as speech
recognition, spectrum analysis, and high-speed modems. T hese
applications require information on the converter’s effect on the
spectral content of the input signal. Hence, the parameters for
which the AD7868 is specified include SNR, harmonic distor-
tion and peak harmonics. T hese terms are discussed in more de-
tail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC or DAC. T he signal is the rms magnitude of the funda-
mental. Noise is the rms sum of all the nonfundamental signals
up to half the sampling frequency (fs/2) excluding dc. SNR is
dependent upon the number of levels used in the quantization
process; the more levels, the smaller the quantization noise. T he
theoretical signal-to-noise ratio for a sine wave input is given by
SNR = (6.02N + 1.76) dB
(1)
where N is the number of bits. T hus for an ideal 12-bit con-
verter, SNR = 74 dB.
Figure 9. AD7868, ADC FFT Plot
12
Effective Num ber of Bits
T he formula given in Equation 1 relates the SNR to the number
of bits. Rewriting the formula, as in Equation 2, it is possible to
get a measure of performance expressed in effective number of
bits (N).
11.5
11
SNR –1.76
N =
(2)
6.02
T he effective number of bits for a device can be calculated di-
rectly from its measured SNR.
SAMPLE FREQUENCY = 83 kHz
10.5
T
= 25°C
A
H ar m onic D istor tion
Harmonic distortion is the ratio of the rms sum of harmonics to
the fundamental. For the AD7868, total harmonic distortion
(T HD) is defined as
10
0
41.5
INPUT FREQUENCY – kHz
2
2
2
2
2
Figure 10. Effective Num ber of Bits vs. Frequency for the
ADC
V2 +V3 +V4 +V5 +V6
THD = 20 log
V1
D AC Testing
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through to
the sixth harmonic. T he T HD is also derived from the FFT plot
of the ADC or DAC output spectrum.
A simplified diagram of the method used to test the dynamic
performance specifications of the DAC is outlined in Figure 11.
Data is loaded to the DAC under control of the microcontroller
and associated logic. T he output of the DAC is applied to a 9th
order low-pass filter whose cutoff frequency corresponds to the
Nyquist limit. T he output of the filter is in turn applied to a
16-bit accurate digitizer. T his digitizes the signal and the micro-
controller generates an FFT plot from which the dynamic per-
formance of the DAC can be evaluated.
AD C Testing
T he output spectrum from the ADC is evaluated by applying a
sine-wave signal of very low distortion to the VIN input which is
sampled at an 83 kHz sampling rate. A Fast Fourier T ransform
(FFT ) plot is generated from which the SNR data can be ob-
tained. Figure 9 shows a typical 2048 point FFT plot of the
AD7868BQ ADC with an input signal of 10 kHz and a sam-
pling frequency of 83 kHz. T he SNR obtained from this graph
is 73 dB. It should be noted that the harmonics are taken into
account when calculating the SNR.
REV. B
–9–
AD7868
quencies at an update rate of 83 kHz. T he plot of Figure 14 is
without a sample-and-hold on the DAC output while the plot of
Figure 15 is generated with a sample-and-hold on the output.
LOW-PASS
FILTER
AD7868
DAC
MICRO-
CONTROLLER
16-BIT
DIGITIZER
R2
2k2
C9
330pF
Figure 11. AD7868 DAC Dynam ic Perform ance Test Circuit
ADG201HS
R1
T he digitizer sampling is synchronized with the DAC update
rate to ease FFT calculations. T he digitizer samples the DAC
output after the output has settled to its new value. T herefore, if
the digitizer were to sample the output directly it would effec-
tively be sampling a dc value each time. As a result, the dynamic
performance of the DAC would not be measured correctly. Us-
ing the digitizer directly on the DAC output would give better
results than the actual performance of the DAC. Using a filter
between the DAC and the digitizer means that the digitizer
samples a continuously moving signal and the true dynamic per-
formance of the AD7868 DAC output is measured.
2k2
V
OUT
AD7868*
S1
D1
AD711
LDAC
IN1
1µs
ONE
SHOT
DELAY
Q
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. DAC Sam ple-and-Hold Circuit
80
Figure 12 shows a typical 2048 point Fast Fourier T ransform
plot for the AD7868 DAC with an update rate of 83 kHz and an
output frequency of 1 kHz. T he SNR obtained from the graph is
73 dBs.
70
60
50
40
30
20
10
0
T
= +25°C
A
0
1
2
3
4
5
FREQUENCY – kHz
Figure 14. DAC Perform ance vs. Frequency (No Sam ple-
and-Hold)
80
70
60
50
40
30
20
Figure 12. AD7868 DAC FFT Plot
Some applications will require improved performance versus fre-
quency from the AD7868 DAC. In these applications, a simple
sample-and-hold circuit such as that outlined in Figure 13 will
extend the very good performance of the DAC to 20 kHz. Other
applications will already have an inherent sample-and-hold
function following the AD7868 DAC output. An example of
this type of application is driving a switched-capacitor filter
where the updating of the DAC is synchronized with the
switched-capacitor filter. T his inherent sample-and-hold
function also extends the frequency range performance.
T
= +25°C
A
10
0
5
10
FREQUENCY – kHz
15
20
0
P er for m ance ver sus Fr equency
T he typical performance plots of Figures 14 and 15 show the
AD7868’s DAC performance over a wide range of input fre-
Figure 15. DAC Perform ance vs. Frequency (Sam ple-and-
Hold)
REV. B
–10–
AD7868
MICRO P RO CESSO R INTERFACING
DSP56000 internal serial control registers have to be configured
for a 16-bit data word with valid data on the first falling clock
edge. Conversion starts and DAC updating are controlled by an
external timer. Data transfers, which occur during ADC conver-
sions, are between the processor receive and transmit shift regis-
ters and the AD7868’s ADC and DAC. At the end of each
16-bit transfer the DSP56000 receives an internal interrupt indi-
cating the transmit register is empty and the receive register is
full.
Microprocessor interfacing to the AD7868 is via a serial bus that
uses standard protocol compatible with DSP machines. T he
communication interface consists of separate transmit (DAC)
and receive (ADC) sections whose operations can be either syn-
chronous or asynchronous with respect to each other. Each sec-
tion has a clock signal, a data signal and a frame or strobe pulse.
Synchronous operation means that data is transmitted from the
ADC and to the DAC at the same time. In this mode only one
interface clock is needed and this has to be the ADC clock out,
so RCLK must be connected to T CLK. For asynchronous op-
eration, DAC and ADC data transfers are independent of each
other, the ADC provides the receive clock (RCLK) while the
transmit clock (T CLK) may be provided by the processor or the
ADC or some other external clock source.
TIMER
CONVST
LDAC
CONTROL
Another option to be considered with serial interfacing is the use
of a gated clock. A gated clock means that the device that is
sending the data switches on the clock when data is ready to be
transmitted and three states the clock output when transmission
is complete. Only 16 clock pulses are transmitted with the first
data bit getting latched into the receiving device on the first fall-
ing clock edge. Ideally, there is no need for frame pulses, how-
ever, the AD7868 DAC frame input (TFS) has to be driven
high between data transmissions. T he easiest method is to use
RFS to drive TFS and use only synchronous interfacing. T his
avoids the use of interconnects between the processor and
AD7868 frame signals. Not all processors have a gated clock
facility, Figure 16 shows an example with the DSP56000.
+5V
AD7868*
4.7kΩ
2kΩ
4.7kΩ
DSP56000
RFS
SC0
TFS
SCK
SRD
RCLK
DR
DT
STD
TCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
T able I below shows the number of interconnect lines between
the processor and the AD7868 for the different interfacing op-
tions. T he AD7868 has the facility to use different clocks for
transmitting and receiving data. T his option, however, only ex-
ists on some processors and normally just one clock (ADC
clock) is used for all communication with the AD7868. For sim-
plicity, all the interface examples in this data sheet use synchro-
nous interfacing and use the ADC clock (RCLK) as an input for
the DAC clock (T CLK). For a better understanding of each of
these interfaces, consult the relevant processor data sheet.
Figure 16. AD7868—DSP56000 Interface
AD 7868—AD SP -2101/AD SP -2102 Inter face
An interface which is suitable for the ADSP-2101 or the ADSP-
2102 is shown in Figure 17. T he interface is configured for syn-
chronous, continuous clock operation. T he LDAC is tied low so
the DAC gets updated on the sixteenth falling clock after TFS
goes low. Alternatively LDAC may be driven from a timer as
shown in Figure 16. As with the previous interface the processor
receives an interrupt after reading or writing to the AD7868 and
updates its own internal registers in preparation for the next
data transfer.
Table I. Interconnect Lines for D ifferent Interfacing O ptions
TIMER
CONVST
No. of
Configuration Interconnects Signals
CONTROL
–
5V
Synchronous
4
RCLK, DR, DT and RFS
(T CLK = RCLK, TFS = RFS)
RCLK, DR, RFS, DT , TFS
(T CLK = RCLK or
ADSP-2101/
ADSP-2102
+
5V
AD7868*
Asynchronous* 5 or 6
4.7kΩ
2kΩ
4.7kΩ
RFS
RFS
µP serial CLK)
RCLK, DR and DT
RCLK
SCLK
DR
Synchronous
Gated Clock
3
DR
(T CLK = RCLK, TFS = RFS)
TFS
DT
TFS
TCLK
DT
*5 LINES OF INT ERCONNECT WHEN T CLK = RCLK
6 LINES OF INT ERCONNECT WHEN T CLK = µP SERIAL CLK
AD 7868—D SP 56000 Inter face
LDAC
Figure 16 shows a typical interface between the AD7868 and
DSP56000. T he interface arrangement is synchronous with a
gated clock requiring only three lines of interconnect. T he
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. AD7868—ADSP-2101/ADSP-2102 Interface
REV. B
–11–
AD7868
AD 7868—TMS32020/TMS320C25 Inter face
analog circuitry from digital noise. T he circuit layout of Figures
22 and 23 have both analog and digital ground planes which are
kept separated and only joined together at the AD7868 AGND
pins.
Figure 18 shows an interface which is suitable for the
T MS32020/T MS320C25 processors. T his interface is config-
ured for synchronous, continuous clock operation. Note, the
AD7868 will not interface correctly to these processors if the
AD7868 is configured for a noncontinuous clock. Conversion
starts and DAC updating are controlled by an external timer.
NO ISE
Keep the input signal leads to VIN and signal return leads from
AGND as short as possible to minimize input noise coupling. In
applications where this is not possible, use a shielded cable be-
tween the source and the ADC. Reduce the ground circuit im-
pedance as much as possible since any potential difference in
grounds between the signal source and the ADC appears as an
error voltage in series with the input signal.
TIMER
CONVST
LDAC
–
5V
CONTROL
TMS32020
TMS320C25
+
5V
AD7868*
INP UT/O UTP UT BO ARD
Figure 19 shows an analog I/O board based on the AD7868.
T he corresponding printed circuit board (PCB) layout and
silkscreen are shown in Figures 21 to 23.
4.7kΩ
2kΩ
4.7kΩ
FSR
RFS
RCLK
DR
CLKR
DR
T he analog input to the AD7868 is buffered with an AD711 op
amp. T here is a component grid provided near the analog input
on the PCB which may be used for an antialiasing filter for the
ADC or a reconstruction filter for the DAC or any other condi-
tioning circuitry. T o facilitate this option, there are two wire
links (labeled LK1 and LK2) required on the analog input and
output tracks.
TFS
TCLK
DT
FSX
CLKX
DX
*ADDITIONAL PINS OMITTED FOR CLARITY
T he board contains a SHA circuit which can be used on the
output of the AD7868 DAC to extend the very good perfor-
mance of the part over a wider frequency range. T he increased
performance from the SHA can be seen in Figures 14 and 15 of
this data sheet. A wire link (labeled LK3) connects the board
output to either the SHA output or directly to the AD7868
DAC output.
Figure 18. AD7868—TMS32020/TMS320C25 Interface
AP P LICATIO N H INTS
Good printed circuit board (PCB) layout is as important as the
circuit design itself in achieving high speed A/D performance.
T he AD7868’s comparator is required to make bit decisions on
an LSB size of 1.465 mV. T o achieve this, the designer has to
be conscious of noise both in the ADC itself and in the preced-
ing analog circuitry. Switching mode power supplies are not rec-
ommended as the switching spikes will feed through to the
comparator causing noisy code transitions. Other causes of con-
cern are ground loops and digital feedthrough from micropro-
cessors. T hese are factors which influence any ADC, and a
proper PCB layout which minimizes these effects is essential for
best performance.
T here are three LDAC link options on the board; LDAC can be
driven from an external source independent of CONVST,
LDAC can be tied to CONVST or LDAC can be tied to GND.
Choosing the latter option of tying LDAC to GND disables the
SHA operation, and places the SHA permanently in the track
mode.
Microprocessor connections to the board are made by a 9-way
D-type connector. T he pinout is shown in Figure 20. T he
ADC’s digital outputs are buffered with 74HC4050s. T hese
buffers provide a higher current output capability for high
capacitance loads or cables. Normally, these buffers are not
required as the AD7868 will be sitting on the same board as the
processor.
LAYO UT H INTS
Ensure that the layout for the printed circuit board has the digi-
tal and analog signal lines separated as much as possible. T ake
care not to run any digital track alongside an analog signal track.
Guard (screen) the analog input with AGND.
P O WER SUP P LY CO NNECTIO NS
Establish a single point analog ground (star ground) separate
from the logic system ground as close as possible to the AD7868
AGND pins. Connect all other grounds and the AD7868
DGND to this single analog ground point. Do not connect any
other digital grounds to this analog ground point.
T he PCB requires two analog power supplies and one 5 V digi-
tal supply. Connections to the analog supply are made directly
to the PCB as shown on the silkscreen in Figure 21. T he con-
nections are labeled V+ and V– and the range for both of these
supplies is 12 V to 15 V. Connections to the 5 V digital supply
are made through the D-type connector SKT 6. T he ±5 V ana-
log supply required by the AD7868 are generated from two volt-
age regulators on the V+ and V– supplies.
Low impedance analog and digital power supply common re-
turns are essential to low noise operation of the ADC, so make
the foil width for these tracks as wide as possible. T he use of
ground planes minimizes impedance paths and also guards the
REV. B
–12–
AD7868
5V
V+
IN
OUT
C1
10µF
C2
0.1µF
IC5
78L05
V+
C6
GND
C5
10µF
0.1µF
ANALOG INPUT
±3V RANGE
VDD
VDD
LK1
C
R7
200
A
B
AD711
+
RO ADC
IC2
SKT1
VIN
C24
0.1µF
C23
10µF
V–
A
B
COMPONENT
GRID
RI DAC
LK4
C7
10µF
C8
0.1µF
C
RO DAC
IC1
AD7868
–5V
A
B
LK5
CONTROL
C
COMPONENT
GRID
AGND
SKT6
9-WAY D-TYPE
CONNECTOR
B
LK2
C
AGND
SKT2
B
5V
R3
A
C
IC7 1/2
74HC4050
A
ANALOG OUTPUT
±3V RANGE
5V
DGND
DGND
R5
4.7kΩ
R4
2kΩ
LK3
+
V
4.7kΩ
DR
DR
C10
0.1µF
C9
10µF
RCLK
RFS
RCLK
IC4
ADG201HS
RFS
+
AD711
R1
IC3
2kΩ
LK9
VOUT
V–
LK8
TFS
TCLK
DT
C12
0.1µF
C11
10µF
TFS
TCLK
DT
C21
330pF
R2
2kΩ
DGND
CLK
5V
LDAC
CONVST
VSS
R6
15k
VCC
Q
VSS
REXT/C
EXT
C22
68pF
B
A
B
A
C
CEXT
V–
–5V
IN
OUT
5V
LK7
–5V
C4
0.1µF
C3
10µF
CLR
IC6
IC8 1/2
74HC221
79L05
C
A
B
GND
GND
LK6
SKT3
LDAC
SKT4
SKT5
EXT CLK
CONVST
Figure 19. Input/Output Circuit Based on the AD7868
WIRE LINK O P TIO NS
LK1, Analog Input Link
LK1 connects the analog input to a component grid or to a
buffer amplifier which drives the ADC input.
1
2
3
4
5
6
7
8
9
LK2, Analog O utput Link
LK2 connects the analog output to the component grid or to
either the SHA or DAC output (see LK3).
NC = NO CONNECT
LK3, SH A or D AC Select
T he analog output may be taken directly from the DAC or from
a SHA at the output of the DAC.
Figure 20. SKT6, D-Type Connector Pinout
REV. B
–13–
AD7868
LK4, D AC Refer ence Selection
CO MP O NENT LIST
T he DAC reference may be connected to either the ADC refer-
ence output (RO ADC) or to the DAC reference (RO DAC).
IC1
IC2, IC3
IC4,
IC5,
IC6,
AD7868
2X AD711
ADG201HS
MC78L05
MC79L05
74HC4050
74HC221
LK5, AD C Inter nal Clock Selection
T his link configures the ADC for continuous or noncontinuous
internal clock operation.
IC7,
IC8,
LK6, D AC Updating
C1, C3, C5, C7
C9, C11, C13, C15
C17, C19, C23
T he DAC, LDAC input may asserted independently of the
ADC CONVST signal or it may be tied to CONVST or it may
tied to GND.
10 µF Capacitor
0.1 µF Capacitor
C2, C4, C6, C8
C10, C12, C14, C16
C18, C20, C24
LK7, AD C Clock Sour ce
T his link provides the option for the ADC to use its own inter-
nal clock oscillator or an external T T L compatible clock.
C21
C22
330 pF Capacitor
68 pF Capacitor
R1, R2, R4
R3, R5
2 kΩ Resistor
4.7 kΩ Resistor
LK8 Fr am e Synchr onous O ption
LK8 provides the option of tying the ADC RFS output to the
DAC TFS input.
R6
R7
15 kΩ Resistor
200 Ω Resistor
LK9 Tr ansm it/Receive Clock O ption
LK9 provides the option to connect the ADC RCLK to the
DAC T CLK.
LK1, LK2, LK3,
LK4, LK5, LK6,
LK7, LK8
Shorting Plugs
LK9
SKT 1, SKT 2, SKT 3,
SKT 4, SKT 5
BNC Sockets
SKT 6
9-Contact D-T ype Connector
Figure 21. Silkscreen for the Circuit Diagram of Figure 19
REV. B
–14–
AD7868
Figure 22. Com ponent Side Layout for the Circuit Diagram of Figure 19
Figure 23. Solder Side Layout for the Circuit Diagram of Figure 19
REV. B
–15–
AD7868
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
24-P in P lastic (N-24)
24-P in Cer dip (Q -24)
28-P in P lastic SO IC (R-28)
REV. B
–16–
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