AD7869JN [ADI]
LC2MOS Complete, 14-Bit Analog I/O System; LC2MOS完成， 14位模拟I / O系统
| 型号： | AD7869JN |
| 厂家： | 
ADI |
| 描述： | LC2MOS Complete, 14-Bit Analog I/O System |
| 文件： | 总16页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
a
Complete, 14-Bit Analog I/O System
AD7869
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Com plete 14-Bit l/ O System , Com prising
14-Bit ADC w ith Track/ Hold Am plifier
83 kHz Throughput Rate
V
DD
RI DAC
14-Bit DAC w ith Output Am plifier
3.5 s Settling Tim e
R
R
On-Chip Voltage Reference
Operates from ؎5 V Supplies
Low Pow er—130 m W typ
Sm all 0.3" Wide DIP
V
OUT
14 - BIT
DAC
LDAC
TFS
TCLK
DT
DAC
SERIAL
INTERFACE
DAC 3V
REFERENCE
APPLICATIONS
RO DAC
RO ADC
Digital Signal Processing
Speech Recognition and Synthesis
Spectrum Analysis
High Speed Modem s
DSP Servo Control
ADC 3V
REFERENCE
CONTROL
RFS
RCLK
ADC SERIAL
INTERFACE
DR
R
R
CLK
CLOCK
14 - BIT
ADC
V
IN
CONVST
GENERAL D ESCRIP TIO N
TRACK/HOLD
AGND
AD7869
T he AD7869 is a complete 14-bit I/O system containing a DAC
and an ADC. T he ADC is a successive approximation type with
a track-and-hold amplifier, having a combined throughput rate
of 83 kHz. T he DAC has an output buffer amplifier with a set-
tling time of 4 µs to 14 bits. T emperature compensated 3 V bur-
ied Zener references provide precision references for the DAC
and ADC.
DGND
V
SS
P RO D UCT H IGH LIGH TS
1. Complete 14-Bit I/O System.
T he AD7869 contains a 14-bit ADC with a track-and-hold
amplifier and a 14-bit DAC with output amplifier. Also in
cluded are separate on-chip voltage references for the DAC
and the ADC.
Interfacing to both the DAC and ADC is serial, minimizing pin
count and giving a small 24-pin package size. Standard control
signals allow serial interfacing to most DSP machines.
2. Dynamic Specifications for DSP Users.
In addition to traditional dc specifications, the AD7869 is
specified for ac parameters, including signal-to-noise ratio
and harmonic distortion. T hese parameters, along with im-
portant timing parameters, are tested on every device.
Asynchronous ADC conversion control and DAC updating is
made possible with the CONVST and LDAC logic inputs.
T he AD7869 operates from ±5 V power supplies; the analog in-
put/output range of the ADC/DAC is ±3 V. T he part is fully
specified for dynamic parameters such as signal-to-noise ratio
and harmonic distortion as well as traditional dc specifications.
3. Small Package.
T he AD7869 is available in a 24-pin DIP and a 28-pin SOIC
package.
T he part is available in a 24-pin, 0.3 inch wide, plastic or her-
metic dual-in-line package (DIP) and in a 28-pin, plastic SOIC
package.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1996
AD7869–SPECIFICATIONS
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = 0 V, fCLK = 2.0 MHz external.
DD
SS
ADC SECTION
P aram eter
All specifications TMIN to TMAX unless otherwise noted.)
J Version1
A Version1 Units
Test Conditions/Com m ents
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio3, 4 (SNR) @ +25°C
T MIN to T MAX
T otal Harmonic Distortion (T HD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order T erms
78
78
–86
–86
78
77
–86
–86
dB min
dB min
dB typ
dB typ
VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
–86
–88
2
–86
–88
2
dB typ
dB typ
µs max
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
T hird Order T erms
T rack/Hold Acquisition T ime
DC ACCURACY
Resolution
14
14
Bits
Minimum Resolution
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
Positive Gain Error5
Negative Gain Error5
14
±2
±1
±20
±20
±20
14
±2
±1
±20
±20
±20
Bits
No Missing Codes Are Guaranteed
LSB max
LSB max
LSB max
LSB max
LSB max
ANALOG INPUT
Input Voltage Range
Input Current
±3
±1
±3
±1
Volts
mA max
REFERENCE OUT PUT 6
RO ADC @ +25°C
RO ADC T C
2.99/3.01
±25
2.99/3.01
±25
V min/ V max
ppm/°C typ
±40
±ppm/°C max
Reference Load Sensitivity
(∆RO ADC vs. ∆I)
–1.5
–1.5
mV max
Reference Load Current Change (0–500 µA),
Reference Load Should Not Be Changed
During Conversion
LOGIC INPUT S
(CONVST, CLK, CONTROL)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±10
±10
10
2.4
0.8
±10
±10
10
V min
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VIN = 0 V to VDD
VIN = VSS to DGND
V max
µA max
µA max
pF max
Input Current7 (CONT ROL & CLK)
8
Input Capacitance, CIN
LOGIC OUT PUT S
DR, RFS Outputs
Output Low Voltage, VOL
RCLK Output
Output Low Voltage, VOL
DR, RFS, RCLK Outputs
Floating-State Leakage Current
Floating-State Output Capacitance8
0.4
0.4
0.4
0.4
V max
V max
ISINK = 1.6 mA, Pull-Up Resistor = 4.7 kΩ
ISINK = 2.6 mA, Pull-Up Resistor = 2 kΩ
±10
15
±10
15
µA max
pF max
CONVERSION T IME
External Clock
Internal Clock
10
10
10
10
µs max
µs max
The Internal Clock Has a Nominal Value of 2.0 MHz
POWER REQUIREMENT S
For Both DAC and ADC
VDD
VSS
IDD
ISS
+5
–5
22
12
170
+5
–5
22
12
170
V nom
V nom
mA max
mA max
mW max
±5% for Specified Performance
±5% for Specified Performance
Cumulative Current from the T wo VDD Pins
Cumulative Current from the T wo VSS Pins
T ypically 130 mW
T otal Power Dissipation
NOT ES
1T emperature ranges are as follows: J Version, 0°C to +70°C; A Version, –40°C to +85°C.
2VIN = ±3 V.
3SNR calculation includes distortion and noise components.
4SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.
5Measured with respect to internal reference.
6For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).
7T ying the CONT ROL input to VDD places the device in a factory test mode where normal operation is not exhibited.
8Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. A
AD7869
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = 0 V, Rl DAC = +3 V and decoupled as shown in Figure 2,
DD
SS
V Load to AGND; = 2 k⍀, C = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
DAC SECTION
P aram eter
OUT
L
J Versions1 A Version1
Units
Test Conditions/Com m ents
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio3 (SNR) @ +25°C 78
78
77
–86
dB min
dB min
dB typ
VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz
T ypically 82 dB at +25°C for 0 < VOUT < 20 kHz4
VOUT = 1 kHz Sine Wave, fSAMPLE = 83 kHz
Typically –84 dB at +25°C for 0 < VOUT < 20 kHz4
VOUT = 1 kHz, fSAMPLE = 83 kHz
T MIN to T MAX
78
T otal Harmonic Distortion (T HD)
–86
Peak Harmonic or Spurious Noise
–86
–86
dB typ
T ypically –84 dB at +25°C for 0 < VOUT < 20 kHz4
DC ACCURACY
Resolution
14
14
Bits
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
±2
±1
±10
±10
±10
±2
±1
±10
±10
±10
LSB max
LSB max
LSB max
LSB max
LSB max
Guaranteed Monotonic
Positive Full-Scale Error5
Negative Full-Scale Error5
REFERENCE OUT PUT 6
RO DAC @ +25°C
RO DAC T C
2.99/3.01
±25
2.99/3.01
±25
±40
V min/V max
ppm/°C typ
ppm/°C max
Reference Load Change
(∆RO DAC vs. ∆I)
–1.5
–1.5
mV max
Reference Load Current Change (0 µA–500 µA)
REFERENCE INPUT
RI DAC Input Range
Input Current
2.85/3.15
1
2.85/3.15
1
V min/V max 3 V ± 5%
µA max
LOGIC INPUT S
(LDAC, TFS, T CLK, DT )
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±10
10
2.4
0.8
±10
10
V min
VDD = 5 V ± 5%
VDD = 5 V ± 5%
VIN = 0 V to VDD
V max
µA max
pF max
7
Input Capacitance, CIN
ANALOG OUT PUT
Output Voltage Range
DC Output Impedance
Short-Circuit Current
±3
0.3
20
±3
0.3
20
V nom
Ω typ
mA typ
AC CHARACT ERIST ICS7
Voltage Output Settling-T ime
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Settling T ime to Within ±1/2 LSB of Final Value
T ypically 3 µs
T ypically 3.5 µs
4
4
10
2
100
4
4
10
2
100
µs max
µs max
nV secs typ
nV secs typ
dB typ
DAC Code Change All 1s to All 0s
VIN to VOUT Isolation
VIN = ±3 V, 41.5 kHz Sine Wave
POWER REQUIREMENT S
NOT ES
As per ADC Section
1T emperature ranges are as follows: J Version, 0°C to +70°C; A Version, –40°C to +85°C.
2VOUT (p-p) = ±3 V.
3SNR calculation includes distortion and noise components.
4Using external sample and hold, see Figures 13 to 15.
5Measured with respect to REF IN and includes bipolar offset error.
6For capacitive loads greater than 50 pF a series resistor is required (see Internal Reference section).
7Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice
REV. A
–3–
AD7869
1, 2
TIMING SPECIFICATIONS (V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = 0 V)
DD
SS
Lim it at TMIN, TMAX
(All Versions)
P aram eter
Units
Conditions/Com m ents
ADC T IMING
t1
t2
t3
t4
50
440
100
20
100
155
4
100
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns typ
CONVST Pulse Width
3
RCLK Cycle T ime, Internal Clock
RFS to RCLK Falling Edge Setup T ime
RCLK Rising Edge to RFS
4
t5
RCLK to Valid Data Delay, CL = 35 pF
Bus Relinquish T ime after RCLK
t6
5
t13
2 RCLK + 200 to
3 RCLK + 200
CONVST to RFS Delay
DAC T IMING
t7
t8
t9
t10
t11
tl2
50
75
150
30
75
40
ns min
ns min
ns min
ns min
ns min
ns min
TFS to T CLK Falling Edge
T CLK Falling Edge to TFS
T CLK Cycle T ime
Data Valid to T CLK Setup T ime
Data Valid to T CLK Hold T ime
LDAC Pulse Width
NOT ES
1T iming specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
voltage level of 1.6 V.
2Serial timing is measured with a 4.7 kΩ pull-up resistor on DR and RFS and a 2 kΩ pull-up resistor on RCLK. T he capacitance on all three outputs is 35 pF.
3When using internal clock, RCLK mark/space ratio (measured form a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space
ratio = external clock mark/space ratio.
4DR will drive higher capacitance loads but this will add to t 5 since it increases the external RC time constant (4.7 kΩ//CL) and hence the time to reach 2.4 V.
5T ime 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.
6T CLK mark/space ratio is 40/60 to 60/40.
ABSO LUTE MAXIMUM RATINGS*
(T A = + 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Operating T emperature Range
J Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
A Version . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . 1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD
VIN to AGND . . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V
RO ADC to AGND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
RO DAC to AGND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
RI DAC to AGND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7869 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
O RD ERING GUID E
Signal-
Tem perature
Range
to-Noise
Ratio (SNR) Accuracy
Relative
P ackage
O ption*
Model
AD7869JN
AD7869JR
AD7869AQ
0°C to +70°C
0°C to +70°C
–40°C to +85°C
78 dB
78 dB
77 dB
±2 LSB max
±2 LSB max
±2 LSB max
N-24
R-28
Q-24
*N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).
–4–
REV. A
AD7869
AD 7869 P IN FUNCTIO N D ESCRIP TIO N
D IP P in
Num ber
Mnem onic
Function
POWER SUPPLY
7 & 23
10 & 22
8 & 19
6 & 17
VDD
Positive Power Supply, 5 V ± 5%. Both VDD pins must be tied together.
Negative Power Supply, –5 V ± 5%. Both VSS pins must be tied together.
Analog Ground. Both AGND pins must be tied together.
VSS
AGND
DGND
Digital Ground. Both DGND pins must be tied together.
ANALOG SIGNAL AND REFERENCE
21
VIN
ADC Analog Input. T he ADC input range is ±3 V.
9
VOUT
Analog Output Voltage from DAC. T his output comes from a buffer amplifier. T he range is bipolar, ±3 V
with RI DAC = +3 V.
20
11
12
RO ADC
RO DAC
RI DAC
Voltage Reference Output. T he internal ADC 3 V reference is provided at this pin. T his output may be used as a
reference for the DAC by connecting it to the RI DAC input. T he external load capability of this reference is 500 µA.
DAC Voltage Reference Output. T his is one of two internal voltage references. T o operate the DAC with this
internal reference, RO DAC should be connected to RI DAC. T he external load capability of the reference is 500 µA.
DAC Voltage Reference Input. T he voltage reference for the DAC must be applied to this pin. It is internally
buffered before being applied to the DAC. T he nominal reference voltage for correct operation of the AD7869 is 3 V.
ADC INT ERFACE AND CONT ROL
2
CLK
Clock Input. An external T T L-compatible clock may be applied to this input. Alternatively, tying this pin to VSS
enables the internal laser-trimmed oscillator.
3
RFS
Receive Frame Synchronization, Logic Output. T his is an active low open-drain output that provides a framing
pulse for serial data. An external 4.7 kΩ pull-up resistor is required on RFS.
4
5
RCLK
Receive Clock, Logic Output. RCLK is the gated serial clock output that is derived from the internal or external
ADC clock. If the CONT ROL input is at VSS, the clock runs continuously. With the CONT ROL input at DGND,
the RCLK output is gated off (three-state) after serial transmission is complete. RCLK is an open-drain output and
requires an external 2 kΩ pull-up resistor.
DR
Receive Data, Logic Output. T his is an open-drain data output used in conjunction with RFS and RCLK to transmit
data from the ADC. Serial data is valid on the falling edge of RCLK when RFS is low. An external 4.7 kΩ resistor is
required on the DR output.
1
CONVST
Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into the hold
mode and starts an ADC conversion. T his input is asynchronous to the CLK input.
24
CONT ROL
Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the RCLK is contin-
uous. Note, tying this pin to VDD places the part in a factory test mode where normal operation is not exhibited.
DAC INT ERFACE AND CONT ROL
14
TFS
T ransmit Frame Synchronization, Logic Input. T his is a frame or synchronization signal for the DAC with serial
data expected after the falling edge of this signal.
15
DT
T ransmit Data, Logic Input. T his is the data input that is used in conjunction with TFS and T CLK to transfer
serial data to the input latch.
16
13
T CLK
LDAC
T ransmit Clock, Logic Input. Serial data bits are latched on the falling edge of T CLK when TFS is low.
Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the falling edge
of this signal.
18
NC
No Connect.
P IN CO NFIGURATIO NS
D IP
SO IC
0.708 (18.02)
CONTROL
VDD
24
23
22
21
1
2
CONVST
CLK
0.696 (17.67)
28
15
14
3
VSS
VIN
RFS
0.299 (7.6)
0.414 (10.52)
0.398 (10.10)
RCLK
4
0.291 (7.39)
20 RO ADC
19 AGND
18 NC
5
DR
DGND
VDD
1
AD7869
TOP VIEW
6
(Not to Scale)
7
0.096 (2.44)
0.03 (0.76)
0.02 (0.51)
x
45°
DGND
17
8
AGND
0.089 (2.26)
TCLK
DT
9
16
15
VOUT
VSS
10
11
12
6°
0°
0.05
(1.27)
BSC
0.019 (0.49)
0.014 (0.35)
0.01 (0.254)
0.006 (0.15)
0.042 (1.067)
0.018 (0.457)
0.013 (0.32)
14 TFS
RO DAC
RI DAC
0.009 (0.23)
13 LDAC
1. LEAD NO.
1
INDENTIFIED BY
A
DOT.
NC = NO CONNECT
2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
REV. A
–5–
AD7869
CO NVERTER D ETAILS
T he operation of the track/hold amplifier is essentially transpar-
ent to the user. T he track/hold amplifier goes from its track
mode to its hold mode at the start of conversion on the rising
edge of CONVST.
T he AD7869 is a complete 14-bit I/O port; the only external
components required for normal operation are pull-up resistors
for the ADC data outputs, and power supply decoupling capaci-
tors. T he AD7869 is comprised of a 14-bit successive approxi-
mation ADC with a track/hold amplifier, a 14-bit DAC with a
buffered output and two 3 V buried Zener references, a clock os-
cillator and control logic.
INTERNAL REFERENCES
T he AD7869 has two on-chip temperature compensated buried
Zener references that are factory trimmed to 3 V ±10 mV. One
reference provides the appropriate biasing for the ADC, while
the other is available as a reference for the DAC. Both reference
outputs are available (labelled RO DAC and RO ADC) and are
capable of providing up to 500 µA to an external load.
AD C CLO CK
T he AD7869 has an internal clock oscillator that can be used for
the ADC conversion procedure. T he oscillator is enabled by ty-
ing the CLK input to VSS. T he oscillator is laser trimmed at the
factory to give a maximum conversion time of 10 µs. T he mark/
space ratio can vary from 40/60 to 60/40. Alternatively, an exter-
nal T T L compatible clock may be applied to this input. T he al-
lowable mark/space ratio of an external clock is 40/60 to 60/40.
T he DAC input reference (RI DAC) can be sourced externally
or connected to any of the two on-chip references. Applications
requiring good full-scale error matching between the DAC and
the ADC should use the ADC reference as shown in Figure 4.
T he maximum recommended capacitance on either of the refer-
ence output pins for normal operation is 50 pF. If either of the
reference outputs is required to drive a capacitive load greater
than 50 pF, then a 200 Ω resistor must be placed in series with
the capacitive load. T he addition of decoupling capacitors,
10 µF in parallel with 0.1 µF as shown in Figure 2, improves
noise performance. T he improvement in noise performance can
be seen from the graph in Figure 3. Note: this applies for the
DAC output only; reference decoupling components do not af-
fect ADC performance. Consequently, a typical application will
have just the DAC reference decoupled with the other one open
circuited.
RCLK is a clock output, used for the serial interface. T his out-
put is derived directly from the ADC clock source and can be
switched off at the end of conversion with the CONT ROL
input.
AD C CO NVERSIO N TIMING
T he conversion time for both external clock and continuous in-
ternal clock can vary from 19 to 20 rising clock edges, depending
on the conversion start to ADC clock synchronization. If a con-
version is initiated within 30 ns prior to a rising edge of the ADC
clock, the conversion time will consist of 20 rising clock edges,
i.e., 9.5 µs conversion time. For noncontinuous internal clock,
the conversion time always consists of 19 rising clock edges.
RI DAC
AD C TRACK-AND -H O LD AMP LIFIER
T he track-and-hold amplifier on the analog input of the AD7869
allows the ADC to accurately convert an input sine wave of 6 V
peak–peak amplitude to 14-bit accuracy. T he input impedance is
typically 9 kΩ; an equivalent circuit is shown in Figure 1. T he
input bandwidth of the track/hold amplifier is much greater
than the Nyquist rate of the ADC even when the ADC is oper-
ated at its maximum throughput rate. T he 0.1 dB cutoff fre-
quency occurs typically at 500 kHz. T he track/hold amplifier
acquires an input signal to 14-bit accuracy in less than 2 µs. T he
overall throughput rate is equal to the conversion time plus the
track/hold amplifier acquisition time. For a 2.0 MHz input clock,
the throughput time is 12 µs max.
RO DAC
200Ω
EXT LOAD
or
GREATER THAN 50pF
RO ADC*
0.1µF
10µF
*RO DAC/RO ADC CAN BE LEFT
OPEN CIRCUIT IF NOT USED
Figure 2. Reference Decoupling Com ponents
D AC O UTP UT AMP LIFIER
T he output from the voltage mode DAC is buffered by a non-
inverting amplifier. T he buffer amplifier is capable of developing
±3 V across 2 kΩ and 100 pF load to ground and can produce
6 V peak-to-peak sine wave signals to a frequency of 20 kHz.
T he output is updated on the falling edge of the LDAC input.
T he output voltage settling time, to within 1/2 LSB of its final
value, is typically less than 3.5 µs.
TRACK/HOLD
AMPLIFIER
4.5kΩ
TO INTERNAL
COMPARATOR
V
IN
4.5kΩ
AD7869*
T he small signal (200 mV p–p) bandwidth of the output buffer
amplifier is typically 1 MHz. T he output noise from the ampli-
fier is low with a figure of 30 nV/√Hz at a frequency of 1 kHz.
T he broadband noise from the amplifier exhibits a typical peak-
to-peak figure of 150 µV for a 1 MHz output bandwidth. Figure
3 shows a typical plot of noise spectral density versus frequency
for the output buffer amplifier and for either of the on-chip
references.
TO INTERNAL
3V REFERENCE
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 1. ADC Analog Input
REV. A
–6–
AD7869
AD C AD JUSTMENT
500
Figure 6 has signal conditioning at the input and output of the
AD7869 for trimming the endpoints of the transfer functions of
both the ADC and the DAC. Offset error must be adjusted be-
fore full-scale error. For the ADC, this is achieved by trimming
the offset of A1 while the input voltage, V1, is 1/2 LSB below
ground. T he trim procedure is as follows: apply a voltage of
–183 µV (–1/2 LSB) at V1 in Figure 6 and adjust the offset volt-
age of A1 until the ADC output code flickers between 11 1111
1111 1111 (3FFF HEX) and 00 0000 0000 0000 (0000 HEX).
T
= +25°C
A
V
V
= +5V
= –5V
DD
SS
200
100
REF OUT
50
OUTPUT WITH
ALL 0s LOADED
REF OUT DECOUPLED
AS SHOWN IN
FIGURE 2
20
10
V1
INPUT VOLTAGE
RANGE = ±3V
50
100
200
10k
100k
1k
2k
20k
FREQUENCY – Hz
R1
10k
Figure 3. Noise Spectral Density vs. Frequency
R2
500
INP UT/O UTP UT TRANSFER FUNCTIO NS
A bipolar circuit for the AD7869 is shown in Figure 4.
A1
VIN
VOUT
R3
T he analog input/output voltage range of the AD7869 is ±3 V.
T he designed code transitions for the ADC occur midway be-
tween successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB,
5/2 LSB . . . FS –3/2 LSBs). T he input/output code is 2s
Complement Binary with 1 LSB = FS/16384 = 366 µV. T he
ideal transfer function is shown in Figure 5.
10k
R6
10k
R4
10k
AD7869*
R5
10k
V0
OUTPUT VOLTAGE
RANGE = ± 3V
R7
500
A2
AGND
R8
10k
R9
10k
R10
10k
*ADDITIONAL PINS
OMITTED FOR
CLARITY
AD7869*
ANALOG OUTPUT
V
IN
RANGE = ±3V
V
OUT
ANALOG INPUT
RANGE = ±3V
RI DAC
Figure 6. AD7869 with Input/Output Adjustm ent
R1
200
ADC gain error can be adjusted at either the first code transi-
tion (ADC negative full scale) or the last code transition (ADC
positive full scale). T he trim procedures for both cases are as
follows (see Figure 6).
RO ADC
C1
10µF
C2
0.1µF
AGND
AD C P ositive Full-Scale Adjustm ent
*ADDITIONAL PINS OMITTED FOR CLARITY
Apply a voltage of 2.99945 V (FS/2 – 3/2 LSBs) at V1. Adjust
R2 until the ADC output code flickers between 01 1111 1111
1110 (1FFE HEX) and 01 1111 1111 1111 (1FFF HEX).
Figure 4. Basic Bipolar Operation
OUTPUT
CODE
AD C Negative Full-Scale Adjustm ent
011...111
Apply a voltage of –2.99982 V (–FS/2 + 1/2 LSB) at V1 and ad-
just R2 until the ADC output code flickers between 10 0000
0000 0000 (2000 HEX) and 10 0000 0000 0001 (2001 HEX).
011...110
000...010
000...001
-FS
2
D AC AD JUSTMENT
000...000
111...111
+FS
2
-1LSB
Op amp A2 is included in Figure 6 for the DAC transfer func-
tion adjustment. Again, offset must be adjusted before full scale.
T o adjust offset, load the DAC with 00 0000 0000 0000 (0000
HEX) and trim the offset of A2 to 0 V. As with the ADC adjust-
ment, gain error can be adjusted at either the first code transi-
tion (DAC negative full scale) or the last code transition (DAC
positive full scale). T he trim procedures for both cases are as
follows:
111...110
FS = 6V
FS
16384
1LSB =
100...001
100...000
0V
INPUT VOLTAGE
Figure 5. Input/Output Transfer Function
D AC P ositive Full-Scale Adjustm ent
O FFSET AND FULL SCALE AD JUSTMENT
Load the DAC with 01 1111 1111 1111 (1FFF HEX) and ad-
just R7 until the op amp output voltage is equal to 2.99963 V
(FS/2 – 1 LSB).
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale errors do not cause problems as long as
the input signal is within the full dynamic range of the ADC.
For applications requiring that the input signal range match the
full analog input dynamic range of the ADC, offset and full-
scale errors have to be adjusted to zero.
D AC Negative Full-Scale Adjustm ent
Load the DAC with 10 0000 0000 0000 (2000 HEX) and adjust
R7 until the op amp output voltage is equal to –3 V (–FS/2).
REV. A
–7–
AD7869
TIMING AND CO NTRO L
D AC TIMING
Communication with the AD7869 is managed by six dedicated
pins. T hese consist of separate serial clocks, word framing or
strobe pulses, and data signals for both receiving and transmit-
ting data. Conversion starts and DAC updating are controlled
by two digital inputs, CONVST and LDAC. T hese inputs can
be asserted independently of the microprocessor by an external
timer when precise sampling intervals are required. Alterna-
tively, the LDAC and CONVST can be driven from a decoded
address bus, allowing the microprocessor control over conver-
sion start and DAC updating as well as data communication to
the AD7869.
T he AD7869 DAC contains two latches, an input latch and a
DAC latch. Data must be loaded to the input latch under the
control of the T CLK, TFS and DT serial logic inputs. Data is
then transferred from the input latch to the DAC latch under
the control of the LDAC signal. Only the data in the DAC latch
determines the analog output of the AD7869.
Data is loaded to the input latch under control of T CLK, TFS
and DT . T he AD7869 DAC expects a 16-bit stream of serial
data on its DT input. Data must be valid on the falling edge of
T CLK. T he TFS input provides the frame synchronization sig-
nal, which tells the AD7869 DAC that valid serial data will be
available for the next 16 falling edges of T CLK. Figure 8 shows
the timing diagram for the serial data format.
AD C Tim ing
Conversion control is provided by the CONVST input. A low to
high transition on CONVST input starts conversion and drives
the track/hold amplifier into its hold mode. Serial data then be-
comes available while conversion is in progress. T he corre-
sponding timing diagram is shown in Figure 7. T he word length
is 16 bits, two leading zeros followed by the 14-bit conversion
result starting with the MSB. T he data is synchronized to the
serial clock output (RCLK) and is framed by the serial strobe
(RFS). Data is clocked out on a low to high transition of the se-
rial clock and is valid on the falling edge of this clock while the
RFS output is low. RFS goes low at the start of conversion, and
the first serial data bit (which is the first leading zero) is valid on
the first falling edge of RCLK. All the ADC serial lines are
open-drain outputs and require external pull-up resistors.
t
t
7
8
TFS
t
9
TCLK
t
11
t
10
DON'T DON'T
CARE CARE
DT
DB11 DB10
DB1 DB0
DB13 DB12
Figure 8. DAC Control Tim ing Diagram
Although 16 bits of data are clocked into the input latch, only
14 bits are transferred into the DAC latch. T herefore, two bits
in the stream are don’t cares since their value does not affect the
DAC latch data. T he bit positions are two don’t cares, followed
by the 14-bit DAC data starting with the MSB.
CONVERSION TIME
t
1
CONVST
T he LDAC signal controls the transfer of data to the DAC
latch. Normally, data is loaded to the DAC latch on the falling
edge of LDAC. However, if LDAC is held low, then serial data
is loaded to the DAC latch on the sixteenth falling edge of
T CLK. If LDAC goes low during the loading of serial data to
the input latch, no DAC latch update takes place on the falling
edge of LDAC. If LDAC stays low until the serial transfer is
completed, the update takes place on the sixteenth falling edge
of T CLK. If LDAC returns high before the serial data transfer
is completed, no DAC latch update takes place.
t
13
1
RFS
t
t
t
3
4
2
2,3
RCLK
t
t
5
6
DB13 DB12 DB11
DB1 DB0
1
DR
Figure 7. ADC Control Tim ing Diagram
T he serial clock out is derived from the ADC master clock
source, which may be internal or external. Normally, RCLK is
required during the serial transmission only. In these cases, it
can be shut down (i.e., placed into three-state) at the end of
conversion to allow multiple ADCs to share a common serial
bus. However, some serial systems (e.g., T MS32020) require a
serial clock that runs continuously. Both options are available
on the AD7869 ADC. With the CONT ROL input at 0 V,
RCLK is noncontinuous; when it is at –5 V, RCLK is
continuous.
REV. A
–8–
AD7869
AD 7869 D YNAMIC SP ECIFICATIO NS
T he AD7869 is specified and 100% tested for dynamic perfor-
mance specifications as well as traditional dc specifications such
as Integral and Differential Nonlinearity. T hese ac specifications
are required for signal processing applications such as speech
recognition, spectrum analysis and high speed modems. T hese
applications require information on the converter’s effect on the
spectral content of the input signal. Hence, the parameters for
which the AD7869 is specified include SNR, harmonic distor-
tion and peak harmonics. T hese terms are discussed in more de-
tail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC or DAC. T he signal is the rms magnitude of the funda-
mental. Noise is the rms sum of all the nonfundamental signals
up to half the sampling frequency (fSAMPLE/2), excluding dc.
SNR is dependent upon the number of levels used in the quanti-
zation process; the more levels, the smaller the quantization
noise. T he theoretical signal-to-noise ratio for a sine wave input
is given by
Figure 9. ADC FFT Plot
SNR = (6.02N + 1.76) dB
(1)
where N is the number of bits. T hus for an ideal 14-bit con-
verter, SNR = 86 dB.
Figure 10 shows a typical plot of effective number of bits versus
frequency for an AD7869AQ with a sampling frequency of
60 kHz. T he effective number of bits typically falls between 12.7
and 13.1, corresponding to SNR figures of 79 dB and 80.4 dB.
Effective Num ber of Bits
T he formula given in Equation (1) relates the SNR to the num-
ber of bits. Rewriting the formula, as in Equation (2), it is pos-
sible to obtain a measure of performance expressed in effective
number of bits (N).
SNR –1.76
N =
(2)
6.02
T he effective number of bits for a device can be calculated di-
rectly from its measured SNR.
H ar m onic D istor tion
Harmonic Distortion is the ratio of the rms sum of harmonics to
the fundamental. For the AD7869, total harmonic distortion
(T HD) is defined as:
Figure 10. Effective Num ber of Bits vs. Frequency for the
ADC
2
V2 2 +V3 2 +V4 2 +V5 2 +V6
D AC Testing
THD = 20 log
V1
A simplified diagram of the method used to test the dynamic
performance specifications of the DAC is outlined in Figure 11.
Data is loaded to the DAC under control of the microcontroller
and associated logic. T he output of the DAC is applied to a 9th
order low pass filter whose cutoff frequency corresponds to the
Nyquist limit. T he output of the filter is, in turn, applied to a
16-bit accurate digitizer. T his digitizes the signal and the micro-
controller generates an FFT plot from which the dynamic per-
formance of the DAC can be evaluated.
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through to
the sixth harmonic. T he T HD is also derived from the FFT plot
of the ADC or DAC output spectrum.
AD C Testing
T he output spectrum from the ADC is evaluated by applying a
sine wave signal of very low distortion to the VIN input while
reading multiple conversion results. A Fast Fourier T ransform
(FFT ) plot is generated from which the SNR data can be ob-
tained. Figure 9 shows a typical 2048 point FFT plot of the
AD7869AQ ADC with an input signal of 10 kHz and a sam-
pling frequency of 60 kHz. T he SNR obtained from this graph
is 80 dB. It should be noted that the harmonics are taken into
account when calculating the SNR.
LOW-PASS
16-BIT
DIGITIZER
MICRO-
CONTROLLER
AD7869
DAC
FILTER
Figure 11. DAC Dynam ic Perform ance Test Circuit
REV. A
–9–
AD7869
T he digitizer sampling is synchronized with the DAC update
rate to ease FFT calculations. T he digitizer samples the DAC
output after the output has settled to its new value. T herefore, if
the digitizer were to directly sample the output, it would effec-
tively be sampling a dc value each time. As a result, the dynamic
performance of the DAC would not be measured correctly. Us-
ing the digitizer directly on the DAC output would give better
results than the actual performance of the DAC. Using a filter
between the DAC and the digitizer means that the digitizer
samples a continuously moving signal, and the true dynamic
performance of the AD7869 DAC output is measured.
P er for m ance ver sus Fr equency
T he typical performance plots of Figures 14 and 15 show the
AD7869 DAC performance over a wide range of input frequen-
cies at an update rate of 83 kHz. T he plot of Figure 14 is with-
out a sample-and-hold on the DAC output while the plot of
Figure 15 is generated with a sample-and-hold on the output.
Figure 12 shows a typical 2048 point Fast Fourier T ransform
plot for the AD7869 DAC with an update rate of 83 kHz and an
output frequency of 1 kHz. T he SNR obtained from the graph is
82 dBs.
Figure 14. DAC Perform ance vs. Frequency (No
Sam ple-and-Hold)
Figure 12. DAC FFT Plot
Some applications will require improved performance versus fre-
quency from the AD7869 DAC. In these applications, a simple
sample-and-hold circuit such as that outlined in Figure 13 will
extend the very good performance of the DAC to 20 kHz. Other
applications will already have an inherent sample-and-hold
function following the AD7869 DAC output. An example of
this type of application is driving a switched capacitor filter
where the updating of the DAC is synchronized with the
switched capacitor filter. T his inherent sample-and-hold func-
tion also extends the frequency range performance.
R2
2k2
Figure 15. DAC Perform ance vs. Frequency (Sam ple-and-
Hold)
C9
ADG201HS
330pF
R1
2k2
VOUT
AD7869*
S1
D1
AD711
LDAC
IN1
1µs
Q
ONE SHOT
DELAY
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. DAC Sam ple-and-Hold Circuit
REV. A
–10–
AD7869
MICRO P RO CESSO R INTERFACING
AD 7869–D SP 56000 Inter face
Microprocessor interfacing to the AD7869 is via a serial bus that
uses standard protocol compatible with DSP machines. T he
communication interface consists of separate transmit (DAC)
and receive (ADC) sections whose operations can be either syn-
chronous or asynchronous with respect to each other. Each sec-
tion has a clock signal, a data signal and a frame or strobe pulse.
Synchronous operation means that data is transmitted from the
ADC and to the DAC at the same time. In this mode, only one
interface clock is needed, and this has to be the ADC clock out;
RCLK must be connected to T CLK. For asynchronous opera-
tion, DAC and ADC data transfers are independent of each
other; the ADC provides the receive clock (RCLK) while the
transmit clock (T CLK) may be provided by the processor or the
ADC or some other external clock source.
Figure 16 shows a typical interface between the AD7869 and
DSP56000. T he interface arrangement is synchronous with a
gated clock requiring only three lines of interconnect. T he
DSP56000 internal serial control registers have to be configured
for a 16-bit data word with valid data on the first falling clock
edge. Conversion starts and DAC updating are controlled by an
external timer. Data transfers, which occur during ADC conver-
sions, are between the processor receive and transmit shift regis-
ters and the AD7869’s ADC and DAC. At the end of each
16-bit transfer, the DSP56000 receives an internal interrupt in-
dicating the transmit register is empty, and the receive register is
full.
CONVST
LDAC
TIMER
Another option to be considered with serial interfacing is the use
of a gated clock. A gated clock means that the device sending
the data switches on the clock when data is ready to be transmit-
ted and three states the clock output when transmission is com-
plete. Only 16 clock pulses are transmitted with the first data bit
being latched into the receiving device on the first falling clock
edge. Ideally, there is no need for frame pulses, however the
AD7869 DAC frame input (TFS) has to be driven high between
data transmissions. T he easiest method is to use RFS to drive
TFS and use only synchronous interfacing. T his avoids the use
of interconnects between the processor and AD7869 frame sig-
nals. Not all processors have a gated clock facility; Figure 16
shows an example with the DSP56000.
CONTROL
+5V
AD7869*
DSP56000
4.7kΩ
2kΩ
4.7kΩ
RFS
SC0
TFS
RCLK
DR
SCK
SRD
DT
STD
TCLK
T able I below shows the number of interconnect lines between
the processor and the AD7869 for the different interfacing
options.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. AD7869–DSP56000 Interface
AD 7869–AD SP -2101/2102 Inter face
T he AD7869 has the ability to use different clocks for transmit-
ting and receiving data. T his option, however, exists only on
some processors and normally just one clock (ADC clock) is
used for all communication with the AD7869. For simplicity, all
the interface examples in this data sheet use synchronous inter-
facing and use the ADC clock (RCLK) as an input for the DAC
clock (T CLK). For a better understanding of each of these in-
terfaces, consult the relevant processor data sheet.
An interface that is suitable for the ADSP-2101 or the ADSP-
2102 is shown in Figure 17. T he interface is configured for syn-
chronous, continuous clock operation. T he LDAC is tied low so
the DAC gets updated on the sixteenth falling clock after TFS
goes low. Alternatively, LDAC may be driven from a timer as
shown in Figure 16. As with the previous interface, the proces-
sor receives an interrupt after reading or writing to the AD7869
and updates its own internal registers in preparation for the next
data transfer.
Table I. Interconnect Lines for D ifferent Interfacing O ptions
Num ber of
Configuration
Interconnects Signals
CONVST
TIMER
Synchronous
4
RCLK, DR, DT and RFS
(T CLK = RCLK, TFS = RFS)
CONTROL
–
5V
+
5V
ADSP-2101/2
Asynchronous*
5 or 6
RCLK, DR, RFS, DT , TFS
(T CLK = RCLK or
µP serial CLK)
AD7869*
4.7kΩ
2kΩ
4.7kΩ
RFS
RFS
RCLK
DR
SCLK
DR
Synchronous
Gated Clock
3
RCLK, DR and DT
(T CLK = RCLK, TFS = RFS)
TFS
DT
TFS
TCLK
DT
*5 LINES OF INT ERCONNECT WHEN T CLK = RCLK
6 LINES OF INT ERCONNECT WHEN T CLK = µP SERIAL CLK
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. AD7869–ADSP-2101/ADSP-2102 Interface
REV. A
–11–
AD7869
AD 7869–TMS32020 Inter face
tween the source and the ADC. Reduce the ground circuit im-
pedance as much as possible since any potential difference in
grounds between the signal source and the ADC appears as an
error voltage in series with the input signal.
Figure 18 shows an interface that is suitable for the T MS32020/
T MS320C25 processors. T his interface is configured for syn-
chronous, continuous clock operation. Note the AD7869 will
not correctly interface to these processors if the AD7869 is con-
figured for a noncontinuous clock. Conversion starts and DAC
updating are controlled by an external timer.
INP UT/O UTP UT BO ARD
Figure 19 shows an analog I/O board based on the AD7869.
T he corresponding printed circuit (PC) board layout and
silkscreen are shown in Figures 21 to 23.
TIMER
CONVST
LDAC
T he analog input to the AD7869 is buffered with an AD711 op
amp. T here is a component grid provided near the analog input
on the PC board that may be used for an antialiasing filter for
the ADC or a reconstruction filter for the DAC or any other
conditioning circuitry. T o facilitate this option, there are two
wire links (labeled LK1 and LK2) required on the analog input
and output tracks.
–
5V
CONTROL
TMS32020/
TMS320C25
+
5V
AD7869*
4.7kΩ
2kΩ
4.7kΩ
FSR
RFS
CLKR
DR
RCLK
DR
T he board contains a SHA circuit that can be used on the out-
put of the AD7869 DAC to extend the very good performance
of the part over a wider frequency range. T he increased perfor-
mance from the SHA can be seen from Figures 14 and 15 of
this data sheet. A wire link (labeled LK3) connects the board
output to either the SHA output or directly to the AD7869
DAC output .
FSX
CLKX
DX
TFS
TCLK
DT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. AD7869–TMS32020/TMS32025 Interface
T here are three LDAC link options on the board; LDAC can be
driven from an external source independent of CONVST,
LDAC can be tied to CONVST or LDAC can be tied to GND.
Choosing the latter option disables the SHA operation and
places the SHA permanently in the track mode.
AP P LICATIO N H INTS
Good printed circuit board (PCB) layout is as important as the
circuit design itself in achieving high speed A/D performance.
T he AD7869’s comparator is required to make bit decisions on
an LSB size of 366 µV. T o achieve this, the designer has to be
conscious of noise both in the ADC itself and in the preceding
analog circuitry. Switching mode power supplies are not recom-
mended as the switching spikes will feed through to the com-
parator causing noisy code transitions. Other causes of concern
are ground loops and digital feedthrough from microprocessors.
T hese are factors that influence any ADC, and a proper PCB
layout that minimizes these effects is essential for best
performance.
Microprocessor connections to the board are made by a 9-way
D-type connector. T he pinout is shown in Figure 20. T he
ADC’s digital outputs are buffered with 74HC4050s. T hese
buffers provide a higher current output capability for high
capacitance loads or cables. Normally, these buffers are not re-
quired as the AD7869 will be sitting on the same board as the
processor.
P O WER SUP P LY CO NNECTIO NS
T he PC board requires two analog power supplies and one 5 V
digital supply. Connections to the analog supply are made di-
rectly to the PC board as shown on the silkscreen in Figure 21.
T he connections are labeled V+ and V–, and the range for both
of these supplies is 12 V to 15 V. Connections to the 5 V digital
supply are made through the D-type connector SKT 6. T he
±5 V analog supply required by the AD7869 is generated from
two voltage regulators on the V+ and V– supplies.
LAYO UT H INTS
Ensure that the layout for the printed circuit board has the digi-
tal and analog signal lines separated as much as possible. T ake
care not to run any digital track alongside an analog signal track.
Guard (screen) the analog input with AGND.
Establish a single point analog ground (star ground), separate
from the logic system ground, as close as possible to the
AD7869 AGND pins. Connect all other grounds and the
AD7869 DGND to this single analog ground point. Do not
connect any other digital grounds to this analog ground point.
WIRE LINK O P TIO NS
LK1, Analog Input Link
LK1 connects the analog input to a component grid or to a
buffer amplifier which drives the ADC input.
Low impedance analog and digital power supply common re-
turns are essential to low noise operation of the ADC, so make
the foil width for these tracks as wide as possible. T he use of
ground planes minimizes impedance paths and also guards the
analog circuitry from digital noise. T he circuit layout of Figures
22 and 23 have both analog and digital ground planes that are
kept separated and only joined together at the AD7869 AGND
pins.
LK2, Analog O utput Link
LK2 connects the analog output to the component grid or to ei-
ther the SHA or DAC output (see LK3).
LK3, SH A or D AC Select
T he analog output may be taken directly from the DAC or from
a SHA at the output of the DAC.
LK4, D AC Refer ence Selection
T he DAC reference may be connected to either the ADC refer-
ence output (RO ADC) or to the DAC reference (RO DAC).
NO ISE
Keep the input signal leads to VIN and signal return leads from
AGND as short as possible to minimize input noise coupling. In
applications where this is not possible, use a shielded cable be-
REV. A
–12–
AD7869
5V
+
V
IN
OUT
C2
C1
IC5
78L05
0.1µF
10µF
+
V
GND
C5
C6
10µF
0.1µF
ANALOG INPUT
VDD
VDD
LK1
C
±3V RANGE
R7
A
B
200
AD711
+
RO ADC
VIN
IC2
SKT1
C24
C23
A
B
0.1µF
–
V
10µF
COMPONENT
GRID
RI DAC
LK4
C7
C8
0.1µF
C
RO DAC
10µF
IC1
AD7869
–
5V
A
B
LK5
CONTROL
C
COMPONENT
GRID
AGND
AGND
SKT6
B
LK2
C
9-WAY D-TYPE
CONNECTOR
SKT2
B
5V
A
C
IC7 1/2
A
74HC4050
ANALOG OUTPUT
5V
DGND
DGND
R3
4.7k
R4
2k
R5
4.7kΩ
LK3
±3V RANGE
+
V
Ω
Ω
DR
DR
RCLK
RFS
C10
C9
10µF
0.1µF
RCLK
RFS
IC4
ADG201HS
AD711
+
R1
2k
IC3
Ω
LK9
VOUT
V–
LK8
TFS
TCLK
DT
C12
0.1µF
C11
TFS
10µF
TCLK
C21
330pF
DT
R2
2k
DGND
Ω
CLK
5V
LDAC
CONVST
VSS
R6
VCC
Q
15k
REXT/CEXT
VSS
C22
68pF
B
A
B
A
C
–
V–
5V
CEXT
OUT
IN
5V
LK7
–
5V
C4
IC6
C3
10µF
IC8 1/2
CLR
0.1µF
79L05
74HC221
A
B
C
GND
GND
LK6
SKT3
LDAC
SKT4
SKT5
EXT CLK
CONVST
Figure 19. Input/Output Circuit Based on the AD7869
LK9 Tr ansm it/Receive Clock O ption
LK5, AD C Inter nal Clock Selection
T his link configures the ADC for continuous or noncontinuous
internal clock operation.
LK9 provides the option to connect the ADC RCLK to the
DAC T CLK.
LK6, D AC Updating
T he DAC, LDAC input may asserted independently of the
ADC CONVST signal or it may be tied to CONVST or it may
tied to GND.
1
2
3
4
5
LK7, AD C Clock Sour ce
6
7
8
9
T his link provides the option for the ADC to use its own inter-
nal clock oscillator or an external T T L compatible clock.
LK8 Fr am e Synchr onous O ption
NC = NO CONNECT
LK8 provides the option of tying the ADC RFS output to the
DAC TFS input.
Figure 20. SKT6, D-Type Connector Pinout
REV. A
–13–
AD7869
CO MP O NENT LIST
IC1
C21
C22
330 pF Capacitor
68 pF Capacitor
AD7869
IC2, IC3
IC4,
IC5,
IC6,
IC7,
2X AD711
ADG201HS
MC78L05
MC79L05
74HC4050
74HC221
R1, R2, R4
R3, R5
R6
2 kΩ Resistor
4.7 kΩ Resistor
15 kΩ Resistor
200 Ω Resistor
R7
LK1, LK2, LK3,
LK4, LK5, LK6,
LK7, LK8, LK9
IC8,
C1, C3, C5, C7
C9, C11, C13, C15
C17, C19, C23
Shorting Plugs
10 µF Capacitor
0.1 µF Capacitor
SKT 1, SKT 2, SKT 3,
SKT 4, SKT 5
BNC Sockets
C2, C4, C6, C8
C10, C12, C14, C16
C18, C20, C24
SKT 6
9-Contact D-T ype Connector
Figure 21. Silkscreen for the Circuit Diagram of Figure 19
REV. A
–14–
AD7869
Figure 22. Com ponent Side Layout for the Circuit Diagram of Figure 19
Figure 23. Solder Side Layout for the Circuit Diagram of Figure 19
REV. A
–15–
AD7869
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
24-P in P lastic D IP (N-24)
28-P in P lastic SO IC (R-28)
0.708 (18.02)
0.696 (17.67)
1.275 (32.30)
1.125 (28.60)
24
1
13
28
15
0.280 (7.11)
0.240 (6.10)
12
0.299 (7.6)
0.414 (10.52)
0.398 (10.10)
0.325 (8.25)
0.291 (7.39)
0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
0.300 (7.62)
PIN 1
1
14
0.210
(5.33)
MAX
0.150
(3.81)
MIN
0.096 (2.44)
0.089 (2.26)
0.03 (0.76)
0.02 (0.51)
x 45°
0.015 (0.381)
0.008 (0.204)
0.200 (5.05)
0.125 (3.18)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
6°
0°
0.05
(1.27)
BSC
0.019 (0.49)
0.014 (0.35)
0.01 (0.254)
0.006 (0.15)
0.042 (1.067)
0.018 (0.457)
0.013 (0.32)
0.009 (0.23)
1. LEAD NO. 1 INDENTIFIED BY A DOT.
2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
24-P in Cer dip (Q -24)
REV. A
–16–
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