AD5270BCPZ-20-RL7_技术文档

1024-/256-Position, 1% Resistor Tolerance Error,

SPI Interface and 50-TP Memory Digital Rheostat

Data Sheet

AD5270/AD5271

FEATURES

FUNCTIONAL BLOCK DIAGRAM

V

DD

Single-channel, 1024-/256-position resolution

20 kΩ, 50 kΩ, 100 kΩ nominal resistance

Maximum 1ꢀ nominal resistor tolerance error

50-times programmable (50-TP) wiper memory

Rheostat mode temperature coefficient: 5 ppm/°C

2.7 V to 5.5 V single-supply operation

2.5 V to 2.75 V dual-supply operation for ac or bipolar

operations

SPI-compatible interface

Wiper setting readback

Power on refreshed from 50-TP memory

Thin LFCSP, 10-lead, 3 mm × 3 mm × 0.8 mm package

Compact MSOP, 10-lead, 3 mm × 4.9 mm × 1.1 mm package

POWER-ON

RESET

AD5270/AD5271

RDAC

REGISTER

SCLK

SYNC

DIN

A

10/8

SERIAL

INTERFACE

W

50-TP

MEMORY

BLOCK

SDO

APPLICATIONS

V

EXT_CAP

GND

SS

Figure 1.

Mechanical rheostat replacements

Op-amp: variable gain control

Instrumentation: gain, offset adjustment

Programmable voltage to current conversions

Programmable filters, delays, time constants

Programmable power supply

Sensor calibration

The AD5270/AD5271 device wiper settings are controllable

through the SPI digital interface. Unlimited adjustments are

allowed before programming the resistance value into the

50-TP memory. The AD5270/AD5271 do not require any

external voltage supply to facilitate fuse blow and there are

50 opportunities for permanent programming. During 50-TP

activation, a permanent blow fuse command freezes the resistance

position (analogous to placing epoxy on a mechanical trimmer).

GENERAL DESCRIPTION

The AD5270/AD5271¹are single-channel, 1024-/256-position

digital rheostats that combine industry leading variable resistor

performance with nonvolatile memory (NVM) in a compact

package.

The AD5270/AD5271 ensure less than 1% end-to-end resistor

tolerance error and offer 50-times programmable (50-TP) memory.

The guaranteed industry leading low resistor tolerance error

feature simplifies open-loop applications as well as precision

calibration and tolerance matching applications.

The AD5270/AD5271 are available in a 3 mm × 3 mm, 10-lead

LFCSP package and in a 10-lead MSOP package. The parts are

guaranteed to operate over the extended industrial temperature

range of −40°C to +125°C.

¹Protected by U.S.Patent Number 7688240

Rev. F

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

AD5270/AD5271

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Shift Register............................................................................... 18

RDAC Register............................................................................ 18

50-TP Memory Block ................................................................ 18

Write Protection ......................................................................... 18

RDAC and 50-TP Read Operation .......................................... 19

Shut-Down Mode....................................................................... 20

Resistor Performance Mode...................................................... 20

Reset............................................................................................. 20

SDO Pin and Daisy-Chain Operation..................................... 21

RDAC Architecture.................................................................... 21

Programming the Variable Resistor......................................... 22

EXT_CAP Capacitor.................................................................. 22

Terminal Voltage Operating Range ......................................... 22

Power-Up Sequence ................................................................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 24

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—AD5270 .......................................... 3

Electrical Characteristics—AD5271 .......................................... 5

Interface Timing Specifications.................................................. 7

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 11

Test Circuits..................................................................................... 17

Theory of Operation ...................................................................... 18

Serial Data Interface................................................................... 18

REVISION HISTORY

3/13—Rev. E to Rev. F

Added LFCSP Throughout ..............................................................1

Changed OTP to 50-TP Throughout..............................................1

Changes to Product Title, Features, and General Description....1

Changes to Table 1.............................................................................3

Added Table 3; Renumbered Sequentially .....................................4

Changes to Table 4.............................................................................5

Added Table 6 ....................................................................................6

Changes to Table 8 and Table 9........................................................9

Added Figure 6 and changes to Table 10..................................... 10

Replaced Typical Performance Characteristics Section ............ 11

Changes to Figure 44...................................................................... 21

Updated Outline Dimensions....................................................... 23

Changes to Ordering Guide.......................................................... 24

Changed Resistor Noise Density, R_AW= 20 kΩ from 50 nV/√Hz

to 13 nV/√Hz; Table 1...................................................................... 4

Changed Resistor Noise Density, R_AW= 20 kΩ from 50 nV/√Hz

to 13 nV/√Hz; Table 4...................................................................... 6

Updated Outline Dimensions....................................................... 23

12/10—Rev. D to Rev. E

Changes to SDO Pin Description................................................. 10

Changes to SDO Pin and Daisy-Chain Operation Section....... 21

11/10—Rev. C to Rev. D

Changes to Figure 25...................................................................... 14

3/10—Rev. 0 to Rev. A

9/10—Rev. B to Rev. C

Changes to Product Title and General Description.....................1

Changes to Theory of Operation Section...................................14

10/09—Revision 0: Initial Version

Changes to Figure 3 Caption........................................................... 7

Changes to Figure 4 Caption........................................................... 8

Deleted Daisy-Chain Operation Section, Added SDO Pin and

Daisy-Chain Operation Section ................................................... 21

5/10—Rev. A to Rev. B

Rev. F | Page 2 of 24

Data Sheet

AD5270/AD5271

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—AD5270

V_DD= 2.7 V to 5.5 V, V_SS= 0 V; V_DD= 2.5 V to 2.75 V, V _SS= −2.5 V to −2.75 V; −40°C < T_A< +125°C, unless otherwise noted.

Table 1.

Parameter

Symbol

R-INL

Test Conditions/Comments

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution

Resistor Integral Nonlinearity^{2, 3}

10

−1

Bits

LSB

R_AW= 20 kΩ, |V_DD− V_SS| = 3.0 V to 5.5 V

R_AW= 20 kΩ, |V_DD− V_SS| = 2.7 V to 3.0 V

R_AW= 50 kΩ, 100 kΩ

+1

+1.5

+1

Resistor Differential Nonlinearity²

Nominal Resistor Tolerance

R-Perf Mode⁴

R-DNL

+1

−1

0.5

15

5

+1

%

See Table 2 and Table 3

Normal Mode

%

Resistance Temperature Coefficient^{5, 6}

Wiper Resistance

Code = full scale

Code = zero scale

ppm/°C

Ω

35

70

RESISTOR TERMINALS

Terminal Voltage Range^{5, 7}

Capacitance⁵A

V_SS

V_DD

V

f = 1 MHz, measured to GND, code =

half scale

f = 1 MHz, measured to GND, code =

half scale

90

40

pF

Capacitance⁵W

pF

Common-Mode Leakage Current⁵

V_A= V_W

50

nA

DIGITAL INPUTS

Input Logic⁵

High

V_INH

V_INL

I_IN

2.0

V

µA

pF

Low

0.8

Input Current

Input Capacitance⁵

DIGITAL OUTPUT

Output Voltage⁵

High

1

5

C_IN

V_OH

V_OL

R_{PULL_UP}= 2.2 kΩ to V_DD

V_DD− 0.1

V

Low

V_DD= 2.7 V to 5.5 V, V_SS= 0 V

V_DD= 2.5 V to 2.75 V, V_SS= −2.5 V to −2.75 V

0.4

0.6

+1

V

µA

pF

Tristate Leakage Current

Output Capacitance⁵

POWER SUPPLIES

Single-Supply Power Range

Dual-Supply Power Range

Supply Current

Positive

−1

5

V_SS= 0 V

2.7

2.5

5.5

2.75

V

I_DD

I_SS

1

µA

Negative

−1

50-TP Store Current^{5, 8}

Positive

Negative

I_{DD_OTP_STORE}

I_{SS_OTP_STORE}

4

−4

mA

OTP Read Current^{5, 9}

Positive

Negative

I_{DD_OTP_READ}

I_{SS_OTP_READ}

500

µA

−500

Rev. F | Page 3 of 24

AD5270/AD5271

Data Sheet

Parameter

Symbol

Test Conditions/Comments

Min

Typ¹

Max

Unit

µW

dB

Power Dissipation¹⁰

Power Supply Rejection Ratio⁵

V_IH= V_DDor V_IL= GND

ΔV_DD/ΔV_SS= 5 V 10%

5.5

PSRR

R_AW= 20 kΩ

R_AW= 50 kΩ

R_AW= 100 kΩ

−66

−75

−78

−55

−67

−70

DYNAMIC CHARACTERISTICS^{5, 11}

Bandwidth

−3 dB, R_AW= 10 kΩ, Terminal W,

see Figure 42

kHz

R_AW= 20 kΩ

R_AW= 50 kΩ

R_AW= 100 kΩ

300

120

60

Total Harmonic Distortion

Resistor Noise Density

V_A= 1 V rms, f = 1 kHz,

code = half scale

R_AW= 20 kΩ

R_AW= 50 kΩ

R_AW= 100 kΩ

Code = half scale, T_A= 25°C

R_AW= 20 kΩ

R_AW= 50 kΩ

dB

−90

−88

−85

nV/√Hz

13

25

32

R_AW= 100 kΩ

¹Typical specifications represent average readings at 25°C, V_DD= 5 V, and V_SS= 0 V.

²Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

³The maximum current in each code is defined by I_AW= (V_DD− 1)/R_AW

.

⁴The terms resistor performance mode and R-Perf mode are used interchangeably. See the Resistor Performance Mode section.

⁵Guaranteed by design and not subject to production test.

⁶See Figure 25 for more details.

⁷Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

⁸Different from operating current, the supply current for the fuse program lasts approximately 55 ms.

⁹Different from operating current, the supply current for the fuse read lasts approximately 500 ns.

10

P

is calculated from (I_DD× V_DD) + (I_SS× V_SS).

DISS

¹¹All dynamic characteristics use V_DD= +2.5 V, V_SS= −2.5 V.

Table 2. AD5270—20 kΩ Resistor Performance Mode Code Range

Resistor Tolerance Per Code

|V_DD− V_SS| = 4.5 V to 5.5 V

|V_DD− V_SS| = 2.7 V to 4.5 V

R-TOLERANCE

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

From 0x078 to 0x3FF

From 0x037 to 0x3FF

From 0x028 to 0x3FF

From 0x0BE to 0x3FF

From 0x055 to 0x3FF

From 0x037 to 0x3FF

Table 3. AD5270—50 kΩ and 100 kΩ Resistor Performance Mode Code Range

Resistor Tolerance Per Code

R_AW= 50 kΩ

R_AW= 100 kΩ

R-TOLERANCE

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

From 0x078 to 0x3FF

From 0x055 to 0x3FF

From 0x032 to 0x3FF

From 0x04B to 0x3FF

From 0x032 to 0x3FF

From 0x019 to 0x3FF

Rev. F | Page 4 of 24

Data Sheet

AD5270/AD5271

ELECTRICAL CHARACTERISTICS—AD5271

V_DD= 2.7 V to 5.5 V, V_SS= 0 V; V_DD= 2.5 V to 2.75 V, V_SS= −2.5 V to −2.75 V; −40°C < T_A< +125°C, unless otherwise noted.

Table 4.

Parameter

Symbol

Test Conditions/Comments

Min

Typ ¹Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution

Resistor Integral Nonlinearity^{2, 3}

Resistor Differential Nonlinearity²

Nominal Resistor Tolerance

R-Perf Mode⁴

Normal Mode

Resistance Temperature Coefficient^{5, 6}

Wiper Resistance

8

−1

Bits

LSB

R-INL

R-DNL

+1

See Table 5 and Table 6

−1

V_SS

0.5

15

+1

%

Code = full scale

Code = zero scale

5

ppm/°C

Ω

35

70

RESISTOR TERMINALS

Terminal Voltage Range^{5, 7}

Capacitance⁵A

V_DD

V

pF

f = 1 MHz, measured to GND, code =

half scale

f = 1 MHz, measured to GND, code =

half scale

90

40

Capacitance⁵W

pF

Common-Mode Leakage Current⁵

V_A= V_W

50

nA

DIGITAL INPUTS

Input Logic⁵

High

V_INH

V_INL

I_IN

2.0

V

µA

pF

Low⁵

0.8

Input Current

Input Capacitance⁵

DIGITAL OUTPUT

Output Voltage⁵

High

1

5

C_IN

V_OH

V_OL

R_{PULL_UP}= 2.2 kΩ to V_DD

V_DD− 0.1

V

Low

V_DD= 2.7 V to 5.5 V, V_SS= 0 V

V_DD= 2.5 V to 2.75 V, V_SS= −2.5 V to −2.75 V

0.4

0.6

+1

V

µA

pF

Tristate Leakage Current

Output Capacitance⁵

POWER SUPPLIES

Single-Supply Power Range

Dual-Supply Power Range

Supply Current

−1

5

V_SS= 0 V

2.7

2.5

5.5

2.75

V

Positive

Negative

50-TP Store Current^{5, 8}

I_DD

I_SS

1

µA

−1

Positive

Negative

I_{DD_OTP_STORE}

I_{SS_OTP_STORE}

4

−4

mA

OTP Read Current^{5, 9}

Positive

Negative

Power Dissipation¹⁰

Power Supply Rejection Ratio⁵

I_{DD_OTP_READ}

I_{SS_OTP_READ}

500

5.5

µA

µW

dB

−500

V_IH= V_DDor V_IL= GND

ΔV_DD/ΔV_SS= 5 V 10%

R_AW= 20 kΩ

R_AW= 50 kΩ

R_AW= 100 kΩ

PSRR

−66

−75

−78

−55

−67

−70

Rev. F | Page 5 of 24

AD5270/AD5271

Data Sheet

Parameter

Symbol

Test Conditions/Comments

Min

Typ ¹Max

Unit

DYNAMIC CHARACTERISTICS^{5, 11}

Bandwidth

−3 dB, R_AW= 10 kΩ, Terminal W, see Figure 42

R_AW= 20 kΩ

R_AW= 50 kΩ

kHz

300

120

60

R_AW= 100 kΩ

Total Harmonic Distortion

Resistor Noise Density

V_A= 1 V rms, f = 1 kHz, code = half scale

R_AW= 20 kΩ

R_AW= 50 kΩ

R_AW= 100 kΩ

Code = half scale, T_A= 25°C

R_AW= 20 kΩ

dB

−90

−88

−85

nV/√Hz

13

25

32

R_AW= 50 kΩ

R_AW= 100 kΩ

¹Typical specifications represent average readings at 25°C, V_DD= 5 V, and V_SS= 0 V.

²Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions.

³The maximum current in each code is defined by I_AW= (V_DD− 1)/R_AW

.

⁴The terms resistor performance mode and R-Perf mode are used interchangeably. See the Resistor Performance Mode section.

⁵Guaranteed by design and not subject to production test.

⁶See Figure 25 for more details.

⁷Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

⁸Different from operating current, the supply current for the fuse program lasts approximately 55 ms.

⁹Different from operating current, the supply current for the fuse read lasts approximately 500 ns.

10

P

is calculated from (I_DD× V_DD) + (I_SS× V_SS).

DISS

¹¹All dynamic characteristics use V_DD= +2.5 V, V_SS= −2.5 V.

Table 5. AD5271—20 kΩ Resistor Performance Mode Code Range

Resistor Tolerance per Code

|V_DD− V_SS| = 4.5 V to 5.5 V

|V_DD− V_SS| = 2.7 V to 4.5 V

R-TOLERANCE

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

From 0x1E to 0xFF

From 0x0F to 0xFF

From 0x06 to 0xFF

From 0x32 to 0xFF

From 0x19 to 0xFF

From 0x0E to 0xFF

Table 6. AD5271—50 kΩ and 100 kΩ Resistor Performance Mode Code Range

Resistor Tolerance per Code

R_AW= 50 kΩ

R_AW= 100 kΩ

R-TOLERANCE

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

From 0x1E to 0xFF

From 0x14 to 0xFF

From 0x0A to 0xFF

From 0x14 to 0xFF

From 0x0F to 0xFF

From 0x0A to 0xFF

Rev. F | Page 6 of 24

Data Sheet

AD5270/AD5271

INTERFACE TIMING SPECIFICATIONS

V_DD= 2.5 V to 5.5 V, V_SS= 0 V; V_DD= 2.5 V, V_SS= −2.5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 7.

Parameter

Limit¹

20

10

15

5

Unit

Test Conditions/Comments

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge setup time

Data setup time

2

t₁

ns min

ns max

μs max

ns max

μs max

ms max

t₂

t₃

t₄

t₅

t₆

t₇

5

1

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

SYNC rising edge to next SCLK fall ignored

SCLK rising edge to SDO valid

RDAC register write command execute time

Memory readback execute time

Memory program time

3, 4

t₈

500

15

450

2

600

6

350

0.6

2

t₉

5

t₁₀

t_{RDAC_R-PERF}

t_{RDAC_NORMAL}

t_{MEMORY_READ}

t_{MEMORY_PROGRAM}

t_RESET

Reset 50-TP restore time

Power-on 50-TP restore time

6

t_POWER-UP

¹All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

²Maximum SCLK frequency is 50 MHz.

³Refer to t_{RDAC_R-PER}and t_{RDAC_NORMAL}for RDAC register write operations.

⁴Refer to t

t

_{MEMORY_READ}and _{MEMORY_PROGRAM}for memory commands operations.

⁵R_{PULL_UP}= 2.2 kΩ to V_DDwith a capacitance load of 168 pF.

⁶Maximum time after V_DD− V_SSis equal to 2.5 V.

Shift Register and Timing Diagrams

DB9 (MSB)

DB0 (LSB)

C3

C1

C0

D9

D7

D6

D5

D4

D3

D0

D8

0

C2

D2

D1

DATA BITS

CONTROL BITS

Figure 2. Shift Register Content

t₇

t₄

t₂

t₁

SCLK

SYNC

t₉

t₈

t₃

t₅

D1

t₆

DIN

0

C3

C2

D7

D6

D5

D2

D0

SDO

Figure 3. Write Timing Diagram (CPOL = 0, CPHA = 1)

Rev. F | Page 7 of 24

AD5270/AD5271

Data Sheet

SCLK

t₉

SYNC

DIN

0

C3

D0

0

C3

t₁₀

C3

D1

D0

SDO

X

D1

D0

Figure 4. Read Timing Diagram (CPOL = 0, CPHA = 1)

Rev. F | Page 8 of 24

Data Sheet

AD5270/AD5271

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 8.

Parameter

Rating

V_DDto GND

V_SSto GND

V_DDto V_SS

–0.3 V to +7.0 V

+0.3 V to −7.0 V

7 V

V_A, V_Wto GND

V_SS− 0.3 V, V_DD+ 0.3 V

−0.3 V to V_DD+ 0.3 V

7 V

THERMAL RESISTANCE

Digital Input and Output Voltage to GND

EXT_CAP to V_SS

I_A, I_W

θ_JAis defined by JEDEC specification JESD-51 and the value is

dependent on the test board and test environment.

Continuous

Table 9. Thermal Resistance

R_AW= 20 kΩ

R_AW= 50 kΩ, 100 kΩ

Pulsed¹

Frequency > 10 kHz

Frequency ≤ 10 kHz

Operating Temperature Range⁴

Maximum Junction Temperature

(T_JMaximum)

3 mA

2 mA

1

Package Type

10-Lead LFCSP

10-Lead MSOP

θ_JA

50

θ_JC

3

N/A

Unit

°C/W

MCC²/d³

MCC²/√d³

−40°C to +125°C

150°C

135

¹JEDEC 2S2P test board, still air (0 m/s air flow).

ESD CAUTION

Storage Temperature Range

Reflow Soldering

−65°C to +150°C

Peak Temperature

260°C

Time at Peak Temperature

Package Power Dissipation

20 sec to 40 sec

(T_Jmax − T_A)/θ_JA

¹Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A and W terminals at a given

resistance.

²Maximum continuous current.

³Pulse duty factor.

⁴Includes programming of 50-TP memory.

Rev. F | Page 9 of 24

AD5270/AD5271

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

10

9

V

1

2

3

4

5

SYNC

DD

A

SCLK

DIN

AD5270/

AD5271

(EXPOSED

PAD)

8

W

V

7

SDO

GND

SS

V

1

2

3

4

5

10

9

SYNC

SCLK

DIN

DD

A

AD5270/

AD5271

6

EXT_CAP

8

W

TOP VIEW

V

7

NOTES

SS

EXT_CAP

SDO

GND

(Not to Scale)

1. THE EXPOSED PAD IS LEFT FLOATING

OR IS TIED TO V

6

.

SS

Figure 6. LFCSP Pin Configuration

Figure 5. MSOP Pin Configuration

Table 10. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

3

4

V_DD

A

W

Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.

Terminal A of RDAC. V_SS≤ V_A≤ V_DD.

Wiper Terminal of RDAC. V_SS≤ V_W≤ V_DD.

Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic

capacitors and 10 μF capacitors.

V_SS

5

EXT_CAP

External Capacitor. Connect a 1 μF capacitor between EXT_CAP and V_SS. This capacitor must have a voltage

rating of ≥7 V.

6

7

GND

SDO

Ground Pin, Logic Ground Reference.

Serial Data Output. This pin can be used to clock data from the shift register in daisy-chain mode or in

readback mode. This open-drain output requires an external pull-up resistor even if it is not use.

8

DIN

Serial Data Line. This pin is used in conjunction with the SCLK line to clock data into or out of the 16-bit input

register.

9

SCLK

SYNC

Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 50 MHz.

10

Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the shift register and data is transferred in on the falling edges of the subsequent clocks.

The selected register is updated on the rising edge of SYNC following the 16^thclock cycle. If SYNC is taken

high before the 16^thclock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is

ignored by the RDAC.

EPAD

Exposed Pad

Leave floating or connected to V_SS.

Rev. F | Page 10 of 24

Data Sheet

AD5270/AD5271

TYPICAL PERFORMANCE CHARACTERISTICS

0.8

0.6

0.4

0.2

+125°C

R

= 20kΩ

T

= 25°C

AW

A

20kΩ

50kΩ

100kΩ

+25°C

–40°C

0.6

0.4

0.2

0

–0.2

–0.4

0

–0.2

–0.4

0

256

512

768

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 7. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5270)

Figure 10. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5270)

0.6

0.2

T

= 25°C

A

R

= 20kΩ

AW

0.1

0

0.4

0.2

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.2

–0.4

–0.6

–40°C

256

+25°C

512

+125°C

768

20kΩ

50kΩ

100kΩ

0

256

512

CODE (Decimal)

768

1023

0

128

384

640

896

1023

CODE (Decimal)

Figure 11. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5270)

Figure 8. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5270)

0.6

0.50

+125°C

+25°C

–40°C

20kΩ

50kΩ

100kΩ

T

= 25°C

A

R

= 20kΩ

AW

0.40

0.30

0.20

0.4

0.2

0

–0.2

–0.4

0.10

0

–0.10

0

256

512

768

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 9. R-INL in Normal Mode vs. Code vs. Temperature (AD5270)

Figure 12. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5270)

Rev. F | Page 11 of 24

AD5270/AD5271

Data Sheet

0.15

0.10

+125°C

+25°C

–40°C

T

= 25°C

20kΩ

50kΩ

100kΩ

R

= 20kΩ

A

AW

0.10

0.05

0

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.15

0

256

512

768

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 13. R-DNL in Normal Mode vs. Code vs. Temperature (AD5270)

Figure 16. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5270)

0.15

0.20

+125°C

+25°C

–40°C

T

= 25°C

20kΩ

A

R

= 20kΩ

AW

100kΩ

0.15

0.10

0.05

0.10

0.05

0

–0.05

–0.10

–0.05

–0.10

0

64

128

192

255

0

64

128

192

255

CODE (Decimal)

Figure 17. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5271)

Figure 14. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5271)

0.06

0.15

+125°C

+25°C

–40°C

R

= 20kΩ

T

= 25°C

AW

A

0.04

0.02

0.10

0.05

0

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

0

–0.05

–0.10

–0.15

20kΩ

100kΩ

–0.14

0

64

128

192

255

0

64

128

CODE (Decimal)

192

255

CODE (Decimal)

Figure 18. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5271)

Figure 15. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5271)

Rev. F | Page 12 of 24

Data Sheet

AD5270/AD5271

0.10

0.15

0.10

0.05

0

+125°C

+25°C

–40°C

20kΩ

100kΩ

T

= 25°C

R

= 20kΩ

A

AW

0.08

0.06

0.04

0.02

0

–0.05

–0.10

–0.02

0

64

128

192

255

0

64

128

192

255

CODE (Decimal)

Figure 22. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5271)

Figure 19. R-INL in Normal Mode vs. Code vs. Temperature (AD5271)

0.010

0.03

+125°C

+25°C

–40°C

T

= 25°C

100kΩ

20kΩ

R

= 20kΩ

A

AW

0.008

0.006

0.02

0.01

0

0.004

0.002

0

–0.01

–0.02

–0.002

–0.03

0

64

128

192

255

0

64

128

192

255

CODE (Decimal)

Figure 23. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5271)

Figure 20. R-DNL in Normal Mode vs. Code vs. Temperature (AD5271)

1.0

500

400

I

= 5V

DD

0.8

0.6

0.4

300

200

I

= 3V

DD

100

I

= 3V

0

SS

–100

–200

–300

–400

–500

= 5V

SS

0.2

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VOLTAGE (V)

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100 110

TEMPERATURE (°C)

Figure 24. Supply Current I_DDvs. Digital Input Voltage

Figure 21. Supply Current (I_DD, I_SS) vs. Temperature

Rev. F | Page 13 of 24

AD5270/AD5271

Data Sheet

50

45

40

35

30

25

20

15

10

5

7

6

5

4

3

2

V

/V = 5V/0V

DD SS

V

/V = 5V/0V

DD SS

20kΩ

50kΩ

100kΩ

20kΩ

50kΩ

100kΩ

1

0

256

64

512

128

768

192

1023 AD5270

255 AD5271

0

256

64

512

128

768

192

1023 AD5270

255 AD5271

CODE (Decimal)

Figure 28. Theoretical Maximum Current vs. Code

Figure 25. Tempco ΔR_WA/ΔT vs. Code

0

AD5270 (AD5271)

0x200 (0x80)

0x100 (0x40)

0x080 (0x20)

0x040 (0x10)

0x020 (0x08)

0x010 (0x04)

0x008 (0x02)

0x004 (0x01)

AD5270 (AD5271)

0x200 (0x80)

–10

–20

–10 0x100 (0x40)

0x080 (0x20)

–20

0x040 (0x10)

–30

–40

–50

–60

–70

0x020 (0x08)

–30

0x010 (0x04)

0x008 (0x02)

–40

0x004 (0x01)

0x002

0x001

0x002

–50

0x001

–60

1k

10k

100k

1M

10M

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 26. 20 kΩ Gain vs. Code vs. Frequency

Figure 29. 100 kΩ Gain vs. Code vs. Frequency

0

–10

–20

–30

0

V

/V = 5V/0V

DD SS

AD5270 (AD5271)

0x200 (0x80)

CODE = HALF SCALE

–10

0x100 (0x40)

0x080 (0x20)

0x040 (0x10)

0x020 (0x08)

0x010 (0x04)

50kΩ

100kΩ

20kΩ

–20

–30

–40

–50

–60

–70

–80

–90

0x008 (0x02)

0x004 (0x01)

–40

–50

–60

0x002

0x001

100

1k

10k

FREQUENCY (Hz)

100k

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 27. 50 kΩ Gain vs. Code vs. Frequency

Figure 30. PSRR vs. Frequency

Rev. F | Page 14 of 24

Data Sheet

AD5270/AD5271

0

–10

–20

20kΩ

50kΩ

100kΩ

V

/V = 5V/0V

DD SS

V

/V = 5V/0V

DD SS

CODE = HALF SCALE

NOISE BW = 22kHz

V

CODE = HALF SCALE

f_IN= 1kHz

= 1V rms

NOISE BW = 22kHz

–20

–40

–60

IN

20kΩ

50kΩ

100kΩ

–30

–40

–50

–60

–70

–80

–90

–100

0.001

100

1k

10k

0.01

0.1

)

1

100k

VOLTAGE (V

FREQUENCY (Hz)

RMS

Figure 31. THD + N vs. Frequency

Figure 34. THD + N vs. Amplitude

0.03

0.02

0.01

0

0.0010

0.0005

0

V

/V = 5V/0V

DD SS

= 200µA

20kΩ

50kΩ

100kΩ

I

AW

CODE = HALF SCALE

–0.01

–0.0005

–0.0010

–0.0015

–0.02

–0.03

–0.04

–1

4

9

14

19

–10

0

10

20

30

40

50

60

TIME (µs)

Figure 32. Maximum Glitch Energy

Figure 35. Digital Feedthrough

45

40

70

11.25

10.00

8.75

15.5

T

= 25°C

A

V

/V = 5V/0V

DD SS

20kΩ

50kΩ

100kΩ

20kΩ

50kΩ

100kΩ

60

50

40

30

20

10

0

15.0

12.5

10.0

7.5

5.0

2.5

0

35

30

7.50

6.25

25

20

5.00

3.75

2.50

15

10

1.25

0

5

0

2.7

3.2

3.7

4.2

(V)

4.7

5.2

–40

–20

0

20

40

60

80

100

120

V

TEMPERATURE (°C)

DD

Figure 36. Maximum Code Loss vs. Temperature

Figure 33. Maximum Code Loss vs. Voltage

Rev. F | Page 15 of 24

AD5270/AD5271

Data Sheet

8

0.006

0.005

0.004

0.003

0.002

0.001

0

V

/V = 5V/0V

= 10µA

DD SS

I

AW

CODE = HALF SCALE

7

6

5

4

–0.001

–0.002

0

100 200 300 400 500 600 700 800 900 1000

OPERATION AT 150°C (Hours)

0.07

0.09

0.11

0.13

0.15

0.17

TIME (Seconds)

Figure 37. V_{EXT_CAP}Waveform While Writing Fuse

Figure 38. Long-Term Drift Accelerated Average by Burn-In

Rev. F | Page 16 of 24

Data Sheet

AD5270/AD5271

TEST CIRCUITS

Figure 39 to Figure 43 define the test conditions used in the Specifications section.

DUT

I

W

1GΩ

W

A

V

MS

Figure 42. Gain vs. Frequency

Figure 39. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT

GND

VMS

R

=

WA

I

W

CM

+2.75V

–2.75V

W

CODE = 0x00

DUT

A

RWA

I

W

R

W

2

A

W

GND

V

NC

GND

–2.75V

MS

NC = NO CONNECT

+2.75V

Figure 40. Wiper Resistance

Figure 43. Common Leakage Current

V+ = V ±10%

DD

V

MS

PSRR (dB) = 20 LOG

DD

ΔV

%

MS

DD

I

W

PSS (%/%) =

V

DD

W

V+

A

V

MS

Figure 41. Power Supply Sensitivity (PSS, PSRR)

Rev. F | Page 17 of 24

AD5270/AD5271

Data Sheet

THEORY OF OPERATION

The AD5270 and AD5271 are designed to operate as true

variable resistors for analog signals within the terminal voltage

range of V_SS< V_TERM< V_DD. The RDAC register contents deter-

mine the resistor wiper position. The RDAC register acts as a

scratchpad register, which allows unlimited changes of resistance

settings. The RDAC register can be programmed with any position

setting using the SPI interface. When a desirable wiper position

is found, this value can be stored in a 50-TP memory register.

Thereafter, the wiper position is always restored to that position

for subsequent power-up. The storing of 50-TP data takes approx-

imately 350 ms; during this time, the AD5270/AD5271 lock to

prevent any changes from taking place.

RDAC REGISTER

The RDAC register directly controls the position of the digital

rheostat wiper. For example, when the RDAC register is loaded

with all zeros, the wiper is connected to Terminal A of the variable

resistor. The RDAC register is a standard logic register and

there is no restriction on the number of changes allowed. The

basic mode of setting the variable resistor wiper position

(programming the RDAC register) is accomplished by loading

the serial data input register with Command 1 (see Table 11) and

with the desired wiper position data.

50-TP MEMORY BLOCK

The AD5270/AD5271 contain an array of 50-TP programmable

memory registers, which allow the wiper position to be pro-

grammed up to 50 times. Table 13 shows the memory map.

When the desired wiper position is determined, the user can

load the serial data input register with Command 3 (see Table 11)

which stores the wiper position data in a 50-TP memory

register. The first address to be programmed is Location 0x01

(see Table 13); the AD5270/AD5271 increments the 50-TP

memory address for each subsequent program until the memory

is full. Programming data to 50-TP consumes approximately

4 mA for 55 ms, and takes approximately 350 ms to complete,

during which time the shift register locks to prevent any changes

from occurring. Bit C3 of the control register can be polled to

verify that the fuse program command was completed properly.

No change in supply voltage is required to program the 50-TP

memory; however, a 1 μF capacitor on the EXT_CAP pin is

required (see Figure 46). Prior to 50-TP activation, the AD5270

and the AD5271 preset to midscale on power up.

The AD5270/AD5271 also feature a patented 1% end-to-end

resistor tolerance. This simplifies precision, rheostat mode, and

open-loop applications where knowledge of absolute resistance

is critical.

SERIAL DATA INTERFACE

SYNC

The AD5270/AD5271 contain a serial interface (

, SCLK,

DIN , and SDO), which is compatible with SPI interface standards,

as well as most DSPs. This device allows writing of data via the

serial interface to every register.

SHIFT REGISTER

For the AD5270/AD5271, the shift register is 16 bits wide, as

shown in Figure 2. The 16-bit word consists of two unused bits,

which should be set to zero, followed by four control bits and

10 RDAC data bits (note that for the AD5271 only, the lower

two RDAC data bits are don’t care if the RDAC register is read

from or written to). Data is loaded MSB first (Bit 15). The four

control bits determine the function of the software command as

listed in Table 11. Figure 3 shows a timing diagram of a typical

AD5270/AD5271 write sequence.

WRITE PROTECTION

At power-up, the serial data input register write commands for

both the RDAC register and the 50-TP memory registers are

disabled. The RDAC write protect bit, C1, of the control register

(see Table 13 and Table 14) is set to 0 by default. This disables

any change of the RDAC register content regardless of the

software commands, except that the RDAC register can be

refreshed from the 50-TP memory using the software reset,

Command 4. To enable programming of the RDAC register, the

write protect bit (Bit C1), of the control register must first be

programmed by loading the serial data input register with

Command 7. To enable programming of the 50-TP memory,

the program enable bit (Bit C0) of the control register, which is

set to 0 by default, must first be set to 1.

SYNC

The write sequence begins by bringing the

line low. The

SYNC

pin must be held low until the complete data-word is

SYNC

loaded from the DIN pin. When

returns high, the serial

data-word is decoded according to the instructions in Table 11.

The command bits (Cx) control the operation of the digital

potentiometer. The data bits (Dx) are the values that are loaded

into the decoded register. The AD5270/AD5271 have an internal

counter that counts a multiple of 16 bits (a frame) for proper

operation. For example, AD5270/AD5271 each works with a

32-bit word but do not work properly with a 31-bit or 33-bit

word. The AD5270/AD5271 do not require a continuous SCLK

SYNC

when

digital input buffers, operate all serial interface pins close to the

_DDsupply rails.

is high. To minimize power consumption in the

V

Rev. F | Page 18 of 24

Data Sheet

AD5270/AD5271

Data from the selected memory location is clocked out of the

SDO pin during the next SPI operation. A binary encoded

version address of the most recently programmed wiper memory

location can be read back using Command 6 (see Table 11). This

can be used to monitor the spare memory status of the 50-TP

memory block.

RDAC AND 50-TP READ OPERATION

A serial data output SDO pin is available for readback of the

internal RDAC register or 50-TP memory contents. The

contents of the RDAC register can be read back through SDO

by using Command 2 (see Table 11). Data from the RDAC

register is clocked out of the SDO pin during the last 10 clocks

of the next SPI operation.

Table 12 provides a sample listing for the sequence of serial data

input (DIN) words with the serial data output appearing at the

SDO pin in hexadecimal format for a write and read to both the

RDAC register and the 50-TP memory (Memory Location 20).

It is possible to read back the contents of any of the 50-TP

memory registers through SDO by using Command 5. The

lower six LSB bits, D0 to D5 of the data byte, select which

memory location is to be read back, as shown in Table 13.

Table 11. Command Operation Truth Table

Command[DB13:DB10]

Data[DB9:DB0]¹

D9 D8 D7 D6 D5 D4 D3 D2

Command

Number

C3

0

C2

0

C1

0

C0

0

D1 D0 Operation

NOP: do nothing.

0

1

X

0

1

D9 D8 D7 D6 D5 D4 D3 D2

D1²D0²Write contents of serial register

data to RDAC.

2

0

1

0

1

0

1

0

1

0

1

X

Read contents of RDAC wiper

register.

3

X

Store wiper setting: store RDAC

setting to 50-T P.

4

X

Software reset: refresh RDAC with

last 50-TP memory stored value.

5³

6

D5 D4 D3 D2

D1

X

D0 Read contents of 50-TP from SDO

output in the next frame.

X

Read address of last 50-TP

programmed memory location.

7⁴

D2

D1

D0

Write contents of serial register

data to control register.

8

9

1

0

1

X

Read contents of control register.

Software shutdown.

D0

D0 = 0; normal mode.

D0 = 1; device placed in shutdown

mode.

¹X is don’t care.

²AD5271 = don’t care.

³See Table 15 for 50-TP memory map.

⁴See Table 14 for bit details.

Rev. F | Page 19 of 24

AD5270/AD5271

Data Sheet

SHUT-DOWN MODE

RESISTOR PERFORMANCE MODE

The AD5270/AD5271 can be shut down by executing the

software shutdown command, Command 9 (see Table 11), and

setting the LSB to 1. This feature places the RDAC in a zero-

power-consumption state where Terminal Ax is open circuited

and the Wiper Terminal Wx remains connected. It is possible to

execute any command from Table 11 while the AD5270/AD5271

are in shutdown mode. The parts can be taken out of shutdown

mode by executing Command 9 and setting the LSB to 0 or by a

software reset, Command 4 (see Table 11).

This mode activates a new, patented 1% end-to-end resistor

tolerance that ensures a 1% resistor tolerance error on each

code, that is, code = half scale, R_WA= 10 kΩ 100 Ω. See Table 2,

Table 3, Table 5, and Table 6 to verify which codes achieve 1%

resistor tolerance. The resistor performance mode is activated by

programming Bit C2 of the control register.

RESET

The AD5270/AD5271 can be reset through software by executing

Command 4 (see Table 11). The reset command loads the

RDAC register with the contents of the most recently programmed

50-TP memory location. The RDAC register loads with

midscale if no 50-TP memory location has been previously

programmed.

Table 12. Write and Read to RDAC and 50-TP Memory

DIN

SDO¹

Action

0x1C03 0xXXXX Enable update of the wiper position and the 50-TP memory contents through the digital interface.

0x0500 0x1C03 Write 0x100 to the RDAC register; wiper moves to ¼ full-scale position.

0x0800 0x0500 Prepares data read from RDAC register.

0x0C00 0x100

Stores RDAC register content into the 50-TP memory. A 16-bit word appears out of SDO, where the last 10-bits contain

the contents of the RDAC register (0x100).

0x1800 0x0C00 Prepares data read of last programmed 50-TP memory monitor location.

0x0000 0xXX19 NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs last six bits contain the binary address of the last

programmed 50-TP memory location, for example, 0x19 (see Table 13).

0x1419 0x0000 Prepares data read from Memory Location 0x19.

0x2000 0x0100 Prepares data read from the control register. Sends a 16-bit word out of SDO, where the last 10-bits contain the

contents of Memory Location 0x19.

0x0000 0xXXXX NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register.

If Bit C3 = 1, the fuse program command successful.

¹X is don’t care.

Table 13. Control Register Bit Map

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

C3

C2

C1

C0

Table 14. Control Register Bit Description

Bit Name

Description

C0

50-TP program enable

0 = 50-TP program disabled (default)

1 = enable device for 50-TP program

RDAC register write protect

0 = wiper position frozen to value in 50-TP memory (default)¹

1 = allow update of wiper position through digital interface

R-performance enable

0 = RDAC resistor tolerance calibration enabled (default)

1 = RDAC resistor tolerance calibration disabled

50-TP memory program success bit

C1

C2

C3

0 = fuse program command unsuccessful (default)

1 = fuse program command successful

¹Wiper position frozen to the last value programmed in the 50-TP memory. The wiper is frozen to midscale if the 50-TP memory has not been previously programmed.

Rev. F | Page 20 of 24

Data Sheet

AD5270/AD5271

Table 15. Memory Map

Data Byte[DB9:DB8]¹

Command Number

D9

X

D8

X

D7

X

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

Register Contents

5

Reserved

X

…

X

…

X

…

X

0

…

0

…

0

1

0

…

0

1

0

…

1

0

1

0

1

…

0

1

0

1

0

…

1

0

1

0

1

0

1

0

…

0

1st programmed wiper location (0x01)

2nd programmed wiper location (0x02)

3rd programmed wiper location (0x03)

4th programmed wiper location (0x04)

…

10th programmed wiper location (0xA)

20th programmed wiper location (0x14)

30th programmed wiper location (0x1E)

40th programmed wiper location (0x28)

50th programmed wiper location (0x32)

X

0

1

0

1

0

¹X is don’t care.

V

DD

SDO PIN AND DAISY-CHAIN OPERATION

R

2.2kΩ

AD5270/

AD5271

U1

AD5270/

AD5271

U2

SDO

P

The serial data output pin (SDO) serves two purposes: it can be

used to read the contents of the wiper setting and 50-TP values

using Command 2 and Command 5, respectively (see Table 11),

or the SDO pin can be used in daisy-chain mode. Data is clocked

out of SDO on the rising edge of SCLK. The SDO pin contains

an open-drain N-channel FET that requires a pull-up resistor.

To place the pin in high impedance and mini-mize the power

dissipation when the pin is used, the 0x8001 data word followed

by Command 0 should be sent to the part. Table 16 provides a

sample listing for the sequence of the serial data input (DIN).

Daisy chaining minimizes the number of port pins required

from the controlling IC. As shown in Figure 44, the user must

tie the SDO pin of one package to the DIN pin of the next

package. The user may need to increase the clock period because

the pull-up resistor and the capacitive loading at the SDO-to-

DIN interface may require additional time delay between

subsequent devices. When two AD5270/AD5271 devices are

daisy-chained, 32 bits of data are required. The first 16 bits go to

U2, and the second 16 bits go to U1.

MOSI

SS

DIN

SDO

µC

SCLK

SYNC

SCLK

SYNC SCLK

Figure 44. Daisy-Chain Configuration Using SDO

RDAC ARCHITECTURE

To achieve optimum performance, Analog Devices has patented

the RDAC segmentation architecture for all the digital potentio-

meters. In particular, the AD5270/AD5271 employ a three-stage

segmentation approach as shown in Figure 45.The AD5270/

AD5271 wiper switch is designed with the transmission gate

CMOS topology.

A

R

L

Table 16. Minimize Power Dissipation at the SDO Pin

R

M

DIN

SDO¹

Action

0xXXXX 0xXXXX

0x8001 0xXXXX

Last user command sent to the digipot.

Prepares the SDO pin to be placed in

high impedance mode.

S

W

8-/10-BIT

ADDRESS

DECODER

R

W

0x0000 High

The SDO pin is placed in high

W

Impedance impedance.

R

W

¹X is don’t care.

SYNC

Keep the

pin low until all 32 bits are clocked to their

Figure 45. Simplified RDAC Circuit

SYNC

respective serial registers. The

complete the operation.

pin is then pulled high to

Rev. F | Page 21 of 24

AD5270/AD5271

Data Sheet

PROGRAMMING THE VARIABLE RESISTOR

TERMINAL VOLTAGE OPERATING RANGE

Rheostat Operation—1% Resistor Tolerance

The positive V_DDand negative V_SSpower supplies of the

AD5270/AD5271 define the boundary conditions for proper

2-terminal digital resistor operation. Supply signals present on

Terminal A and Terminal W that exceed V_DDor V_SSare clamped

by the internal forward-biased diodes, see Figure 47.

The nominal resistance between Terminal W and Terminal A, R_WA,

is 20 kΩ, 50 kΩ, or 100 kΩ and has 1024-/256-tap points accessed

by the wiper terminal. The 10-/8-bit data in the RDAC latch is

decoded to select one of the 1024 or 256 possible wiper settings.

The AD5270 and AD5271 contain an internal 1ꢀ resistor

tolerance calibration feature that can be disabled or enabled,

enabled by default, or by programming Bit C2 of the control

register (see Table 13 and Table 14).

V

DD

A

The digitally programmed output resistance between the W

terminal and the A terminal, R_WA, is calibrated to give a

maximum of 1ꢀ absolute resistance error over both the full

supply and temperature ranges. As a result, the general

equations for determining the digitally programmed output

resistance between the W terminal and the A terminal are the

following:

W

V

SS

Figure 47. Maximum Terminal Voltages Set by V_DDand V_SS

For the AD5270

The ground pins of the AD5270/AD5271 devices are primarily

used as digital ground references. To minimize the digital ground

bounce, join the AD5270/AD5271 ground terminal remotely

to the common ground. The digital input control signals to the

AD5270/AD5271 must be referenced to the device ground pin

(GND), and must satisfy the logic level defined in the

D

R_WA(D) 

R_WA

(1)

(2)

1024

For the AD5271

D

R_WA(D) 

R_WA

256

Specifications section. An internal level shift circuit ensures that

the common-mode voltage range of the three terminals extends

from V_SSto V_DD, regardless of the digital input level.

where:

D is the decimal equivalent of the binary code loaded in the

10-/8-bit RDAC register.

R

_WAis the end-to-end resistance.

POWER-UP SEQUENCE

Because there are diodes to limit the voltage compliance at

Terminal A and Terminal W (see Figure 47), it is important to

power V_DD/V_SSfirst before applying any voltage to Terminal A

and Terminal W; otherwise, the diode is forward-biased such

that V_DD/V_SSare powered unintentionally. The ideal power-up

sequence is V_SS, GND, V_DD, digital inputs, V_A, and V_W. The

order of powering V_A, V_W, and the digital inputs is not

important as long as they are powered after V_DD/V_SS.

In the zero-scale condition, a finite total wiper resistance of

120 Ω is present. Regardless of which setting the part is oper-

ating in, take care to limit the current between Terminal A to

Terminal W to the maximum continuous current of 3 mA or

a pulse current specified in Table 8. Otherwise, degradation or

possible destruction of the internal switch contact can occur.

EXT_CAP CAPACITOR

A 1 μF capacitor to V_SSmust be connected to the EXT_CAP

pin, as shown in Figure 46, on power-up and throughout the

operation of the AD5270/AD5271.

As soon as V_DDis powered, the power-on preset activates which

first sets the RDAC to midscale and then restores the last pro-

grammed 50-TP value to the RDAC register.

AD5270/

AD5271

50_OTP

MEMORY

EXT_CAP

BLOCK

C1

1µF

V

SS

V

SS

Figure 46. EXT_CAP Hardware Setup

Rev. F | Page 22 of 24

Data Sheet

AD5270/AD5271

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

1

6

5

5.15

4.90

4.65

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.70

0.55

0.40

0.15

0.05

0.23

0.13

6°

0°

0.30

0.15

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 48. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

2.48

2.38

2.23

3.10

3.00 SQ

2.90

0.50 BSC

10

6

PIN 1 INDEX

AREA

EXPOSED

PAD

1.74

1.64

1.49

0.50

0.40

0.30

0.20 MIN

1

5

BOTTOM VIEW

TOP VIEW

PIN 1

INDICATOR

(R 0.15)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.30

0.25

0.20

0.20 REF

Figure 49. 10-Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

Rev. F | Page 23 of 24

AD5270/AD5271

Data Sheet

ORDERING GUIDE

Model¹

R_AW(kΩ)

20

50

100

20

100

20

Resolution

1,024

256

Temperature Range

−40°C to +125°C

Package Description

10-Lead MSOP

10-Lead LFCSP_WD

10-Lead MSOP

10-Lead LFCSP_WD

Evaluation Board

Package Option

Branding

D1X

DDP

D1W

DDY

DDX

DE0

AD5270BRMZ-20

AD5270BRMZ-20-RL7

AD5270BRMZ-50

RM-10

CP-10-9

RM-10

CP-10-9

AD5270BRMZ-50-RL7

AD5270BRMZ-100

AD5270BRMZ-100-RL7

AD5270BCPZ-20-RL7

AD5270BCPZ-100-RL7

AD5271BRMZ-20

AD5271BRMZ-20-RL7

AD5271BRMZ-100

AD5271BRMZ-100-RL7

AD5271BCPZ-20-RL7

AD5271BCPZ-100-RL7

EVAL-AD5270SDZ

20

256

DE0

100

20

DDZ

DE2

100

256

DE1

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D08077-0-3/13(F)

Rev. F | Page 24 of 24


型号：	AD5270BCPZ-20-RL7
厂家：	Rochester Electronics
描述：	20K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO10, 3 X 3 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, LFCSP-10 光电二极管转换器电阻器
文件：	总25页 (文件大小：1854K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5270BCPZ-20-RL7 [ROCHESTER]

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AD5270BRMZ-20-RL7

AD5270BRMZ-20-U1

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