AD5270BRMZ100-U1 [ADI]
IC,DIGITAL POTENTIOMETER,TSSOP,10PIN,PLASTIC;
| 型号： | AD5270BRMZ100-U1 |
| 厂家： | 
ADI |
| 描述： | IC,DIGITAL POTENTIOMETER,TSSOP,10PIN,PLASTIC 光电二极管 转换器 |
| 文件： | 总17页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Channel, 1% Resistor tolerance,
1024/256-Position Digital Variable Resistor
Preliminary Technical Data
AD5270/AD5271
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Single-channel, 1,024/256-position resolution
20 kΩ, 50 kΩ and 100 kΩ nominal resistance
Calibrated 1% Nominal Resistor Tolerance
Multiple-time programmable set-and-forget resistance
setting allows 50 time permanent programming
Rheostat mode temperature coefficient: 35 ppm/°C
2.7V to 5.5V single-supply operation
2.5V to 2.75V dual-supply operation for AC or Bipolar
Operations
SPI compatible interface
Wiper setting readback
Power-on refreshed from 50-TP memory
Thin LFCSP(SON)-10 (3 mm x 3 mm x 0.8 mm) package
Compact MSOP-10 (3 mm × 4.9 mm x 1.1mm) package
APPLICATIONS
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage to current conversion
Programmable filters, delays, time constants
Programmable power supply
Figure 1. Block Diagram
Sensor calibration
the SPI compatible digital interface. Unlimited adjustments are
allowed before programming the resistance value into the 50-
TP (Fifty Time Programmable) memory. The AD5270/1 do not
require any external voltage supply to facilitate fuse blow and
there are 50 opportunities for permanent programming. During
50-TP activation, a permanent blow fuse command freezes the
wiper position (analogous to placing epoxy on a mechanical
trimmer).
GENERAL DESCRIPTION
The AD5270/1 are single-channel, 1024/256-positions digitally
controlled resistors1 with less than 1% end-to-end Resistor
Tolerance error and 50-Time Programmable Memory. The
AD5270/1 perform the same electronic adjustment function as
a mechanical rheostat with enhanced resolution, solid state
reliability, and superior low temperature coefficient perform-
ance.
The AD5270/1 offer guaranteed industry leading low resistor
tolerance errors of 1% with a nominal temperature coefficient
of 35 ppm/ºC. The low resistor tolerance feature simplifies
open-loop applications as well as precision calibration and
tolerance matching applications
The AD5270 and AD5271 are available in a thin 3mmX3mm
LFCSP package and in a compact 10ld MSOP package. The
parts are guaranteed to operate over the extended industrial
temperature range of −40°C to +105°C.
1 The terms programmable resistor and RDAC are used interchangeably.
The AD5270/1 device wiper settings are controllable through
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2009 Analog Devices, Inc. All rights reserved.
AD5270/AD5271
Preliminary Technical Data
TABLE OF CONTENTS
Rev.PrA | Page 2 of 17
Preliminary Technical Data
SPECIFICATIONS
AD5270/AD5271
ELECTRICAL CHARACTERISTICS – 50KΩ AND 100KΩ VERSIONS
VDD = 2.7V to 5.5V, VSS = 0V; VDD = 2.5V to 2.75V, VSS = -2.5V to -2.75V; −40°C < TA < +105°C, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS— RHEOSTAT MODE
Resolution
Bits
AD5270
AD5271
Resistor Integral Nonlinearity2
10
8
LSB
LSB
AD5270
VDD = 3.0V to 5.5V
VDD = 2.7V to 3.0V
−1
−1
-1
+1
+1.5
+1
AD5271
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
−1
−1
+1
+1
LSB
%
ppm/°C
Ω
0.5
35
35
70
RESISTOR TERMINALS
Terminal Voltage Range4
Capacitance5 A
VSS
2.0
-1
VDD
V
pF
f = 1 MHz, measured to GND,
Code = half-scale
f = 1 MHz, measured to GND,
Code = half-scale
165
60
Capacitance5 W
pF
Common-Mode Leakage Current5
DIGITAL INPUTS
VINH, Input Logic High
VINL, Input Logic Low
VA = VW
4
nA
V
V
μA
pF
0.8
IIN, Input Current
1
5
CIN,Input Capacitance5
DIGITAL OUTPUTS(OPEN DRAIN)
VOL, Output Low Voltage
ISINK = 3mA
ISINK = 6mA
0.4
0.6
1
V
V
μA
pF
Three state Leakage Current
Three state Output Capacitance5
POWER SUPPLIES
2
Single-Supply Power Range
Dual-Supply Power Range
IDD, Positive Supply Current
ISS, Negative Supply Current
IDD_OTP_STORE, OTP Store Current5,6
ISS_OTP_STORE, OTP Store Current5,6
IDD_OTP_READ, OTP Read Current5,7
ISS_OTP_READ, OTP Read Current5,7
Power Dissipation8
VSS = 0 V
2.7
2.5
5.5
2.75
1
−1
4
V
V
μA
μA
mA
mA
μA
μA
mW
dB
-4
500
-500
11
VIH = VDD or VIL = GND
∆VDD/∆VSS
Power Supply Rejection Ratio5
DYNAMIC CHARACTERISTICS5, 9
Bandwidth
=
5 V 10%
-90
-60
−3 dB,
kHz
R
AW = 50 kΩ
20
10
RAW = 100 kΩ
Rev. PrA | Page 3 of 17
AD5270/AD5271
Preliminary Technical Data
Parameter
Conditions
Min
Typ1
Max
Unit
Total Harmonic Distortion
VA = 1 V rms, f = 1 kHz
RAW = 50 kΩ
-60
-57
9.2
dB
RAW = 100 kΩ
RWB = 5 kΩ, TA = 25°C,
Resistor Noise Density
Hz
nV/√
1 Typicals represent average readings at 25°C,VDD = 5 V and VSS = 0 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions.
3
1% resistor tolerance code range per end-to-end resistor option;
AD5270: RAB = 50KΩ: 50 to 1,023 for | VDD - VSS | = 4.5V to 5.5V, 85 to 1,023 for | VDD - VSS | = 3V to 4.5V and TBD to 1,023 for | VDD - VSS | = 2.7V to 2.9V;
RAB = 100kΩ: 20 to 1,023 for | VDD - VSS | = 4.5V to 5.5V, 75 to 1,023 for | VDD - VSS | = 3V to 4.5V and TBD to 1,023 for | VDD - VSS | = 2.7V to 2.9V.
AD5271: RAB = 50KΩ: 12 to 255 for | VDD - VSS | = 4.5V to 5.5V, 22 to 255 for | VDD - VSS | = 3V to 4.5V and TBD to 255 for | VDD - VSS | = 2.7V to 2.9V;
RAB = 100KΩ: 5 to 255 for | VDD - VSS | = 4.5V to 5.5V, 19 to 255 for | VDD - VSS | = 3V to 4.5V and TBD to 255 for | VDD - VSS | = 2.7V to 2.9V.
4 Resistor Terminals A and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.
5 Guaranteed by design and not subject to production test.
6 Different from operating current; supply current for fuse program lasts approximately TBDμs.
7 Different from operating current; supply current for fuse read lasts approximately TBDμs..
8 PDISS is calculated from (IDD × VDD) + (ISS × VSS).
9 All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.
Rev. PrA | Page 4 of 17
Preliminary Technical Data
AD5270/AD5271
ELECTRICAL CHARACTERISTICS – 20KΩ
VDD = 2.7V to 5.5V, VSS = 0V; VDD = 2.5V to 2.75V, VSS = -2.5V to -2.75V; −40°C < TA < +105°C, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS— RHEOSTAT MODE
Resolution
Bits
AD5270
AD5271
Resistor Integral Nonlinearity2
10
8
AD5270
VDD = 4.5V to 5.5V
VDD = 3.0V to 4.4V
VDD = 2.7V to 3.0V
−1
−1.5
+1
+2
LSB
LSB
LSB
1.75
AD5271
−1
−1
−1
+1
+1
+1
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
LSB
%
ppm/°C
Ω
0.5
35
35
70
RESISTOR TERMINALS
Terminal Voltage Range4
Capacitance5 A
VSS
2.0
-1
VDD
V
pF
f = 1 MHz, measured to GND,
Code = half-scale
f = 1 MHz, measured to GND,
Code = half-scale
165
60
Capacitance5 W
pF
Common-Mode Leakage Current5
DIGITAL INPUTS
VINH, Input Logic High
VINL, Input Logic Low
VA = VW
4
nA
V
V
μA
pF
0.8
IIN, Input Current
1
5
CIN,Input Capacitance5
DIGITAL OUTPUTS(OPEN DRAIN)
VOL, Output Low Voltage
ISINK = 3mA
ISINK = 6mA
0.4
0.6
1
V
V
μA
pF
Three state Leakage Current
Three state Output Capacitance5
POWER SUPPLIES
2
Single-Supply Power Range
Dual-Supply Power Range
IDD, Positive Supply Current
ISS, Negative Supply Current
IDD_OTP_STORE, OTP Store Current5,6
ISS_OTP_STORE, OTP Store Current5,6
IDD_OTP_READ, OTP Read Current5,7
ISS_OTP_READ, OTP Read Current5,7
Power Dissipation8
VSS = 0 V
2.7
2.5
5.5
2.75
1
-1
4
V
V
μA
μA
mA
mA
μA
μA
mW
dB
-4
500
-500
16.5
-50
VIH = VDD or VIL = GND
∆VDD/∆VSS
Power Supply Rejection Ratio5
DYNAMIC CHARACTERISTICS5, 9
Bandwidth
=
5 V 10%
-80
50
−3 dB,
R
AW = 20 kΩ
kHz
dB
Total Harmonic Distortion
Resistor Noise Density
VA = 1 V rms, f = 1 kHz
RAW = 20 kΩ
RWB = 5 kΩ, TA = 25°C,
-70
9.2
Hz
nV/√
Rev. PrA | Page 5 of 17
AD5270/AD5271
Preliminary Technical Data
1 Typicals represent average readings at 25°C,VDD = 5 V and VSS = 0 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions.
3
1% resistor tolerance code range per end-to-end resistor option;
AD5270: RAB = 20KΩ: 18 to 1,023 for | VDD - VSS | = 4.5V to 5.5V, 270 to 1,023 for | VDD - VSS | = 3V to 4.5V and TBD to 1,023 for | VDD - VSS | = 2.7V to 2.9V;
AD5271: RAB = 20KΩ: 70 to 255 for | VDD - VSS | = 4.5V to 5.5V, 68 to 255 for | VDD - VSS | = 3V to 4.5V and TBD to 255 for | VDD - VSS | = 2.7V to 2.9V;
4 Resistor Terminals A and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.
5 Guaranteed by design and not subject to production test.
6 Different from operating current; supply current for fuse program lasts approximately TBDμs.
7 Different from operating current; supply current for fuse read lasts approximately TBDμs..
8 PDISS is calculated from (IDD × VDD) + (ISS × VSS).
9 All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.
Rev. PrA | Page 6 of 17
Preliminary Technical Data
AD5270/AD5271
INTERFACE TIMING SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = -2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Unit
ns min
Test Conditions/Comments
Limit1
20
2
t1
SCLK cycle time
t2
t3
10
10
ns min
ns min
ns min
ns min
ns min
ns min
μs min
ns min
ns max
ns min
ms max
ms max
ms max
SCLK high time
SCLK low time
t4
15
SYNC to SCLK falling edge setup time
Data setup time
t5
5
t6
5
Data hold time
t7
0
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
SCLK rising edge to SDO valid
SCLK to SDO Data hold time
Power-on OTP restore time
Memory Program Time
Memory Read Time
t8
TBD
13
t9
3
3
t10
t11
125
TBD(40)
18
tOTP
tMEMORY_PROGRAM
tMEMORY_READ
TBD
TBD
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 50 MHz
3 RPULL_UP = 2.2kΩ to VDD
Figure 2. AD5270 Input Register Content
Figure 3. AD5271 Input Register Content
Rev. PrA | Page 7 of 17
AD5270/AD5271
Preliminary Technical Data
TIMING DIAGRAMS
Figure 4. Write Timing Diagram
Figure 5. Read Timing Diagram
Rev. PrA | Page 8 of 17
Preliminary Technical Data
AD5270/AD5271
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
VDD to GND
VSS to GND
VDD to VSS
Rating
–0.3 V to +7.0 V
+0.3 V, −7.0 V
7 V
VSS−0.3 V to VDD+0.3
V
VA, VW to GND
IA, IW
Pulsed1
TBD mA
Continuous
20KΩ End-to-End resistance
50KΩ and 100 KΩ End-to-End resistance
Digital Input and Output Voltage to GND
Operating Temperature Range2
Maximum Junction Temperature (TJ max)
Storage Temperature
3 mA
2 mA
-0.3 V to VDD +0.3 V
−40°C to +125°C
150°C
−65°C to +150°C
Reflow Soldering
Peak Temperature
260°C
Time at peak temperature
20 sec to 40 sec
Thermal Resistance Junction-to-Ambient3
θJA, MSOP – 10
216°C/W
θJA, LFCSP - 10
41°C/W
Package Power Dissipation
(TJ max − TA)/θJA
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Includes programming of OTP memory.
3 Thermal Resistance (JEDEC 4 layer(2S2P) board).
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 9 of 17
AD5270/AD5271
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 6. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic
Description
1
2
3
4
VDD
A
Positive Power Supply. This pin should be decoupled with 0.1µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC. VSS ≤ VA ≤ VDD
W
Wiper terminal of RDAC. VSS ≤ VW ≤ VDD
VSS
Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1µF
ceramic capacitors and 10 µF capacitors.
5
6
7
MEM_CAP
GND
SDO
Connect a 1µF capacitor between MEM_CAP and VSS.
Ground Pin, Logic Ground Reference.
Serial Data Output. Open Drain Output requires external pull-up resistor. SDO can be used to clock data from
the serial register on the poitive SCLK edge in daisy chain or readback mode.
8
SDIN
SCLK
SYNC
Serial Data Line. This is used in conjunction with the SCLK line to clock data into or out of the 16-bit input
register.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 50 MHz.
9
10
Falling edge Synchronisation signal.
This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift
register and data is transferred in on the falling edges of the following clocks. The selected DAC register is
updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high before the 16th clock
cycle the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
Rev. PrA | Page 10 of 17
Preliminary Technical Data
THEORY OF OPERATION
AD5270/AD5271
RDAC REGISTER
The RDAC register directly controls the position of the digital
rheostat wiper. For example, when the RDAC register is loaded
with all zeros, the wiper is connected to Terminal A of the
variable resistor. The RDAC register is a standard logic register;
there is no restriction on the number of changes allowed.
The AD5270 and AD5271 programmable resistors are designed
to operate as true variable resistors for analog signals within the
terminal voltage range of VSS < VTERM < VDD. The resistor wiper
position is determined by the RDAC register contents. The
RDAC register acts as a scratchpad register which allows
unlimited changes of resistance settings. The RDAC register can
be programmed with any position setting using the SPI
interface. Once a desirable wiper position is found, this value
can be stored in a 50-TP memory register. Thereafter, the wiper
position is always restored to that position for subsequent
power-up. The storing of 50-TP data takes approximately TBD;
during this time, the AD5270/1 will be locked preventing any
changes from taking place.
50-TP MEMORY BLOCK
The AD5270/71 contain an array of 50 OTP (One-Time
Programmable) memory words which allow the wiper position
to be programmed up to 50 times. Table 9 shows the memory
map. Once a desirable wiper position is found, this value can be
saved into a 50-TP memory register. Thereafter the wiper
position will always be set at that position for any future ON-
OFF-ON power supply sequence. Command 3, Table 7, is used
to program the contents of the RDAC register to memory. The
first address to be programmed is location 0x01(see Table 9)
and the AD5272/4 increments the 50-TP memory address for
each subsequent program until the memory is full.
The AD5270/1 also feature a patented (filed not yet issued) 1%
end-to-end resistor tolerance. This simplifies precision, rheostat
mode, and open-loop applications where knowledge of absolute
resistance is critical.
WRITE PROTECTION
SERIAL DATA INTERFACE
On power-up, serial data input register write commands for
both the RDAC register and the 50-TP memory registers are
disabled. The RDAC write protect bit, C1 of the control register
(Table 8), is set to 0 by default. This disables any change of the
RDAC register content regardless of the software commands,
except that the RDAC register can be refreshed from the 50-TP
memory using the software reset command (command #4). To
enable programming of the variable resistor wiper position
(programming the RDAC register) the write protect bit C1 of
the control register must first be programmed. This is
accomplished by loading the serial data input register with
Command #7 (Table 7). To enable programming of the 50-TP
memory block bit C0 of the control register, set to 0 by default,
must first be set to ‘1’.
The AD5270/1contain a serial interface (
, SCLK, DIN and
SYNC
SDO), which is compatible with SPI interface standards, as well
as most DSPs. This device allows writing of data via the serial
interface to every register.
INPUT SHIFT REGISTER
For the AD5270/1 the input shift register is 16 bits wide
(Figures 2 and 3). The 16-bit word consists of two unused bits
(should be set to zero), followed by four control bits, and ten
RDAC data bits, for the AD5272 the lower 2 DAC data bits are
don’t cares if the RDAC register is read from or wrote to. Data is
loaded MSB first (Bit 15). The four control bits determine the
function of the software command (Table 7). Figure 4 shows a
timing diagram of a typical AD5270/1 write sequence.
RDAC AND 50-TP WRITE OPERATION
The write sequence begins by bringing the
line low. The
SYNC
The basic mode of setting the variable resistor wiper position
(programming the RDAC register) is accomplished by loading
the serial data input register with Command #1 (Table 7) and
the desired wiper position data. When the desired wiper
position is determined, the user can load the serial data input
register with Command #3 (Table 7) which stores the wiper
position data in a 50-TP memory register. After TBD (μs), the
wiper position is permanently stored in the 50-TP memory.
Programming data to 50-TP consumes approximately 4mA and
takes approximately TBDms, during this time the shift register
is locked preventing any changes from taking place. Bit C3 of
the Control register can be polled to verify that the fuse
program command was successful. No change in supply voltage
is required to program the 50-TP memory however a 1μF
capacitor on the MEM_CAP pin is required (Figure 9). Prior to
50-TP activation, the AD5270 and the AD5271 preset to mid-
scale on power-up.
pin must be held low until the complete data-word is
SYNC
loaded from the DIN pin. When
returns high, the serial
SYNC
data-word is decoded according to the instructions in Table 7.
The command bits (Cx) control the operation of the digital
potentiometer. The data bits (Dx) are the values that are loaded
into the decoded register. The AD5270/1 have an internal
counter that counts a multiple of 16 bits (a frame) for proper
operation. For example, AD5270/1 work with a 32-bit word, but
cannot work properly with a 31-bit or 33-bit word. The
AD5270/1 do not require a continuous SCLK and dynamic
power can be saved by only transmitting clock pulses during a
serial write. All interface pins should be operated at close to the
supply rails to minimize power consumption in the digital input
buffers.
Rev. PrA | Page 11 of 17
AD5270/AD5271
Preliminary Technical Data
RDAC AND 50-TP READ OPERATION
0x1419
0x2000
0x0000
0x0100
Prepares data read from memory
location 0x19.
A serial data output SDO pin is available for read back of the
internal RDAC register or 50-TP memory contents. The
contents of the RDAC register can be read back through SDO
by using Command #2 (Table 7). Data from the RDAC register
will be clocked out of the SDO pin during the last 10 clocks of
the next SPI operation.
Prepare data read from Control
Register. Sends 16-bit word out of
SDO, where last 10-bits contain
the contents of memory location
0x19
It is possible to read back the contents of any of the 50-TP
memory registers through SDO by using Command #5 (Table
7). The lower 6 LSB bits, (D0 to D5) of the data byte, select
which memory location is to be read back (Table 10). Data from
the selected memory location will be clocked out of the SDO
pin during the next SPI operation
0x0000
0xXXXX
NOP instruction 0 sends 16-bit
word out of SDO, where last 10-
bits contain the contents of the
Control Register. If bit C3 = 1,
Fuse program command
successful.
A binary encoded version address of the most recently
programmed wiper memory location can be read back using
Command #6 (Table 7). This can be used to monitor the spare
memory status of the 50-TP memory block.
SHUT-DOWN MODE
The AD5270/AD5271 can be shut down by executing the
software shut down command, command 9 (Table 7), and
setting the LSB to ‘1’. This feature places the RDAC in a zero-
power-consumption state where Terminal Ax is open-circuited
while the Wiper Terminal Wx remains connected. It is possible
to execute any command from Table 7 while the
AD5270/AD5271 are in shut down mode. The part can be taken
out of shut-down mode by executing command 9 and setting
the LSB to ‘0’.
Table 6, provides an example listing for the sequence of serial
data input (DIN) words with the serial data output appearing at
the SDO pin in hexadecimal format for of a write and read to
both the RDAC register and 50-TP memory(memory location
20).
Table 6. Write and Read to RDAC and 50-TP memory
DIN
SDO
Action
RESET
0x1C03
0xXXXX
Enable update of wiper position
and 50-TP memory contents
through digital interface
The AD5270/AD5271 can be reset through software by
executing command 4(Table 7). The reset command loads the
RDAC Register with the contents of the most recently
programmed 50-TP memory location. The RDAC Register will
be loaded with midscale if no 50-Tp memory location has been
previously programmed.
0x0500
0x1C03
Write 0x100 to the RDAC register,
Wiper moves to ¼ fullscale
position.
DAISY-CHAIN OPERATION
0x0800
0x0C00
0x0500
0x100
Prepare data read from RDAC
Register.
The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting and 50-TP values
using Commands 2 and 5 respectively ( Table 7) or the SDO pin
can be used in daisy-chain mode. The remaining instructions
are valid for daisy-chaining multiple devices in simultaneous
operations. Data is clocked out of SDO on the rising edge of
SCLK. Daisy-chaining minimizes the number of port pins
required from the controlling IC. The SDO pin contains an
open-drain N-Ch FET that requires a pull-up resistor, if this
function is used. As shown in Figure 7, users need to tie the
SDO pin of one package to the DIN pin of the next package.
Users might need to increase the clock period, because the pull-
up resistor and the capacitive loading at the SDO–DIN interface
might require additional time delay between subsequent
devices.
Stores RDAC register content into
50-TP memory. 16-bit word
appears out of SDO, where last 10-
bits contain the contents of the
RDAC Register(0x100).
0x1800
0x0000
0x0C00
0xXX19
Prepare data read of last
programmed 50-TP Memory
monitor location
NOP instruction 0 sends 16-bit
word out of SDO, where the 6
LSB’s last 6-bits contain the binary
address of the last programmed
50-TP Memory location, e.g, 0x19
(see Table 9)
Rev. PrA | Page 12 of 17
Preliminary Technical Data
AD5270/AD5271
When two AD5270/1s are daisy-chained, 32 bits of data are
required. The first 16 bits go to U2, and the second 16 bits go to
U1. The
pin should be kept low until all 32 bits are
SYNC
clocked into their respective serial registers. The
pulled high to complete the
operation.
is then
SYNC
Figure 7. Daisy-Chain Configuration Using SDO
Table 7. Command Operation Truth Table
Command
Data
B8 B7
C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Operation
B13
C3
0
B9
B0
Command
Number
0
1
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
NOP: Do nothing.
0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of Serial Register Data to
RDAC.
2
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Read RDAC wiper setting from SDO
output in the next frame.
3
Store Wiper Setting: Store RDAC setting
to 50TP.
4
Software Reset: Refresh RDAC with OTP
stored value.
51
A5 A4 A3 A2 A1 A0
< < < < ADDR > > > >
Read contents of 50-TP from SDO output
in the next frame.
6
0
1
1
0
X
X
X
X
X
X
X
X
X
X
Read address of last 50-TP programmed
memory location from SDO output in the
next frame
7
8
9
0
1
1
1
0
0
1
0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D3 D2 D1 D0 Write Contents of Serial Register Data to
Control Register
X
X
X
X
Read Control Register from SDO output in
the next frame.
X
X
X
D0 Software Shutdown
D0 = 0; Normal Mode
D0 = 1; Device placed in Shutdown mode
1 See Table 11 for OTP Memory Map
Rev. PrA | Page 13 of 17
AD5270/AD5271
Preliminary Technical Data
Table 8. Control Register and special function codes
Register Name
Data Byte
Operation
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Control
X
X
X
X
X
X
C3 C2 C1 C0
C0 = 50-TP Program Enable
0 = 50-TP program disabled(Default)
1 = Enable device for TTP program
C1 = RDAC Register Write Protect.
0 = Wiper position frozen to value in OTP memory(Default)1
1 = Allow update of wiper position through Digital Interface
C2 = Calibration Enable.
0 = RDAC Resistor Tolerance Calibration enabled(Default)
1 = RDAC Resistor Tolerance Calibration enabled
C3 = 50-Tp Memory Program Success Bit.
0 = Fuse program command unsuccessful(Default)
1 = Fuse program command successful
1 Wiper position frozen to value last programmed in 50-TP memory. Wiper will be frozen to mid-scale if 50-TP memory has not been previously programmed
Table 9. Memory Map
Data Byte (ADDR)
Command
Number
Register Contents
D9 D8 D7 D6 A5 A4 A3 A2 A1 A0
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
Reserved
5
1st programmed wiper location1 (0X01)
2nd programmed wiper location1 (0X02)
3rd programmed wiper location1 (0X03)
4th programmed wiper location1 (0X04)
5th programmed wiper location1 (0X05)
6th programmed wiper location1 (0X06)
7th programmed wiper location1 (0X07)
8th programmed wiper location1 (0X08)
9th programmed wiper location1 (0X09)
10th programmed wiper location1 (0X0A)
20th programmed wiper location1 (0X14)
30th programmed wiper location1 (0X1E)
40th programmed wiper location1 (0X28)
50th programmed wiper location1 (0X32)
1 AD5270, 10-bit wiper memory register; AD5272, 8-bit wiper memory register
Rev. PrA | Page 14 of 17
Preliminary Technical Data
AD5270/AD5271
TBD Ω is present. Regardless of which setting the part is oper-
ating in, care should be taken to limit the current between
the A terminal to B terminal, W terminal to A terminal, and
W terminal to B terminal, to the maximum continuous current of
3 mA(20Kꢀ) or 2 mA(50Kꢀ and 100 Kꢀ) or pulse current of
TBD mA. Otherwise, degradation, or possible destruction of the
internal switch contact, can occur.
RDAC ARCHITECTURE
In order to achieve optimum cost performance, Analog Devices
has patented the RDAC segmentation architecture for all the
digital potentiometers. In particular, the AD5270/1 employs a
3-stage segmentation approach as shown in Figure 8. The
AD5270/1 wiper switch is designed with the transmission gate
CMOS topology.
MEM_CAP CAPACITOR
A 1μF capacitor to VSS must be connected to the MEM_CAP pin
(Figure 9) on power-up and throughout the operation of the
AD5270/1.
Figure 9. MEM_CAP Hardware Setup
Figure 8. AD5270/1 Simplified RDAC Circuit.
TERMINAL VOLTAGE OPERATING RANGE
The AD5270/1’s positive VDD and negative VSS power supplies
define the boundary conditions for proper 2-terminal digital
resistor operation. Supply signals present on Terminals A and
W that exceed VDD or VSS are clamped by the internal forward-
biased diodes (Figure 10).
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation - 1% Resistor Tolerance
The nominal resistance between Terminal W and Terminal A,
RWA, is available in 20 kΩ, 50 kΩ, and 100 kΩ and has 1,024/256
tap points accessed by the wiper terminal. The 10/8-bit data in
the RDAC latch is decoded to select one of the 1,024/256
possible wiper settings. The AD5270/1 contain an internal
1% resistor tolerance calibration feature which can be disabled
or enabled, enabled by default, by programming bit C2 of the
control register (Table 8). The digitally programmed output
resistance between the W terminal and the A terminal, RWA is
calibrated to give a maximum of 1% absolute resistance error
over both the full supply and temperature ranges. As a result,
the general equations for determining the digitally programmed
output resistance between the W terminal and A terminal are
AD5270:
Figure 10. Maximum Terminal Voltages Set by VDD and V SS
The ground pin of the AD5270/1 devices is primarily used as a
digital ground reference. To minimize the digital ground
bounce, the AD5270/1 ground terminal should be joined
remotely to the common ground. The digital input control
signals to the AD5270/1 must be referenced to the device
ground pin (GND), and satisfy the logic level defined in the
Specifications section. An internal level-shift circuit ensures
that the common-mode voltage range of the three terminals
extends from VSS to VDD, regardless of the digital input level.
D
RWA (D) =
× RWA
(1)
1,024
AD5271:
D
RWA(D) =
× RWA
(2)
256
where:
D is the decimal equivalent of the binary code loaded in
the 10/8-bit RDAC register.
Power-Up Sequence
R
WA is the end-to-end resistance.
Because there are diodes to limit the voltage compliance at
Terminals A and W (Figure 10), it is important to power
In the zero-scale condition, a finite total wiper resistance of
Rev. PrA | Page 15 of 17
AD5270/AD5271
Preliminary Technical Data
VDD/VSS first before applying any voltage to Terminals A and W.
Otherwise, the diode is forward-biased such that VDD/VSS are
powered unintentionally. The ideal power-up sequence is
GND, VDD/VSS, digital inputs, and VA and VW. The order of
powering VA, VW, and digital inputs is not important as long as
they are powered after VDD/VSS .
Once VDD is powered, the power-on preset activates, which first
sets the RDAC to midscale and then restores the last
programmed 50-TP value to the RDAC register.
Rev. PrA | Page 16 of 17
Preliminary Technical Data
OUTLINE DIMENSIONS
AD5270/AD5271
Figure 11. 10-Lead Frame Chip Scale Package[LFCSP_WD]
3mm x 3mm Body, Very Thin, Dual Lead (CP-10-9)
Dimensions shown in millimeters
Figure 12. 10-Lead Mini Small Outline Package[MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5270BCPZ100-R2
AD5270BCPZ100-RL7
AD5270BCPZ20-R2
AD5270BCPZ20-RL7
AD5270BCPZ20-U1
AD5270BRMZ100
AD5270BRMZ100-RL7
AD5270BRMZ100-U1
AD5270BRMZ20
AD5270BRMZ20-RL7
AD5270BRMZ-20-U1
AD5270BRMZ-50
AD5271BCPZ100-R2
AD5271BCPZ100-RL7
AD5271BCPZ20-R2
AD5271BCPZ20-RL7
AD5271BCPZ20-U1
AD5271BRMZ100
RAB (kΩ)
100
100
20
20
20
100
100
100
20
20
20
50
100
100
20
20
20
Resolution
1,024
1,024
1,024
1,024
1,024
1,024
1,024
1,024
1,024
1,024
1,024
1,024
256
Temperature Range
Package Description Package Option
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
256
256
256
256
256
256
256
256
100
100
100
20
20
20
AD5271BRMZ100-RL7
AD5271BRMZ100-U1
AD5271BRMZ20
AD5271BRMZ20-RL7
AD5271BRMZ-20-U1
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
256
256
10-Lead MSOP
©
2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR08077-0-2/09(PrA)
Rev. PrA | Page 17 of 17
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