AD1895AYRSZ [ROCHESTER]
SPECIALTY CONSUMER CIRCUIT, PDSO28, PLASTIC, MO-150AH, SSOP-28;
| 型号： | AD1895AYRSZ |
| 厂家： | 
Rochester Electronics |
| 描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28, PLASTIC, MO-150AH, SSOP-28 光电二极管 商用集成电路 |
| 文件： | 总25页 (文件大小：1582K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
192 kHz Stereo Asynchronous
Sample Rate Converter
a
AD1895
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Automatically Senses Sample Frequencies
No Programming Required
VDD_IO VDD_CORE
RESET
Attenuates Sample Clock Jitter
3.3 V to 5 V Input and 3.3 V Core Supply Voltages
Accepts 16-/18-/20-/24-Bit Data
Up to 192 kHz Sample Rate
Input/Output Sample Ratios from 7.75:1 to 1:8
Bypass Mode
Multiple AD1895 TDM Daisy-Chain Mode
128 dB Signal-to-Noise and Dynamic Range
(A-Weighted, 20 Hz to 20 kHz BW)
Up to –122 dB THD + N
AD1895
MUTE_IN
FS
OUT
SDATA_I
SCLK_I
LRCLK_I
SDATA_O
SCLK_O
LRCLK_O
FIFO
FS
IN
SERIAL
INPUT
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
TDM_IN
SERIAL
OUTPUT
FIR
FILTER
SMODE_OUT_0
SMODE_OUT_1
DIGITAL
PLL
BYPASS
MUTE_OUT
WLNGTH_OUT_0
WLNGTH_OUT_1
Linear Phase FIR Filter
CLOCK DIVIDER
MMODE_0
ROM
Hardware Controllable Soft Mute
Supports 256
؋
fS, 512 ؋
fS, or 768 ؋
fS Master Mode Clock
Flexible 3-Wire Serial Data Port with Left-Justified,
I2S, Right-Justified (16-, 18-, 20-, 24-Bit), and TDM
Serial Port Modes
MCLK_IN
MMODE_2
MCLK_OUT
MMODE_1
a digital signal processor. The serial output data is dithered down
to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is
selected. The AD1895 sample rate converts the data from the
serial input port to the sample rate of the serial output port. The
sample rate at the serial input port can be asynchronous with
respect to the output sample rate of the output serial port. The
master clock to the AD1895, MCLK, can be asynchronous to
both the serial input and output ports.
Master/Slave Input and Output Modes
28-Lead SSOP Plastic Package
APPLICATIONS
Home Theater Systems, Automotive Audio Systems,
DVD, DVD-R, CD-R, Set-Top Boxes, Digital Audio
Effects Processors
MCLK can either be generated off-chip or on-chip by the AD1895
master clock oscillator. Since MCLK can be asynchronous to the
input or output serial ports, a crystal can be used to generate
MCLK internally to reduce noise and EMI emissions on the
board. When MCLK is synchronous to either the output or input
serial port, the AD1895 can be configured in a master mode where
MCLK is divided down and used to generate the left/right
and bit clocks for the serial port that is synchronous to MCLK.
The AD1895 supports master modes of 256 × fS, 512 × fS, and
768 × fS for both input and output serial ports.
PRODUCT OVERVIEW
The AD1895 is a 24-bit, high performance, single-chip, second
generation asynchronous sample rate converter. Based upon
Analog Devices’ experience with its first asynchronous sample
rate converter, the AD1890, the AD1895 offers improved perfor-
mance and additional features. This improved performance
includes a THD + N range of –115 dB to –122 dB depending
on sample rate and input frequency, 128 dB (A-Weighted)
dynamic range, 192 kHz sampling frequencies for both input and
output sample rates, improved jitter rejection, and 1:8 upsampling
and 7.75:1 downsampling ratios. Additional features include
more serial formats, a bypass mode, and better interfacing to
digital signal processors.
Conceptually, the AD1895 interpolates the serial input data by
a rate of 220 and samples the interpolated data stream by the
output sample rate. In practice, a 64-tap FIR filter with 220
polyphases, a FIFO, a digital servo loop that measures the time
difference between input and output samples within 5 ps, and a
digital circuit to track the sample rate ratio are used to perform
the interpolation and output sampling. Refer to the Theory of
Operation section. The digital servo loop and sample rate ratio
circuit automatically track the input and output sample rates.
(continued on page 15)
The AD1895 has a 3-wire interface for the serial input and
output ports that supports left-justified, I2S, and right-justified
(16-, 18-, 20-, 24-bit) modes. Additionally, the serial output
port supports TDM Mode for daisy-chaining multiple AD1895s to
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
AD1895–SPECIFICATIONS
TEST CONDITIONS, UNLESS OTHERWISE NOTED.
Supply Voltages
VDD_CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V
VDD_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 V or 3.3 V
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.0 MHz
Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . 1.000 kHz, 0 dBFS
Measurement Bandwidth . . . . . . . . . . . . . . . . . . 20 to fS_OUT/2 Hz
Word Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bits
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 pF
Input Voltage High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 V
Input Voltage Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 V
DIGITAL PERFORMANCE (VDD_CORE = 3.3 V ꢀ 5%, VDD_IO = 5.0 V ꢀ 10%)
Parameter
Min
Typ
Max
Unit
Bits
kHz
kHz
RESOLUTION
24
SAMPLE RATE @ MCLK_IN = 30 MHz
SAMPLE RATE (@ OTHER MASTER CLOCKS)1
6
215
MCLK_IN/5000 ≤ fS_MAX < MCLK_IN/138
SAMPLE RATE RATIOS
Upsampling
Downsampling
1:8
7.75:1
DYNAMIC RANGE2
(20 Hz to fS_OUT/2, 1 kHz, –60 dBFS Input) A-Weighted
44.1 kHz: 48 kHz
48 kHz: 44.1 kHz
48 kHz: 96 kHz
44.1 kHz: 192 kHz
96 kHz: 48 kHz
192 kHz: 32 kHz
128
128
128
128
127
127
dB
dB
dB
dB
dB
dB
(20 Hz to fS_OUT/2, 1 kHz, –60 dBFS Input) No Filter
44.1 kHz: 48 kHz
48 kHz: 44.1 kHz
48 kHz: 96 kHz
44.1 kHz: 192 kHz
125
125
125
125
124
124
dB
dB
dB
dB
dB
dB
96 kHz: 48 kHz
192 kHz: 32 kHz
TOTAL HARMONIC DISTORTION + NOISE2
(20 Hz to fS_OUT/2, 1 kHz, 0 dBFS Input) No Filter
Worst-Case (48 kHz: 96 kHz)3
44.1 kHz: 48 kHz
48 kHz: 44.1 kHz
48 kHz: 96 kHz
44.1 kHz: 192 kHz
96 kHz: 48 kHz
192 kHz: 32 kHz
–115
dB
dB
dB
dB
dB
dB
dB
–120
–119
–118
–120
–122
–122
INTERCHANNEL GAIN MISMATCH
INTERCHANNEL PHASE DEVIATION
0.0
dB
0.0
Degrees
dB
MUTE ATTENUATION (24 BITS WORD WIDTH)(A-WEIGHT)
–127
NOTES
1Lower sampling rates than those given by this formula are possible, but the jitter rejection will decrease.
2Refer to the Typical Performance Characteristics section for DNR and THD + N numbers over a wide range of input and output sample rates.
3For any other ratio, minimum THD + N will be better than –115 dB. Please refer to detailed performance plots.
Specifications subject to change without notice.
–2–
REV. B
AD1895
DIGITAL TIMING (–40ꢀC < TA < +105ꢀC, VDD_CORE = 3.3 V ꢁ 5%, VDD_IO = 5.0 V ꢁ 10%)
Parameter1
Min
Max
Unit
tMCLKI
fMCLK
tMPWH
tMPWL
MCLK_IN Period
33.3
ns
MHz
ns
MCLK_IN Frequency
MCLK_IN Pulsewidth High
MCLK_IN Pulsewidth Low
30.02, 3
9
12
ns
INPUT SERIAL PORT TIMING
tLRIS
tSIH
tSIL
tDIS
tDIH
LRCLK_I Setup to SCLK_I
SCLK_I Pulsewidth High
SCLK_I Pulsewidth Low
SDATA_I Setup to SCLK_I Rising Edge
SDATA_I Hold from SCLK_I Rising Edge
8
8
8
8
3
ns
ns
ns
ns
ns
OUTPUT SERIAL PORT TIMING
tTDMS
tTDMH
tDOPD
tDOH
tLROS
tLROH
tSOH
TDM_IN Setup to SCLK_O Falling Edge
3
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDM_IN Hold from SCLK_O Falling Edge
SDATA_O Propagation Delay from SCLK_O, LRCLK_O
SDATA_O Hold from SCLK_O
LRCLK_O Setup to SCLK_O (TDM Mode Only)
LRCLK_O Hold from SCLK_O (TDM Mode Only)
SCLK_O Pulsewidth High
20
3
5
3
10
5
tSOL
tRSTL
SCLK_O Pulsewidth Low
RESET Pulsewidth Low
200
NOTES
1Refer to Timing Diagrams section.
2The maximum possible sample rate is: FSMAX = fMCLK /138.
3fMCLK of up to 34 MHz is possible under the following conditions: 0°C < TA < 70°C, 45/55 or better MCLK_IN duty cycle.
Specifications subject to change without notice.
TIMING DIAGRAMS
MCLK IN
LRCLK_I
tSIH
tLRIS
RESET
SCLK I
tRSTL
tDIS
tSIL
Figure 2. RESET Timing
SDATA I
tDIH
LRCLK O
SCLK O
tMPWH
tSOH
tSOL
tDOPD
tMPWL
SDATA O
LRCLK O
tDOH
Figure 3. MCLK_IN Timing
tLROS
tLROH
SCLK O
TDM IN
tTDMS
tTDMH
Figure 1. Input and Output Serial Port Timing (SCLK_I/O,
LRCLK_I/O, SDATA_I/O, TDM_IN)
REV. B
–3–
–SPECIFICATIONS
AD1895
DIGITAL FILTERS (VDD_CORE = 3.3 V ꢁ 5%, VDD_IO = 5.0 V ꢁ 10%)
Parameter
Min
Typ
Max
Unit
Pass Band
0.4535 fS_OUT
0.016
0.5465 fS_OUT
Hz
dB
Hz
Hz
dB
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
0.4535 fS_OUT
0.5465 fS_OUT
–125
Refer to the Group Delay Equations Section
Specifications subject to change without notice.
DIGITAL I/O CHARACTERISTICS (VDD_CORE = 3.3 V ꢁ 5%, VDD_IO = 5.0 V ꢁ 10%)
Parameter
Min
Typ
Max
Unit
Input Voltage High (VIH)
Input Voltage Low (VIL)
2.4
V
V
µA
µA
pF
V
V
mA
mA
0.8
+2
–2
Input Leakage (IIH @ VIH = 5 V)
Input Leakage (IIL @ VIL = 0 V)
Input Capacitance
Output Voltage High (VOH @ IOH = –4 mA)
Output Voltage Low (VOL @ IOL = +4 mA)
5
10
VDD_CORE – 0.5
VDD_CORE – 0.4
0.2
0.5
–4
+4
Output Source Current High (IOH
Output Sink Current Low (IOL
)
)
Specifications subject to change without notice.
POWER SUPPLIES
Parameter
Min
Typ
Max
Unit
SUPPLY VOLTAGE
VDD_CORE
VDD_IO*
3.135
VDD_CORE
3.3
3.3/5.0
3.465
5.5
V
V
ACTIVE SUPPLY CURRENT
I_CORE_ACTIVE
48 kHz: 48 kHz
96 kHz: 96 kHz
192 kHz: 192 kHz
I_IO_ACTIVE
20
26
43
2
mA
mA
mA
mA
POWER-DOWN SUPPLY CURRENT: (ALL CLOCKS STOPPED)
I_CORE_PWRDN
I_IO_PWRDN
0.5
10
mA
µA
*For 3.3 V tolerant inputs, VDD_IO supply should be set to 3.3 V; however, VDD_CORE supply voltage should not exceed VDD_IO.
Specifications subject to change without notice.
REV. B
–4–
AD1895
POWER SUPPLIES (VDD_CORE = 3.3 V ꢁ 5%, VDD_IO = 5.0 V ꢁ 10%)
Parameter
Min
Typ
Max
Unit
TOTAL ACTIVE POWER DISSIPATION
48 kHz: 48 kHz
96 kHz: 96 kHz
65
85
132
mW
mW
mW
192 kHz: 192 kHz
TOTAL POWER-DOWN DISSIPATION (RESET LOW)
2
mW
Specifications subject to change without notice.
TEMPERATURE RANGE
Parameter
Min
Typ
Max
Unit
Specifications Guaranteed
Functionality Guaranteed
Storage
25
°C
–40
–55
+105
+150
°C
°C
°C/W
Thermal Resistance, θJA (Junction to Ambient)
109
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Parameter
Min
Max
Unit
POWER SUPPLIES
VDD_CORE
VDD_IO
–0.3
–0.3
+3.6
+6.0
V
V
DIGITAL INPUTS
Input Current
10
mA
V
Input Voltage
DGND – 0.3
–40
VDD_IO + 0.3
AMBIENT TEMPERATURE (OPERATING)
+105
°C
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD1895AYRS
AD1895AYRSRL
–40°C to +105°C
–40°C to +105°C
28-Lead SSOP
28-Lead SSOP
RS-28
RS-28 on 13" Reel
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1895 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
AD1895
PIN FUNCTION DESCRIPTIONS
Description
Pin No.
IN/OUT (I/O)
Mnemonic
1
2
IN
IN
NC
MCLK_IN
No Connect
Master Clock or Crystal Input
3
4
5
6
7
8
OUT
IN
IN/OUT
IN/OUT
IN
MCLK_OUT
SDATA_I
SCLK_I
LRCLK_I
VDD_IO
Master Clock Output or Crystal Output
Input Serial Data (at Input Sample Rate)
Master/Slave Input Serial Bit Clock
Master/Slave Input Left/Right Clock
3.3 V/5 V Input/Output Digital Supply Pin
Digital Ground Pin
IN
DGND
9
IN
BYPASS
ASRC Bypass Mode, Active High
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
IN/OUT
IN/OUT
IN
IN
IN
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
RESET
Input Port Serial Interface Mode Select Pin 0
Input Port Serial Interface Mode Select Pin 1
Input Port Serial Interface Mode Select Pin 2
Reset Pin, Active Low
Mute Input Pin—Active High Normally Connected to MUTE_OUT
Output Mute Control—Active High
Hardware Selectable Output Wordlength—Select Pin 1
Hardware Selectable Output Wordlength—Select Pin 0
Output Port Serial Interface Mode Select Pin 1
Output Port Serial Interface Mode Select Pin 0
Serial Data Input* (Only for Daisy-Chain Mode). Ground when not used.
Digital Ground Pin
MUTE_IN
MUTE_OUT
WLNGTH_OUT_1
WLNGTH_OUT_0
SMODE_OUT_1
SMODE_OUT_0
TDM_IN
DGND
VDD_CORE
SDATA_O
LRCLK_O
SCLK_O
MMODE_0
MMODE_1
MMODE_2
3.3 V Digital Supply Pin
Output Serial Data (at Output Sample Rate)
Master/Slave Output Left/Right Clock
Master/Slave Output Serial Bit Clock
Master/Slave Clock Ratio Mode Select Pin 0
Master/Slave Clock Ratio Mode Select Pin 1
Master/Slave Clock Ratio Mode Select Pin 2
*Also used to input matched-phase mode data.
PIN CONFIGURATION
NC
1
2
28 MMODE_2
27
26
25
24
23
22
21
20
MCLK_IN
MCLK_OUT
SDATA_I
MMODE_1
MMODE_0
SCLK_O
LRCLK_O
SDATA_O
VDD_CORE
DGND
3
4
AD1895
TOP VIEW
(NOT TO SCALE
5
SCLK_I
)
6
LRCLK_I
7
VDD_IO
8
DGND
BYPASS
9
TDM_IN
10
11
12
13
14
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
19 SMODE_OUT_0
18 SMODE_OUT_1
17
16
15
WLNGTH_OUT_0
WLNGTH_OUT_1
MUTE_OUT
RESET
MUTE_IN
NC = NO CONNECT
REV. B
–6–
Typical Performance Characteristics–AD1895
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
0
2.5
5.0
7.5 10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
0
10
20
30
40
50
60
70
80
90
FREQUENCY – kHz
TPC 1. Wideband FFT Plot (16 k Points) 0 dBFS 1 kHz
Tone, 48 kHz: 48 kHz (Asynchronous)
TPC 4. Wideband FFT Plot (16 k Points) 44.1 kHz: 192 kHz,
0 dBFS 1 kHz Tone
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
0
2.5
5.0
7.5
10.0
12.5 15.0
17.5 20.0
0
2.5
5.0
7.5 10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
FREQUENCY – kHz
TPC 2. Wideband FFT Plot (16 k Points) 0 dBFS 1 kHz
Tone, 44.1 kHz: 48 kHz (Asynchronous)
TPC 5. Wideband FFT Plot (16 k Points) 48 kHz: 44.1 kHz,
0 dBFS 1 kHz Tone
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
0
2.5
5.0
7.5 10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
0
5
10
15
20
25
30
35
40
45
FREQUENCY – kHz
TPC 3. Wideband FFT Plot (16 k Points) 48 kHz: 96 kHz,
0 dBFS 1 kHz Tone
TPC 6. Wideband FFT Plot (16 k Points) 96 kHz: 48 kHz,
0 dBFS 1 kHz Tone
REV. B
–7–
AD1895
0
–50
–60
–70
–80
–90
–20
–40
–60
–100
–110
–80
–120
–130
–140
–150
–160
–170
–180
–190
–200
–100
–120
–140
–160
–180
–200
0
2.5
5.0
7.5 10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
0
5
10
15
20
25
30
35
40
45
FREQUENCY – kHz
TPC 7. Wideband FFT Plot (16 k Points) 192 kHz: 48 kHz,
0 dBFS 1 kHz Tone
TPC 10. Wideband FFT Plot (16 k Points) 48 kHz: 96 kHz,
–60 dBFS 1 kHz Tone
–50
–50
–60
–70
–60
–70
–80
–90
–80
–90
–100
–110
–100
–110
–120
–130
–120
–130
–140
–150
–160
–170
–180
–190
–200
–140
–150
–160
–170
–180
–190
–200
0
2.5
5.0
7.5 10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
0
10
20
30
40
50
60
70
80
90
FREQUENCY – kHz
TPC 8. Wideband FFT Plot (16 k Points) 48 kHz: 48 kHz
–60 dBFS 1 kHz Tone (Asynchronous)
TPC 11. Wideband FFT Plot (16 k Points) 44.1 kHz: 192 kHz,
–60 dBFS 1 kHz Tone
–50
–50
–60
–60
–70
–80
–90
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
–200
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
–200
0
2.5
5.0
7.5
10.0 12.5 15.0 17.5
20.0
0
2.5
5.0
7.5 10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
FREQUENCY – kHz
TPC 12. Wideband FFT Plot (16 k Points) 48 kHz: 44.1 kHz,
–60 dBFS 1 kHz Tone
TPC 9. Wideband FFT Plot (16 k Points) 44.1 kHz: 48 kHz,
–60 dBFS 1 kHz Tone
REV. B
–8–
AD1895
–50
–60
–70
0
–20
–80
–90
–40
–60
–100
–110
–120
–130
–80
–100
–120
–140
–140
–150
–160
–170
–180
–190
–200
–160
–180
0
2.5
5.0
7.5
10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
0
2.5
5.0
7.5
10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
TPC 13. Wideband FFT Plot (16 k Points) 96 kHz: 48 kHz,
–60 dBFS 1 kHz Tone
TPC 16. IMD, 10 kHz and 11 kHz, 0 dBFS Tone,
96 kHz: 48 kHz
–50
–60
–70
0
–20
–80
–90
–40
–100
–110
–120
–130
–140
–60
–80
–100
–120
–140
–150
–160
–170
–180
–190
–200
–160
–180
0
2.5
5.0
7.5
10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
0
2.5
5.0
7.5
10.0 12.5 15.0 17.5
20.0
FREQUENCY – kHz
TPC 14. Wideband FFT Plot (16 k Points) 192 kHz: 48 kHz,
–60 dBFS 1 kHz Tone
TPC 17. IMD, 10 kHz and 11 kHz, 0 dBFS Tone,
48 kHz: 44.1 kHz
0
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
–180
–180
–200
0
2.5
5.0
7.5
10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
0
2.5
5.0
7.5
10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
TPC 15. IMD, 10 kHz and 11 kHz, 0 dBFS Tone,
44:1 kHz: 48 kHz
TPC 18. Wideband FFT Plot (16 k Points) 44.1 kHz: 48 kHz,
0 dBFS 20 kHz Tone
REV. B
–9–
AD1895
0
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
–180
–200
–180
–200
0
10
20
30
40
50
60
70
80
90
0
5
10
15
20
25
30
35
40
45
FREQUENCY – kHz
FREQUENCY – kHz
TPC 19. Wideband FFT Plot (16 k Points) 192 kHz: 192 kHz,
0 dBFS 80 kHz Tone
TPC 22. Wideband FFT Plot (16 k Points) 48 kHz: 96 kHz,
0 dBFS 20 kHz Tone
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
–180
–200
–180
–200
0
2.5
5.0
7.5
10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
0
2.5
5.0
7.5
10.0 12.5 15.0 17.5 20.0 22.5
FREQUENCY – kHz
TPC 20. Wideband FFT Plot (16 k Points) 48 kHz: 48 kHz,
0 dBFS 20 kHz Tone
TPC 23. Wideband FFT Plot (16 k Points) 96 kHz: 48 kHz,
0 dBFS 20 kHz Tone
0
–20
–119
–121
–123
–125
–127
–129
–131
–133
–135
–40
–60
–80
–100
–120
–140
–160
–180
–200
0
2.5
5.0
7.5
10.0 12.5 15.0 17.5
20.0
30000
66000
102000
138000
174000
192000
48000
84000
OUTPUT SAMPLE RATE – Hz
120000
156000
FREQUENCY – kHz
TPC 21. Wideband FFT Plot (16 k Points) 48 kHz: 44:1 kHz,
0 dBFS 20 kHz Tone
TPC 24. THD + N vs. Output Sample Rate, fS_IN = 192 kHz,
0 dBFS 1 kHz Tone
REV. B
–10–
AD1895
–119
–121
–123
–125
–127
–129
–131
–133
–135
–119
–121
–123
–125
–127
–129
–131
–133
–135
30000
66000
102000
138000
174000
30000
66000
102000
138000
174000
192000
48000
84000
OUTPUT SAMPLE RATE – Hz
120000
156000
192000
48000
84000
OUTPUT SAMPLE RATE – Hz
120000
156000
TPC 25. THD + N vs. Output Sample Rate, fS_IN = 48 kHz,
0 dBFS 1 kHz Tone
TPC 28. THD + N vs. Output Sample Rate, fS_IN = 96 kHz,
0 dBFS 1 kHz Tone
–119
–121
–123
–125
–127
–129
–131
–133
–135
–119
–121
–123
–125
–127
–129
–131
–133
–135
30000
66000
102000
138000
174000
192000
30000
66000
102000
138000
174000
192000
48000
84000
OUTPUT SAMPLE RATE – Hz
120000
156000
48000
84000
OUTPUT SAMPLE RATE – Hz
120000
156000
TPC 26. THD + N vs. Output Sample Rate, fS_IN
44.1 kHz, 0 dBFS 1 kHz Tone
=
TPC 29. DNR (Unweighted) vs. Output Sample Rate,
fS_IN = 192 kHz, –60 dBFS 1 kHz Tone
–119
–121
–123
–125
–127
–129
–131
–133
–135
–119
–121
–123
–125
–127
–129
–131
–133
–135
30000
66000
102000
138000
174000
30000
66000
102000
138000
174000
192000
48000
84000
OUTPUT SAMPLE RATE – Hz
120000
156000
192000
48000
84000
OUTPUT SAMPLE RATE – Hz
120000
156000
TPC 30. DNR (Unweighted) vs. Output Sample Rate,
fS_IN = 32 kHz, –60 dBFS 1 kHz Tone
TPC 27. THD + N vs. Output Sample Rate, fS_IN = 32 kHz,
0 dBFS 1 kHz Tone
REV. B
–11–
AD1895
–119
–121
–123
–125
–127
–129
–131
–133
–135
–119
–121
–123
–125
–127
–129
–131
–133
–135
30000
66000
102000
138000
174000
192000
30000
66000
102000
138000
174000
192000
48000
84000
OUTPUT SAMPLE RATE – Hz
120000
156000
48000
84000
OUTPUT SAMPLE RATE – Hz
120000
156000
TPC 34. DNR (Unweighted) vs. Output Sample Rate,
TPC 31. DNR (Unweighted) vs. Output Sample Rate,
f
S_IN = 44.1 kHz, –60 dBFS 1 kHz Tone
f
S_IN = 96 kHz, –60 dBFS 1 kHz Tone
0.00
–0.01
–0.02
0
–20
192kHz: 96kHz
–40
–60
–0.03
–0.04
–0.05
–0.06
–0.07
192kHz: 48kHz
–80
192kHz: 32kHz
–100
–120
–140
–0.08
–0.09
–0.10
0
4000
8000
12000
16000
20000
24000
0
10000
20000
30000
40000
50000
60000
FREQUENCY – Hz
FREQUENCY – Hz
TPC 35. Pass-Band Ripple, 192 kHz: 48 kHz
TPC 32. Digital Filter Frequency Response
5
4
–119
–121
–123
–125
–127
–129
–131
–133
–135
3
2
1
0
–1
–2
–3
–4
–5
30000
66000
102000
138000
174000
192000
–140
–120
–100
–80
–60
–40
–20
0
48000
84000
OUTPUT SAMPLE RATE – Hz
120000
156000
INPUT LEVEL – dBFS
TPC 36. Linearity Error, 48 kHz: 48 kHz, 0 dBFS to
–140 dBFS Input, 200 Hz Tone
TPC 33. DNR (Unweighted) vs. Output Sample Rate,
fS_IN = 48 kHz, –60 dBFS 1 kHz Tone
REV. B
–12–
AD1895
5
4
5
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–140
–120
–100
–80
–60
–40
–20
0
–140
–120
–100
–80
–60
–40
–20
0
INPUT LEVEL – dBFS
INPUT LEVEL – dBFS
TPC 40. Linearity Error, 48 kHz: 96 kHz, 0 dBFS to
–140 dBFS Input, 200 Hz Tone
TPC 37. Linearity Error, 48 kHz: 44.1 kHz, 0 dBFS to
–140 dBFS Input, 200 Hz Tone
5
4
5
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–140
–120
–100
–80
–60
–40
–20
0
–140
–120
–100
–80
–60
–40
–20
0
INPUT LEVEL – dBFS
INPUT LEVEL – dBFS
TPC 41. Linearity Error, 44.1 kHz: 192 kHz, 0 dBFS to
–140 dBFS Input, 200 Hz Tone
TPC 38. Linearity Error, 96 kHz: 48 kHz, 0 dBFS to
–140 dBFS Input, 200 Hz Tone
5
4
5
4
3
3
2
1
0
2
1
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–140
–120
–100
–80
–60
–40
–20
0
–140
–120
–100
–80
–60
–40
–20
0
INPUT LEVEL – dBFS
INPUT LEVEL – dBFS
TPC 42. Linearity Error, 192 kHz: 44.1 kHz, 0 dBFS to
–140 dBFS Input, 200 Hz Tone
TPC 39. Linearity Error, 44.1 kHz: 48 kHz, 0 dBFS to
–140 dBFS Input, 200 Hz Tone
REV. B
–13–
AD1895
–110.0
–110.0
–112.5
–112.5
–115.0
–117.5
–120.0
–122.5
–125.0
–127.5
–130.0
–132.5
–135.0
–115.0
–117.5
–120.0
–122.5
–125.0
–127.5
–130.0
–132.5
–135.0
–137.5
–140.0
–137.5
–140.0
–140
–120
–100
–80
–60
–40
–20
0
–140
–120
–100
–80
–60
–40
–20
0
INPUT LEVEL – dBFS
INPUT LEVEL – dBFS
TPC 43. THD + N vs. Input Amplitude, 48 kHz: 44.1 kHz,
1 kHz Tone
TPC 46. THD + N vs. Input Amplitude, 48 kHz: 96 kHz,
1 kHz Tone
–110.0
–112.5
–110.0
–112.5
–115.0
–117.5
–120.0
–122.5
–125.0
–127.5
–130.0
–132.5
–135.0
–115.0
–117.5
–120.0
–122.5
–125.0
–127.5
–130.0
–132.5
–135.0
–137.5
–140.0
–137.5
–140.0
–140
–120
–100
–80
–60
–40
–20
0
–140
–120
–100
–80
–60
–40
–20
0
INPUT LEVEL – dBFS
INPUT LEVEL – dBFS
TPC 44. THD + N vs. Input Amplitude, 96 kHz: 48 kHz,
1 kHz Tone
TPC 47. THD + N vs. Input Amplitude, 44.1 kHz: 192 kHz,
1 kHz Tone
–110.0
–112.5
–110.0
–112.5
–115.0
–117.5
–120.0
–122.5
–125.0
–127.5
–130.0
–132.5
–135.0
–115.0
–117.5
–120.0
–122.5
–125.0
–127.5
–130.0
–132.5
–135.0
–137.5
–140.0
–137.5
–140.0
–140
–120
–100
–80
–60
–40
–20
0
–140
–120
–100
–80
–60
–40
–20
0
INPUT LEVEL – dBFS
INPUT LEVEL – dBFS
TPC 45. THD + N vs. Input Amplitude, 44.1 kHz: 48 kHz,
1 kHz Tone
TPC 48. THD + N vs. Input Amplitude, 192 kHz: 48 kHz,
1 kHz Tone
REV. B
–14–
AD1895
–110
–110
–120
–130
–140
–120
–130
–140
–150
–160
–150
–160
–170
–180
–170
–180
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
FREQUENCY – kHz
FREQUENCY – kHz
TPC 49. THD + N vs. Frequency Input, 48 kHz: 44.1 kHz,
0 dBFS
TPC 51. THD + N vs. Frequency Input, 48 kHz: 96 kHz,
0 dBFS
–110
–110
–120
–130
–140
–120
–130
–140
–150
–160
–150
–160
–170
–180
–170
–180
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
FREQUENCY – kHz
FREQUENCY – kHz
TPC 50. THD + N vs. Frequency Input, 44.1 kHz: 48 kHz,
0 dBFS
TPC 52. THD + N vs. Frequency Input, 96 kHz: 48 kHz,
0 dBFS
PRODUCT OVERVIEW (continued from page 1)
Fast Mode, the MUTE_OUT signal is asserted high. Normally,
the MUTE_OUT is connected to the MUTE_IN pin. The
MUTE_IN signal is used to softly mute the AD1895 upon
assertion and softly unmute the AD1895 when it is deasserted.
The digital servo loop measures the time difference between
input and output sample rates within 5 ps. This is necessary in
order to select the correct polyphase filter coefficient. The digital
servo loop has excellent jitter rejection for both input and output
sample rates as well as the master clock. The jitter rejection begins
at less than 1 Hz. This requires a long settling time whenever
RESET is deasserted or when the input or output sample rate
changes. To reduce the settling time, upon deassertion of RESET
or a change in a sample rate, the digital servo loop enters the Fast
Settling Mode. When the digital servo loop has adequately settled
in the Fast Mode, it switches into the Normal or Slow Settling
Mode and continues to settle until the time difference measurement
between input and output sample rates is within 5 ps. During
The sample rate converter of the AD1895 can be bypassed
altogether using the Bypass Mode. In Bypass Mode, the AD1895’s
serial input data is directly passed to the serial output port with-
out any dithering. This is useful for passing through nonaudio
data or when the input and output sample rates are synchronous
to one another and the sample rate ratio is exactly 1 to 1.
The AD1895 is a 3.3 V, 5 V input tolerant part and is available
in a 28-lead SSOP SMD package. The AD1895 is 5 V input
tolerant only when the VDD_IO supply pin is supplied with 5 V.
REV. B
–15–
AD1895
ASRC FUNCTIONAL OVERVIEW
THEORY OF OPERATION
involve the steps of zero-stuffing (220 –1) a number of samples
between each fS_IN sample and convolving this interpolated signal
with a digital low-pass filter to suppress the images. In the time
domain, it can be seen that fS_OUT selects the closest fS_IN × 220
sample from the zero-order hold as opposed to the nearest fS_IN
sample in the case of no interpolation. This significantly reduces
the resampling error.
Asynchronous sample rate conversion is converting data from one
clock source at some sample rate to another clock source at the
same or different sample rate. The simplest approach to asyn-
chronous sample rate conversion is the use of a zero-order hold
between two samplers as shown in Figure 4. In an asynchronous
system, T2 is never equal to T1 nor is the ratio between T2 and
T1 rational. As a result, samples at fS_OUT will be repeated or
dropped, producing an error in the resampling process. The
frequency domain shows the wide side lobes that result from this
error when the sampling of fS_OUT is convolved with the attenuated
images from the sin(x)/x nature of the zero-order hold. The images
at fS_IN, dc signal images, of the zero-order hold are infinitely
attenuated. Since the ratio of T2 to T1 is an irrational number,
the error resulting from the resampling at fS_OUT can never be
eliminated. However, the error can be significantly reduced
through interpolation of the input data at fS_IN. The AD1895 is
conceptually interpolated by a factor of 220.
IN
OUT
INTERPOLATE
BY N
LOW-PASS
FILTER
ZERO-ORDER
HOLD
fS_IN
fS_OUT
TIME DOMAIN OF fS_IN SAMPLES
TIME DOMAIN OUTPUT OFTHE LOW-PASS FILTER
IN
ZERO-ORDER
HOLD
OUT
fS_IN = 1/T1
fS_OUT = 1/T2
TIME DOMAIN OF fS_OUT RESAMPLING
ORIGINAL SIGNAL
SAMPLED AT fS_IN
TIME DOMAIN OFTHE ZERO-ORDER HOLD OUTPUT
SIN(X)/X OF ZERO-ORDER HOLD
Figure 5. Time Domain of the Interpolation and Resampling
SPECTRUM OF ZERO-ORDER HOLD OUTPUT
In the frequency domain shown in Figure 6, the interpolation
expands the frequency axis of the zero-order hold. The images
from the interpolation can be sufficiently attenuated by a good
low-pass filter. The images from the zero-order hold are now
pushed by a factor of 220 closer to the infinite attenuation point
of the zero-order hold, which is fS_IN × 220. The images at the
zero-order hold are the determining factor for the fidelity of the
output at fS_OUT. The worst-case images can be computed from
the zero-order hold frequency response, maximum image =
sin (π × F/fS_INTERP)/(π × F/fS_INTERP). F is the frequency of the
SPECTRUM OF fS_OUT SAMPLING
fS_OUT
2 ꢂ fS_OUT
FREQUENCY RESPONSE OF fS_OUT CONVOLVEDWITH ZERO-ORDER
HOLD SPECTRUM
Figure 4. Zero-Order Hold Being Used by fS_OUT to
Resample Data from fS_IN
worst-case image, which would be 220 × fS_IN
fS_INTERP is fS_IN × 220.
fS_IN/2 , and
THE CONCEPTUAL HIGH INTERPOLATION MODEL
Interpolation of the input data by a factor of 220 involves placing
(220 –1) samples between each fS_IN sample. Figure 5 shows
both the time domain and the frequency domain of interpolation
by a factor of 220. Conceptually, interpolation by 220 would
The following worst-case images would appear for fS_IN
=
192 kHz:
Image at fS_INTERP – 96 kHz = –125.1 dB
Image at fS_INTERP + 96 kHz = –125.1 dB
REV. B
–16–
AD1895
rate, fS_IN, the ROM starting address, input data, and length of
the convolution must be scaled. As the input sample rate rises
over the output sample rate, the antialiasing filter’s cutoff fre-
quency has to be lowered because the Nyquist frequency of the
output samples is less than the Nyquist frequency of the input
samples. To move the cutoff frequency of the antialiasing filter,
the coefficients are dynamically altered and the length of the
convolution is increased by a factor of fS_IN/fS_OUT. This tech-
nique is supported by the Fourier transform property that if f(t)
is F(ω), then f(k × t) is F(ω/k). Thus, the range of decimation is
simply limited by the size of the RAM.
IN
INTERPOLATE
BY N
LOW-PASS
FILTER
ZERO-ORDER
HOLD
OUT
fS_IN
fS_OUT
FREQUENCY DOMAIN OF SAMPLES AT fS_IN
fS_IN
20
FREQUENCY DOMAIN OFTHE INTERPOLATION
2
ꢂ fS_IN
THE SAMPLE RATE CONVERTER ARCHITECTURE
The architecture of the sample rate converter is shown in
Figure 7. The sample rate converter’s FIFO block adjusts the
left and right input samples and stores them for the FIR filter’s
convolution cycle. The fS_IN counter provides the write address to
the FIFO block and the ramp input to the digital servo loop. The
ROM stores the coefficients for the FIR filter convolution and
performs a high order interpolation between the stored coefficients.
The sample rate ratio block measures the sample rate for dynami-
cally altering the ROM coefficients and scaling of the FIR filter
length as well as the input data. The digital servo loop automatically
tracks the fS_IN and fS_OUT sample rates and provides the RAM
and ROM start addresses for the start of the FIR filter convolution.
SIN(X)/X OF ZERO-ORDER HOLD
FREQUENCY DOMAIN OF fS_OUT RESAMPLING
20
ꢂ
2
fS_IN
20
FREQUENCY DOMAIN AFTER
RESAMPLING
2
ꢂ fS_IN
Figure 6. Frequency Domain of the Interpolation and
Resampling
ROM A
ROM B
RIGHT DATA IN
LEFT DATA IN
HIGH
FIFO
HARDWARE MODEL
ORDER
INTERP
The output rate of the low-pass filter of Figure 5 would be the
interpolation rate, 220 × 192000 kHz = 201.3 GHz. Sampling at
a rate of 201.3 GHz is clearly impractical, not to mention the
number of taps required to calculate each interpolated sample.
However, since interpolation by 220 involves zero-stuffing 220–1
samples between each fS_IN sample, most of the multiplies in
the low-pass FIR filter are by zero. A further reduction can be
realized by the fact that since only one interpolated sample is
taken at the output at the fS_OUT rate, only one convolution
needs to be performed per fS_OUT period instead of 220 convo-
lutions. A 64-tap FIR filter for each fS_OUT sample is sufficient
to suppress the images caused by the interpolation.
ROM C
ROM D
fS_IN
COUNTER
DIGITAL
SERVO LOOP
SAMPLE RATE RATIO
FIR FILTER
fS_IN
SAMPLE RATE
RATIO
L/R DATA OUT
fS_OUT
EXTERNAL
RATIO
Figure 7. Architecture of the Sample Rate Converter
The FIFO receives the left and right input data and adjusts the
amplitude of the data for both the soft muting of the sample rate
converter and the scaling of the input data by the sample rate
ratio before storing the samples in the RAM. The input data
is scaled by the sample rate ratio because as the FIR filter length
of the convolution increases, so does the amplitude of the convo-
lution output. To keep the output of the FIR filter from saturating,
the input data is scaled down by multiplying it by fS_OUT/fS_IN
when fS_OUT < fS_IN. The FIFO also scales the input data for
muting and unmuting the AD1895.
The difficulty with the above approach is that the correct inter-
polated sample needs to be selected upon the arrival of fS_OUT
.
Since there are 220 possible convolutions per fS_OUT period, the
arrival of the fS_OUT clock must be measured with an accuracy
of 1/201.3 GHz = 4.96 ps. Measuring the fS_OUT period with a
clock of 201.3 GHz frequency is clearly impossible; instead,
several coarse measurements of the fS_OUT clock period are made
and averaged over time.
Another difficulty with the above approach is the number of
coefficients required. Since there are 220 possible convolutions
with a 64-tap FIR filter, there needs to be 220 polyphase coeffi-
cients for each tap, which requires a total of 226 coefficients. To
reduce the number of coefficients in ROM, the AD1895 stores a
small subset of coefficients and performs a high order interpola-
tion between the stored coefficients. So far, the above approach
works for the case of fS_OUT > fS_IN. However, in the case when
the output sample rate, fS_OUT, is less than the input sample
The RAM in the FIFO is 512 words deep for both left and right
channels. A small offset of 16 is added to the write address
provided by the fS_IN counter to prevent the RAM read pointer
from ever overlapping the write address. The maximum deci-
mation rate can be calculated from the RAM word depth as
(512 – 16)/64 taps = 7.75 and a small offset.
REV. B
–17–
AD1895
10
0
–10
–20
–30
–40
SLOW MODE
–50
FAST MODE
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
–200
–210
–220
0.01
0.1
1
10
100
1e3
1e4
1e5
FREQUENCY – Hz
Figure 8. Frequency Response of the Digital Servo Loop. fS_IN is the x-axis, fS_OUT = 192 kHz, master clock
frequency is 30 MHz.
The digital servo loop is essentially a ramp filter that provides
the initial pointer to the address in RAM and ROM for the start
of the FIR convolution. The RAM pointer is the integer output
of the ramp filter, while the ROM is the fractional part. The
digital servo loop must be able to provide excellent rejection of
jitter on the fS_IN and fS_OUT clocks as well as measure the arrival
of the fS_OUT clock within 4.97 ps. The digital servo loop will
also divide the fractional part of the ramp output by the ratio of
fS_IN/fS_OUT for the case when fS_IN > fS_OUT, to dynamically alter
the ROM coefficients.
The FIR filter is a 64-tap filter in the case of fS_OUT ≥ fS_IN and is
(fS_IN/fS_OUT) × 64 taps for the case when fS_IN > fS_OUT. The FIR
filter performs its convolution by loading in the starting address
of the RAM address pointer and the ROM address pointer
from the digital servo loop at the start of the fS_OUT period.
The FIR filter then steps through the RAM by decrementing its
address by 1 for each tap, and the ROM pointer increments its
address by the (fS_OUT/fS_IN) × 220 ratio for fS_IN > fS_OUT or 220
for fS_OUT ≥ fS_IN. Once the ROM address rolls over, the con-
volution is completed. The convolution is performed for both
the left and right channels, and the multiply accumulate circuit
used for the convolution is shared between the channels.
The digital servo loop is implemented with a multirate filter. To
settle the digital servo loop filter quicker upon startup or a change
in the sample rate, a Fast Mode was added to the filter. When
the digital servo loop starts up or the sample rate is changed, the
digital servo loop kicks into Fast Mode to adjust and settle on the
new sample rate. Upon sensing the digital servo loop settling down
to some reasonable value, the digital servo loop will kick into
Normal or Slow Mode. During Fast Mode, the MUTE_OUT
signal of the sample rate converter is asserted to let the user
know that they should mute the sample rate converter to avoid
any clicks or pops. The frequency response of the digital servo
loop for Fast Mode and Slow Mode are shown in Figure 8.
The fS_IN/fS_OUT sample rate ratio circuit is used to dynamically
alter the coefficients in the ROM for the case when fS_IN > fS_OUT
The ratio is calculated by comparing the output of an fS_OUT
counter to the output of an fS_IN counter. If fS_OUT > fS_IN, the
.
ratio is held at 1. If fS_IN > fS_OUT, the sample rate ratio is updated
if it is different by more than two fS_OUT periods from the previous
fS_OUT to fS_IN comparison. This is done to provide some
hysteresis to prevent the filter length from oscillating and causing
distortion.
REV. B
–18–
AD1895
OPERATING FEATURES
RESET and Power-Down
Upon RESET, or a change in the sample rate between LRCLK_I
and LRCLK_O, the MUTE_OUT pin will be asserted high. The
MUTE_OUT pin will remain asserted high until the digital servo
loop’s internal Fast Settling Mode has completed. When the digital
servo loop has switched to Slow Settling Mode, the MUTE_OUT
pin will deassert. While MUTE_OUT is asserted, the MUTE_IN
pin should be asserted as well to prevent any major distortion in
the audio output samples.
When RESET is asserted low, the AD1895 will turn off the
master clock input to the AD1895, MCLK_IN, initialize all of its
internal registers to their default values, and three-state all of the
I/O pins. While RESET is active low, the AD1895 is consuming
minimum power. For the lowest possible power consumption
while RESET is active low, all of the input pins to the AD1895
should be static.
Master Clock
When RESET is deasserted, the AD1895 begins its initialization
routine where all locations in the FIFO are initialized to zero,
MUTE_OUT is asserted high, and any I/O pins configured as
outputs are enabled. The mute control counter, which controls
the soft mute attenuation of the input samples, is initialized to
maximum attenuation, –127 dB (see Mute Control section).
A digital clock connected to the MCLK_IN pin or a fundamental
or third overtone crystal connected between MCLK_IN and
MCLK_OUT can be used to generate the master clock, MCLK_IN.
The MCLK_IN pin can be 5 V input tolerant just like any of
the other AD1895 input pins. A fundamental mode crystal can
be inserted between MCLK_IN and MCLK_OUT for master
clock frequency generation up to 27 MHz. For master clock
frequency generation with a crystal beyond 27 MHz, it is recom-
mended that the user use a third overtone crystal and add an
LC filter at the output of MCLK_OUT to filter out the fundamental,
do not notch filter the fundamental. Please refer to your quartz
crystal supplier for values for external capacitors and inductor
components.
When asserting RESET and deasserting RESET, the RESET
should be held low for a minimum of five MCLK_IN cycles.
During power-up, the RESET should be held low until the power
supplies have stabilized. It is recommended that the AD1895 be
reset when changing modes.
Power Supply and Voltage Reference
The AD1895 is designed for 3 V operation with 5 V input toler-
ance on the input pins. VDD_CORE is the 3 V supply that is used
to power the core logic of the AD1895 and to drive the output
pins. VDD_IO is used to set the input voltage tolerance of the
input pins. In order for the input pins to be 5 V input tolerant,
VDD_IO must be connected to a 5 V supply. If the input pins do
not have to be 5 V input tolerant, then VDD_IO can be connected
to VDD_CORE. VDD_IO should never be less than VDD_CORE.
VDD_CORE and VDD_IO should be bypassed with 100 nF
ceramic chip capacitors as close to the pins as possible to minimize
power supply and ground bounce caused by inductance in the
traces. A bulk aluminium electrolytic capacitor of 47 µF should
also be provided on the same PC board as the AD1895.
AD1895
MCLK_IN
MCLK_OUT
R
C1
C2
Figure 9a. Fundamental Mode Circuit Configuration
Digital Filter Group Delay
The filter group delay is given by the equation:
AD1895
MCLK_IN
MCLK_OUT
R
16
fS _ IN
32
fS _ IN
GD =
GD =
+
+
seconds for fS _OUT > fS _ IN
fS _ IN
16
fS _ IN
32
×
seconds for fS _OUT < fS _ IN
f
f
S _ IN
S _OUT
1nF
L1
C1
C2
Mute Control
When the MUTE_IN pin is asserted high, the MUTE_IN control
will perform a soft mute by linearly decreasing the input data to the
AD1895 FIFO to almost zero, –127 dB attenuation. When
MUTE_IN is deasserted low, the MUTE_IN control will linearly
decrease the attenuation of the input data to 0 dB. A 12-bit counter,
clocked by LRCLK_I, is used to control the mute attenuation.
Therefore, the time it will take from the assertion of MUTE_IN
to –127 dB full mute attenuation is 4096/LRCLK_I seconds.
Likewise, the time it will take to reach 0 dB mute attenuation from
the deassertion of MUTE_IN is 4096/LRCLK_I seconds.
Figure 9b. Third Overtone Circuit Configuration
There are, of course, maximum and minimum operating fre-
quencies for the AD1895 master clock. The maximum master
clock frequency at which the AD1895 is guaranteed to operate is
30 MHz. 30 MHz is more than sufficient to sample rate convert
sampling frequencies of 192 kHz + 12%. The minimum required
frequency for the master clock generation for the AD1895 depends
upon the input and output sample rates. The master clock has
to be at least 138 times greater than the maximum input or
output sample rate.
REV. B
–19–
AD1895
Serial Data Ports—Data Format
Table III. When the output word width is less than 24 bits, dither is
added to the truncated bits. The Right-Justified Serial Data Out
Mode assumes 64 SCLK_O cycles per frame, divided evenly
for left and right. The AD1895 also supports 16-bit, 32-clock
packed input and output serial data in LJ, RJ, and I2S format.
The Serial Data Input Port Mode is set by the logic levels on the
SMODE_IN_0/SMODE_IN_1/SMODE_IN_2 pins. The serial
data input port modes available are left justified, I2S, and right
justified (RJ), 16, 18, 20, or 24 bits, as defined in Table I.
Table I. Serial Data Input Port Mode
SMODE_IN_[0:2]
Table II. Serial Data Output Port Mode
SMODE_OUT_[0:2]
1
0
Interface Format
Interface Format
2
1
0
0
0
1
1
0
1
0
1
Left Justified (LJ)
I2S
TDM Mode
Right Justified (RJ)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Left Justified
I2S
Undefined
Undefined
Right Justified, 16 Bits
Right Justified, 18 Bits
Right Justified, 20 Bits
Right Justified, 24 Bits
Table III. Word Width
WLNGTH_OUT_[0:1]
1
0
Word Width
The Serial Data Output Port Mode is set by the logic levels on the
SMODE_OUT_0/SMODE_OUT_1 and WLNGTH_OUT_0/
WLNGTH_OUT_1 pins. The serial mode can be changed to left
justified, I2S, right justified, or TDM as defined in the Table II. The
output word width can be set by using the WLNGTH_OUT_0/
WLNGTH_OUT_1 pins as shown in
0
0
1
1
0
1
0
1
24 Bits
20 Bits
18 Bits
16 Bits
The following timing diagrams show the serial mode formats.
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
SCLK
LSB
MSB
LEFT-JUSTIFIED MODE – 16 BITSTO 24 BITS PER CHANNEL
MSB
LSB
SDATA
LRCLK
SCLK
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
MSB
LSB
SDATA
2
I S MODE – 16 BITSTO 24 BITS PER CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
SCLK
MSB
LSB
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
MSB
LSB
SDATA
LRCLK
SCLK
LSB
MSB
LSB
MSB
SDATA
TDM MODE – 16 BITSTO 24 BITS PER CHANNEL
1/fs
NOTES
1. LRCLK NORMALLY OPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY (fs)
2. SCLK FREQUENCY IS NORMALLY 64 ꢂ LRCLK EXCEPT FOR TDM MODE,WHICH IS N ꢂ 64 ꢂ fs,
WHERE N = NUMBER OF STEREO CHANNELS INTHE TDM CHAIN. IN MASTER MODE, N = 4
Figure 10. Input/Output Serial Data Formats
REV. B
–20–
AD1895
TDM MODE APPLICATION
of the next AD1895, a large shift register is created and is
clocked by SCLK_O.
In TDM Mode, several AD1895s can be daisy-chained together
and connected to the serial input port of a SHARC® DSP. The
AD1895 contains a 64-bit parallel load shift register. When the
LRCLK_O pulse arrives, each AD1895 parallel loads its left and
right data into the 64-bit shift register. The input to the shift
register is connected to TDM_IN, while the output is connected
to SDATA_O. By connecting the SDATA_O to the TDM_IN
The number of AD1895s that can be daisy-chained together is
limited by the maximum frequency of SCLK_O, which is about
25 MHz. For example, if the output sample rate, fS, is 48 kHz,
up to eight AD1895s could be connected since 512 × fS is less
than 25 MHz. In Master/TDM Mode, the number of AD1895s
that can be daisy-chained is fixed to four.
LRCLK
SCLK
SHARC
DSP
AD1895
AD1895
AD1895
DR0
TDM_IN
SDATA_O
TDM_IN
SDATA_O
TDM_IN
SDATA_O
RFS0
LRCLK_O
SCLK_O
LRCLK_O
SCLK_O
LRCLK_O
SCLK_O
RCLK0
SLAVE-1
SLAVE-2
SLAVE-n
M2
0
M1
M0
0
M2
0
M1
M0
0
M2
0
M1
M0
0
STANDARD MODE
0
0
0
Figure 11. Daisy-Chain Configuration for TDM Mode (All AD1895s Being Clock-Slaves)
SHARC
DSP
AD1895
AD1895
AD1895
DR0
TDM_IN
SDATA_O
LRCLK_O
SCLK_O
TDM_IN
SDATA_O
TDM_IN
SDATA_O
RFS0
LRCLK_O
SCLK_O
LRCLK_O
SCLK_O
RCLK0
SLAVE-n
CLOCK-MASTER
SLAVE-1
M2
M1
M0
M2
0
M1
M0
0
M2
0
M1
M0
0
STANDARD MODE
0
0
1
1
0
Figure 12. Daisy-Chain Configuration for TDM Mode (First AD1895 Being Clock-Master)
SHARC is a registered trademark of Analog Devices, Inc.
REV. B
–21–
AD1895
Serial Data Port Master Clock Modes
Table IV. Serial Data Port Clock Modes
MMODE_0/
MMODE_1/
MMODE_2
Either of the AD1895 serial ports can be configured as a
master serial data port. However, only one serial port can be
a master, while the other has to be a slave. In Master Mode, the
AD1895 requires a 256 × fS, 512 fS, or 768 × fS master clock
(MCLK_IN). For a maximum master clock frequency of 30 MHz,
the maximum sample rate is limited to 96 kHz. In Slave Mode,
sample rates up to 192 kHz can be handled.
2
1
0
Interface Format
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Both Serial Ports Are in Slave Mode
Output Serial Port Is Master with 768 × fS_OUT
Output Serial Port Is Master with 512 × fS_OUT
Output Serial Port Is Master with 256 × fS_OUT
Undefined
Input Serial Port Is Master with 768 × fS_IN
Input Serial Port Is Master with 512 × fS_IN
Input Serial Port Is Master with 256 × fS_IN
When either of the serial ports is operated in Master Mode, the
master clock is divided down to derive the associated left/right
subframe clock (LRCLK) and serial bit clock (SCLK). The master
clock frequency can be selected for 256, 512, or 768 times the
input or output sample rate. Both the input and output serial
ports will support Master Mode LRCLK and SCLK generation
for all serial modes, left justified, I2S, right justified, and TDM
for the output serial port.
Bypass Mode
When the BYPASS pin is asserted high, the input data bypasses
the sample rate converter and is sent directly to the serial output
port. Dithering of the output data when the word length is set
to less than 24 bits is disabled. This mode is ideal when the
input and output sample rates are the same and LRCLK_I and
LRCLK_O are synchronous with respect to each other. This
mode can also be used for passing through nonaudio data,
since no processing is performed on the input data in this mode.
REV. B
–22–
AD1895
OUTLINE DIMENSIONS
28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
10.50
10.20
9.90
28
15
5.60 8.20
5.30 7.80
5.00 7.40
PIN 1
14
1
1.85
1.75
1.65
0.10
COPLANARITY
2.00 MAX
0.25
0.09
8ꢀ
4ꢀ
0ꢀ
0.95
0.75
0.55
0.65
BSC
0.38
0.22
0.05
MIN
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-150AH
REV. B
–23–
AD1895
Revision History
Location
Page
9/02—Data Sheet changed from REV. A to REV. B.
Changes to SPECIFICATIONS (Digital Performance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Changes to SPECIFICATIONS (Digital Timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Replaced TPCs 1–52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Additions to RESET and Power-Down section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Changes to Figures 9a and 9b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Additions to Serial Data Ports––Data Format section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
–24–
REV. B
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