RT8801BPQV [RICHTEK]
Multi-Phase PWM Controller for K8 CPU Core Power Supply with Serial Programming Interface; 对于K8 CPU内核电源多相PWM控制器，串行编程接口
| 型号： | RT8801BPQV |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | Multi-Phase PWM Controller for K8 CPU Core Power Supply with Serial Programming Interface |
| 文件： | 总23页 (文件大小：491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
RT8801B
Multi-Phase PWM Controller for K8 CPU Core Power
Supply with Serial Programming Interface
General Description
Features
z Multi-Phase Power Conversion with Automatic
The RT8801B is a multi-phase synchronous buck controller
which is implemented with full control functions for AMD
K8 compliant CPU. The RT8801B could be operated with
2, 3 or 4 buck switching stages operating in interleaved
phase set automatically. The multiphase architecture
provides high output current while maintaining low power
dissipation on power devices and low stress on input and
output capacitors.
Phase Selection
z 6-bits AMD K8 DAC Output with Active Droop
Compensation for Fast Load Transient
z Smooth VCORE Transition at VID Jump
z Power Stage Thermal Balance by DCR Current
Sense
z Hiccup Mode Over-Current Protection
z Adjustable Switching Frequency (50kHz to 400kHz
per Phase)
RT8801B is one of RichTek CPU core power solutions
which integrates a specific series programming interface
for the controller peration configuration. There are several
registers implemented for the specific parameters
configuration including VID for core power, and signal for
load current indication. User can program the configuration
of the parameters easily via the specific programming
interface. With the implementation of RT8801B, the part
provides more flexibility and feature for customers advanced
segment product design.
z Under-Voltage Lockout and Soft-Start
z High Ripple Frequency Times Channel Number
z 2-Wires Programming Interface
z Software Programmable VID
z 32-Lead VQFN Package
z RoHS Compliant and 100% Lead (Pb)-Free
Applications
z AMD K8 compliant Processors Voltage Regulator
z Low Output Voltage, High power density DC-DC
Converters
The RT8801B applies theDCR sensing technology newly
as well; with such a topology, the RT8801B extracts the
DCR of output inductor as sense component to deliver a
more precise load line regulation and better thermal
balance for next generation processor application. For
current sense setting, droop tuning, VCORE initial offset
and over current protection are independent to
compensation circuit of voltage loop. The feature greatly
facilitates the flexibility of CPU power supply design and
tuning. The DAC output of RT8801B supports AMD CPU
with 6-bit VID input, precise initial value & smooth VCORE
transient at VID jump. The IC monitors the VCORE voltage
for over-voltage protection. Soft-start, over-current
protection and programmable under-voltage lockout are
also provided to assure the safety of microprocessor and
power system. The RT8801B comes to the package of
VQFN-32L 5x5.
z Voltage Regulator Modules
Ordering Information
RT8801B
Package Type
QV : VQFN-32L 5x5 (V-Type)
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
Note :
Richtek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
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1
Preliminary
RT8801B
Pin Configurations
(TOP VIEW)
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
SLOT_OCC
DATA
1
2
3
4
5
6
7
8
PWM3
PWM2
PWM1
CSP1
CSP2
CSP3
CSP4
ADJ
CLK
RST
AD_SEL
GND
GND
IC_OUT
FB
33
9
10 11 12 13 14 15 16
VQFN-32L 5x5
Registers
0x00 Hi-I setting registers; Default 0x00
Bit4-0 :
Bit4 Bit3 Bit2 Bit1 Bit0 VID Offset (mV)
Bit4 Bit3 Bit2 Bit1 Bit0 VID Offset (mV)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
400
425
450
475
500
525
550
575
600
625
650
675
700
725
750
800
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
25
50
75
100
125
150
175
200
225
250
275
300
325
350
375
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DS8801B-04 August 2007
Preliminary
RT8801B
0x01 Core Current. Default 0x00 (read only). The core current full scale is over current trigger point.
Bit6-0 : Show core voltage current.
0x03 MISC. Default 0x04.
Bit2 : Slot_OCC Detection. This bit be written clear and only can be written 0.
0 : Normal 1 : Slot_OCC ever be pulled high
Bit1 : The reset pin ever be pull low when bit0 = 1 and only can be written 0.
0 : Never issue reset 1 : Ever issue reset
Bit0 : Reset control. When this bit be write 1, the WatchingDog timer (Reset pin) will repeat counter 1400ms then pull
low 200ms.Reset pin be pull low, if this bit = 1 will reset all registers to default exception MISC(Index 0x03).
0 : Disable 1 : Enable
Note : If SLOT_OCC pin = 1 reset all registers value to default.
RST enable
0x03 bit 0
T
delay
7 x T
delay
WD Timer
RST
Product information registers (Read Only)
0x13 Revision_ID
0x00
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3
Preliminary
RT8801B
Typical Application Circuit
CSN
RT
PWM4
VDD
VID4
VID3
VID2
VID1
VID0
VID5
VID4
VID3
VID2
VID1
PGOOD
SS
DVD
VOSS
VID0
VID5
SGND
COMP
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4
DS8801B-04 August 2007
Preliminary
RT8801B
Functional Pin Description
SLOT_OCC (Pin 1)
pin; the internal trip threshold = 0.9V at VDVD rising.
CPU socket occupied; the signal is defined to indicate if
the CPU has been changed/ removed and it will reset all
chip. There is one register implemented for the status
indication. The register will be reset when the VDD power
removed or CPU changed/removed. The pin is
implemented as an input, TTL level, and active-low signal.
SS (Pin 13)
The pin is defined to set soft-start ramp rate; a capacitor
is attached to set the start time interval. Pull this pin lower
than 1.0V (ramp valley of saw-tooth wave in pulse width
modulator) will shut the converter down.
PGOOD (Pin 14)
DATA (Pin 2), CLK (Pin 3)
PowerGood Indication. PGOODis an open drain output.
PGOODwill go high impedance when SS voltage greater
than 3.7V and no fault occurs.
2-wires programming interface.
RST (Pin 4)
This pin be pull low (the Watching Dog = Low), it will
reset some register, when 0x03 bit 0 be setting.
RT (Pin 15)
Default operation switching frequency setting. A resistor
is attached to set the default operation frequency.
AD_SEL (Pin 5)
The pin select series bus address. Pin =1,Address = 0x5E
& Pin = 0, Address = 0x5C.
CSN (Pin 16)
The pin is defined to sense load current of CPU. The pin
should be connected to the output node of choke.
GND (Pin 6)
Chip power ground.
ADJ (Pin 17)
Pin for active droop adjustment. An external resistor is
attached to GND for load droop setting.
IC_OUT (Pin 7)
The pin is defined as a reference current output.Acapacitor
is attached to set the default Watching Dog low pluse
time. Write the index 0x03 bit0 = 1 delay 7 times Tdelay
time then issue Tdelay low pluse,
CSP1 (Pin 21), CSP2 (Pin 20), CSP3 (Pin 19),
CSP4 (Pin 18)
Current sense inputs from the individual converter
channels.
COUT
ICOUT
where Tdelay
=
× VCOUT
FB (Pin 8)
PWM1 (Pin 22), PWM2 (Pin 23), PWM3 (Pin 24),
PWM4 (Pin 25)
The pin is defined as an inverting input of internal error
amplifier.
PWM outputs for each phase switching drive.
COMP (Pin 9)
VDD (Pin 26)
The pin is defined as an output of the error amplifier and an
input of the PWM comparator.
Chip powers supply. Connect this pin to a 5VSB or VCC5
supply.
SGND (Pin 10)
VID4 (Pin 27), VID3 (Pin 28), VID2 (Pin 29),
VID1 (Pin 30), VID0 (Pin 31), VID5 (Pin 32)
Difference ground sense of VCORE
.
DAC voltage identification. The pins are internally pulled
VOSS (Pin 11)
to 1.2V (pull high 50μA) if left open.
VCORE initial value offset. Connect this pin to GND with a
resistor to set the offset value.
GND (Exposed Pad (33)]
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
DVD (Pin 12)
Hardware adjustable system power UVLO detection; input
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5
Preliminary
RT8801B
Function Block Diagram
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6
DS8801B-04 August 2007
Preliminary
RT8801B
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
1.1500
1.1250
1.1000
1.075
1.050
1.025
1.0000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
0.775
0.7625
0.7500
To be continued
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7
Preliminary
RT8801B
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID4
VID3
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
Note: (1) 0 : Connected to GND
(2) 1 : Open
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DS8801B-04 August 2007
Preliminary
Absolute Maximum Ratings (Note 1)
RT8801B
z Supply Voltage, VDD --------------------------------------------------------------------------------------------- 7V
z Input, Output or I/O Voltage ------------------------------------------------------------------------------------ GND-0.3V to VDD+ 0.3V
z PowerDissipation, PD @ TA = 25°C
VQFN-32L5x5 ---------------------------------------------------------------------------------------------------- 2.78W
z Package Thermal Resistance (Note 4)
VQFN-32L 5x5, θJA ----------------------------------------------------------------------------------------------- 36°C/W
z Junction Temperature -------------------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.)---------------------------------------------------------------------- 260°C
z Storage Temperature Range ----------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) --------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 3)
z Supply Voltage, VDD --------------------------------------------------------------------------------------------- 5V 10%
z Ambient Temperature Range----------------------------------------------------------------------------------- 0°C to 70°C
z Junction Temperature Range----------------------------------------------------------------------------------- 0°C to 125°C
Electrical Characteristics
(VDD = 5V, TA = 25°C, unless otherwise specified)
Parameter
VDD Supply Current
Symbol
Test Conditions
Min
Typ
Max Units
Nominal Supply Current
Power-On Reset
POR Threshold
Hysteresis
PWM 1,2,3,4 Open
--
12
16
mA
I
DD
4.0
0.2
0.8
--
4.2
0.5
0.9
70
4.5
--
V
V
V
V
V
V
V
DD
Rising
DDRTH
DDHYS
DVDTP
DVDHYS
Trip (Low to High)
Hysteresis
Enable
1.0
--
V
V
DVD
Threshold
mV
Oscillator
Free Running Frequency
Frequency Adjustable Range
Ramp Amplitude
250
50
--
300
--
350
400
--
kHz
kHz
V
f
R
R
= 22.5kΩ
OSC
RT
RT
f
OSC_ADJ
1.9
1.0
66
ΔV
= 22.5kΩ
OSC
Ramp Valley
0.7
62
1.7
--
V
V
RV
Maximum On-Time of Each Channel
RT Pin Voltage
75
1.9
%
1.8
V
V
R
= 22.5kΩ
≥ 1V
RT
RT
Reference and DAC
--
--
--
--
+1
+10
0.8
--
%
mV
V
−1
−10
--
V
V
DAC
DACOUT Voltage Accuracy
ΔV
DAC
< 1V
DAC
DAC (VID0-VID5) Input Low
DAC (VID0-VID5) Input High
V
V
ILDAC
V
1.4
IHDAC
To be continued
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9
Preliminary
RT8801B
Parameter
Symbol
Test Conditions
Min
−3
Typ
--
Max
3
Units
%
Offset Voltage
VOSS Pin Voltage
Error Amplifier
1.6
1.7
1.8
V
VVOSS
RVOSS = 100kΩ
DC Gain
--
--
--
85
10
3
--
--
--
dB
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/μs
COMP = 10pF
Current Sense GM Amplifier
CSN Full Scale Source Current
CSN Current for OCP
Protection
150
--
--
--
--
μA
μA
IISPFSS
150
SS Current
8
13
18
μA
ISS
VSS = 1V
VSEN
Over-Voltage Trip
130
140
150
%
ΔOVT
VDACOUT + VOFFSET
Delay Time
--
--
200
--
--
ms
ms
WD Timer, TDL (CL = 100nF)
WD Timer, TDH (CL = 100nF)
Power Good
1400
Output Low Voltage
--
--
0.2
V
VPGOODL IPGOOD = 4mA
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
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DS8801B-04 August 2007
Preliminary
Typical Operating Characteristics
RT8801B
Linearity of each PWM
Adjustable Frequency
3
2.8
2.6
2.4
2.2
2
450
400
350
300
250
200
150
100
50
PWM2
PWM3
PWM1
PWM4
1.8
1.6
1.4
1.2
1
fOSC = 200k
0
0
500
1000 1500 2000 2500 3000 3500
Pulse Width (ns)
0
20
40
60
80
100
120
R
RT (kΩ)
Load Transient Response
Load Transient Response
VCORE
VCORE
Phase1
Phase2
Phase
CH1: (500mV/Div)
IOUT
VADJ
CH2: (10V/Div)
CH3: (50A/Div)
CH4: (100mV/Div)
Phase3
CH1: (500mV/Div), CH2: (10V/Div)
CH3: (10V/Div), CH4: (10V/Div)
Time (5μs/Div)
Time (5μs/Div)
Relationship Between Inductor
Current and VADJ
Power-Off @ IOUT = 60A
CH1:(5V/Div)
CH2:(5V/Div)
PWM
PWM
CH1:(5V/Div)
CH2:(20V/Div)
VSS
UGATE
CH3:(10V/Div)
CH4:(1V/Div)
VADJ
LGATE
VCOMP
CH3:(50mV/Div)
CH4:(20A/Div)
IL
Time (10μs/Div)
Time (25ms/Div)
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11
Preliminary
RT8801B
Power-On @ IOUT = 60A
CH1:(5V/Div)
CH2:(5V/Div)
VSS
PWM
UGATE
LGATE
CH3:(20V/Div)
CH4:(10V/Div)
Time (10ms/Div)
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DS8801B-04 August 2007
Preliminary
RT8801B
Application Information
voltage positioning” can reduce the output voltage ripple
at load transient and the LC filter size.
RT8801B is a multi-phaseDC/DC controller that precisely
regulates CPU core voltage and balances the current of
different power channels. The converter consisting of
RT8801B and its companion MOSFET driver RT9607/
RT9607A provides high quality CPUpower and all
protection functions to meet the requirement of modern
VRM.
Fault Detection
The chip detects FB for over voltage. The “hiccup mode”
operation of over current protection is adopted to reduce
the short circuit current. The inrush current at the start up
is suppressed by the soft start circuit through clamping
the pulse width and output voltage.
Voltage Control
RT8801B senses the CPU VCORE by SGND pin to sense
the return of CPU to minimize the voltage drop on PCB
trace at heavy load. OVP is sensed at FB pin. The internal
high accuracy VIDDAC provides the reference voltage for
AMD K8 compliance. Control loop consists of error
amplifier, multi-phase pulse width modulator, driver and
power components. As conventional voltage mode PWM
controller, the output voltage is locked at the VREF of error
amplifier and the error signal is used as the control signal
of pulse width modulator. The PWM signals of different
channels are generated by comparison of EA output and
split-phase sawtooth wave. Power stage transforms VIN
to output by PWM signal on-time ratio.
Phase Setting and Converter Start Up
RT8801B interfaces with companion MOSFET drivers (like
RT9619, RT9607 series) for correct converter initialization.
The tri-state PWM output (high, low and high impedance)
senses its interface voltage when IC POR acts (both VDD
andDVDtrip). The channel is enabled if the pin voltage is
1.2V less than VDD. Tie the PWM to VDD and the
corresponding current sense pins to GND or left float if
the channel is unused. For example, for 3-Channel
application, connect PWM4 high.
Current Sensing Setting
RT8801B senses the current flowing through inductor via
itsDCR for channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal circuit
(see Figure 1).
Current Balance
RT8801B senses the inductor current via inductor'sDCR
for channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal balance
circuit.
VC
L
= R× C VC = DCR×IL IX
=
DCR
RCSN
The current balance circuit sums and averages the current
signals and then produces the balancing signals injected
to pulse width modulator. If the current of some power
channel is larger than average, the balancing signal
reduces that channels pulse width to keep current balance.
The use of singleGM amplifier via time sharing technique
to sense all inductor currents can reduce the offset errors
and linearity variation between GMs. Thus it can greatly
improve signal processing especially when dealing with
such small signal as voltage drop across DCR.
L
DCR
+ V
-
C
R
C
+
-
R
CSN
GMx
I
x
Figure 1. Current Sense Circuit
Figure 2 is the test circuit for GM. We apply test signal at
GM inputs and observe its signal process output at ADJ
pin. Figure 3 shows the variation of signal processing of
all channels. We observe zero offsets and good linearity
between phases.
Load Droop
The sensed power channel current signals regulate the
reference of DAC to form an output voltage droop
proportional to the load current. The droop or so call “active
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13
Preliminary
RT8801B
L
DCR
Over Current Protection
RT8801B uses an external resistor RCSN to set a
programmable over current trip point. OCP comparator
compares each inductor current with this reference current.
RT8801B uses hiccup mode to eliminate fault detection
of OCP or reduce output current when output is shorted
to ground.
ESR
R
V
X
V
V
CSP
+
CSN
-
CSN
GMx
1k
I
OCP Comparator
x
I
+
-
X
Figure 2. The Test Circuit of GM
150uA
Figure 5. Over Current Comparator
GM
300
250
200
150
100
50
Over Current Protection
PWM
CH1:(5V/Div)
CH2:(2V/Div)
CH3:(1V/Div)
VSS
0
VCORE
0
20
40
60
80
100
120
140
VX (mV)
Figure 3. The Linearity of GMx
Time (25ms/Div)
Figure 6. Over Current Protection at steady state
Figure 4 shows the time sharing technique ofGM amplifier.
We apply test signal at phase 4 and observe the waveforms
at both pins of GM amplifier. The waveforms show time
sharing mechanism and the perfomance of GM to hold
both input pins equal when the shared time is on.
Current Ratio Setting
Time Sharing of GM
CH1:(2V/Div)
CH2:(50mV/Div)
CH3:(50mV/Div)
PWM3
Figure 7. Application circuit for current ratio setting
VCSP4
For some case with preferable current ratio instead of
current balance, the corresponding technique is provided.
Due to different physical environment of each channel, it
is necessary to slightly adjust current loading between
channels. Figure 7 shows the application circuit ofGM for
current ratio requirement. Applying KVL along L+DCR
branch and R1+C//R2 branch:
VCSP4
and
VCSN
VCSN
Time (1μs/Div)
Figure 4
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DS8801B-04 August 2007
Preliminary
RT8801B
Current Ratio Function
dIL
dt
VC
R2
dVC
dt
35
L
+DCR×IL = R1(
dVC R1 +R2
+ C
)+ VC
IL4
30
25
20
15
10
5
= R1C
+
VC
dt
R2
R2
R1 +R2
For VC
=
DCR×IL
IL3
IL2
IL1
Look for its corresponding conditions:
dI
L
dI
L
L
+DCR×I = (R1//R2)×C×DCR×
+DCR×I
L
L
dt
dt
L
Let
= (R1//R2)×C
DCR
0
0
15
30
45
60
75
90
L
Thus if
Then
= (R1//R2)×C
IOUT (A)
DCR
R2
Figure 10
Current Balance Function
VC
=
×DCR×IL
R1+R2
25
20
15
10
5
With internal current balance function, this phase would
share (R1+R2)/R2 times current than other phases.
Figure 8 & 9 show different settings for the power stages.
Figure 10 shows the performance of current ratio compared
with conventional current balance function in Figure 11.
IL1
IL4
IL2
IL3
0
-5
0
20
40
60
80
100
IOUT (A)
Figure 8. GM4 Setting for current ratio function
Figure 11
L
DCR
C
ESR
V
V
CSP
CSN
R
+
-
Figure 9. GM1~3 Setting for current ratio function
CSN1
GMx
Ix
R
CSN2
Figure 12. Application circuit of GM
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15
Preliminary
RT8801B
For load line design, with application circuit in Figure 12,
it can eliminate the dead zone of load line at light loads.
VID on the Fly
With external pull up resistors tied to VID pins, RT8801B
converters different VID codes from CPU into output
voltage. Figure 14 and Figure 15 show the waveforms of
VID on the fly function.
VCSP = VOUT +IL x DCR
if GM holds input voltages equal, then
VCSP = VCSN
VCSN IL ×DCR
VID on the Fly (Falling)
IX
=
=
+
RCSN2
RCSN1
VOUT + IL ×DCR IL ×DCR
PWM
VCORE
+
RCSN2
RCSN1
VFB
VOUT IL DCR IL DCR
×
×
=
+
+
RCSN2
RCSN2
RCSN1
CH3:(500mV/Div)
CH4:(1V/Div)
CH1:(5V/Div)
CH2:(500mV/Div)
For the lack of sinking capability of GM, RCSN2 should be
small enough to compensate the negative inductor valley
current especially at light loads.
VID5
VDAC = 1.500, IOUT = 5A
VCSN
IL ×DCR
≥
RCSN2
RCSN1
Time (25μs/Div)
Figure 14
Assume the negative inductor valley current is −5A at no
load, then for
VID on the Fly (Rising)
RCSN1 = 330Ω, RADJ = 160Ω, VOUT = 1.300V
1.3V
- 5A ×1mΩ
330Ω
≥
PWM
R
CSN2
VCORE
RCSN2 ≤ 85.8kΩ
VFB
Choose RCSN2 = 82kΩ
CH1:(5V/Div)
CH2:(500mV/Div)
CH3:(500mV/Div)
CH4:(1V/Div)
Load Line without dead zone at light loads
1.31
VID5
1.3
VDAC = 1.500, IOUT = 5A
1.29
1.28
1.27
1.26
1.25
1.24
1.23
Time (25μs/Div)
Figure 15
RCSN2 open
RCSN2 = 82k
1/4 I
VOSS
RB1
-
EA
+
0
5
10
15
20
25
V
-V
DAC ADJ
IOUT (A)
Figure 13
Figure 16
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DS8801B-04 August 2007
Preliminary
RT8801B
Output Voltage Offset Function
EA Rising Slew Rate
To meet Intel® requirement of initial offset of load line,
RT8801B provides programmable initial offset function.
External resistor RVOSS and voltage source at VOSS pin
VVOSS
generate offset current
.
IVOSS
=
RVOSS
VFB
One quarter of IVOSS flows through RB1 as shown in Figure
16. Error amplifier would hold the inverting pin equal to
VDAC - VADJ. Thus output voltage is subtracted from VDAC
- VADJ for a constant offset voltage.
RFB1
4×RVOSS
CH1:(1V/Div)
CH2:(2V/Div)
VCOMP
VCORE = VDAC - VADJ
-
A positive output voltage offset is possible by connecting
RVOSS to VDD instead of to GND. Please note that when
RVOSS is connected to VDD, VVOSS is VDD − 2V typically
and half of IVOSS flows through RFB1. VCORE is rewritten as:
Time (250ns/Div)
Figure 18. EA Falling Transient with 10pF Loading;
Slew Rate = 8V/us
RFB1
RVOSS
VCORE = VDAC - VADJ
+
4.7k
4.7k
B
-
A
Error Amplifier Characteristic
EA
+
For fast response of converter to meet stringent output
current transient response, RT8801B provides large slew
rate capability and high gain-bandwidth performance.
V
REF
Figure 19. Gain-Bandwidth Measurement by signalA
divided by signal B
EA Falling Slew Rate
PGOOD Function
To indicate the condition of multiphase converter, RT8801
provides PGOODsignal through an open drain connection.
As shown in Figure 20. PGOOD pin is externally pulled
high when SS pin voltage higher than 3.7V and no fault
occurs.
VFB
VDD
CH1:(1V/Div)
VCOMP
CH4:(2V/Div)
R
PGOOD
Time (250ns/Div)
V
PGOOD
Figure 17. EA Rising Transient with 10pF Loading; Slew
Rate = 10V/us
SS > 3.7V
Figure 20
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17
Preliminary
RT8801B
where VRAMP : ramp amplitude of saw-tooth wave
LC Filter Pole = 1.45kHz and
Design Procedure Suggestion
a.Output filter pole and zero (Inductor, output capacitor
value & ESR).
ESR Zero = 3.98kHz
b.Error amplifier compensation & sawtooth wave amp-
litude (compensation network).
b. EA Compensation Network :
Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF and
use the Type 2 compensation scheme shown in
Figure 21. By calculation, the FZ = 0.88kHz, FP = 322kHz
and Middle Band Gain is 3.19 (i.e 10.07dB).
c.Kelvin sense for VCORE
.
Current Loop Setting
GM amplifier S/H current (current sense componentDCR,
CSN pin external resistor value).
C2 68pF
VRM Load Line Setting
C1
RB2
a.Droop amplitude (ADJ pin resistor).
15k
12nF
RB1
4.7k
-
b.No load offset (RCSN2
)
EA
+
c.DAC offset voltage setting (VOSS pin & compensation
network resistor RB1).
Figure 21. Type 2 compensation network of EA
Power Sequence & SS
The bode plot of EA compensation is shown as Figure 22.
DVD pin external resistor and SS pin capacitor.
The bode plot of power stage is shown as Figure 23. The
total loop gain is in Figure 24.
PCB Layout
a.Kelvin sense for current sense GM amplifier input.
2. Over-Current Protection Setting
Consider the temperature coefficient of copper
b.Refer to layout guide for other items.
3900ppm/°C,
Voltage Loop Setting
Design Example
IL ×DCR
= 150μA
RCSN
40A ×1.39mΩ
Given:
RCSN
=
150μA
Apply for four phase converter
RCSN = 370Ω
VIN = 12V
VCORE = 1.5V
ILOAD (MAX) = 100A
3. Soft-Start Capacitor Selection
For most application cases, 0.1μF is a good engineering
value.
VDROOP = 100mV at full load (1mΩ Load Line)
OCP trip point set at 40A for each channel (S/H)
DCR = 1mΩ of inductor at 25°C
L = 1.5μH
COUT = 8000μF with 5mΩ equivalent ESR.
1. Compensation Setting
a. Modulator Gain, Pole and Zero :
From the following formula :
Modulator Gain = VIN/VRAMP = 12/1.9 = 6.3 (i.e 16dB)
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DS8801B-04 August 2007
Preliminary
RT8801B
0dB
180°
Figure 22. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at
10.86MHz
0dB
-180°
Figure 23. The Frequency Response of the CompensatorNetwork
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19
Preliminary
RT8801B
0dB
-180°
Figure 24. The Frequency Response of Power Stage
0dB
-180°
Figure 25. The LoopGain of Converter
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20
DS8801B-04 August 2007
Preliminary
RT8801B
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes.
1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from
the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.
Kelvin connection of the sense component (additional sense resistor or Inductor DCR) ensures the accurate
stable current sensing.
Keep well Kelvin sense to ensure the stable operation!
2. Switching ripple current path:
a. Input capacitor to high side MOSFET.
b. Low side MOSFET to output capacitor.
c. The return path of input and output capacitor.
d. Separate the power and signalGND.
e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.
Keep them away from sensitive small-signal node.
f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via.
3. MOSFET driver should be closed to MOSFET.
4. The compensation, bypass and other function setting components should be near the IC and away from the noisy
power path.
L1
SW1
VOUT
VIN
RIN
COUT
RL
CIN
V
L2
SW2
Figure 26. Power Stage Ripple Current Path
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21
Preliminary
RT8801B
Next to IC
C
+12V or +5V
+12V
PWM
+5V
VDD
SB
0.1uF
VCC BOOT1
C
C
BP
RT
BOOT
VOSS
Next to IC
PVCC
COMP
UGATE1
SGND
L
O1
VCORE
C
PWM1 PHASE1
RT9607
RT8801B
C
OUT
R
CSN
C
IN
R
C
CSN
LGATE1
Kelvin
Sense
Locate next
to FB Pin
FB
GND
R
FB
CSPx
ADJ
Locate near MOSFETs
GND
For Thermal Couple
Figure 27. Layout Consideration
Figure 28
Figure 30
Figure 29
Figure 31
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DS8801B-04 August 2007
Preliminary
RT8801B
Outline Dimension
D
D2
SEE DETAIL A
L
1
E
E2
e
b
1
2
1
2
A
A3
DETAILA
A1
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A3
b
0.800
0.000
0.175
0.180
4.950
3.400
4.950
3.400
1.000
0.050
0.250
0.300
5.050
3.750
5.050
3.750
0.031
0.000
0.007
0.007
0.195
0.134
0.195
0.134
0.039
0.002
0.010
0.012
0.199
0.148
0.199
0.148
D
D2
E
E2
e
0.500
0.020
L
0.350
0.450
0.014
0.018
V-Type 32L QFN 5x5 Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
DS8801B-04 August 2007
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23
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