X9317TM8-2.7T2 [RENESAS]
100K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 100 POSITIONS, PDSO8, PLASTIC, MO-187AA, MSOP-8;
| 型号： | X9317TM8-2.7T2 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 100K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 100 POSITIONS, PDSO8, PLASTIC, MO-187AA, MSOP-8 光电二极管 转换器 电阻器 |
| 文件： | 总14页 (文件大小：702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X9317
FN8183
Rev.10.00
Dec 17, 2018
Low Noise, Low Power, 100 Taps, Digitally Controlled Potentiometer (XDCP™)
The X9317 is a digitally controlled potentiometer (XDCP™). The
Features
device consists of a resistor array, wiper switches, a control
section, and nonvolatile memory. The wiper position is
controlled by a 3-wire interface.
• Solid-state potentiometer
• 3-wire serial up/down interface
• 100 wiper tap points
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs. The
position of the wiper can be stored in nonvolatile memory and
then be recalled upon a subsequent power-up operation.
- Wiper position stored in nonvolatile memory and recalled
on power-up
• 99 resistive elements
- Temperature compensated
- End-to-end resistance range ±20%
The device can be used as a three-terminal potentiometer for
voltage control or as a two-terminal variable resistor for current
control in a wide variety of applications.
• Low power CMOS
- V = 2.7V to 5.5V, and 5V ±10%
CC
- Standby current <5µA
Applications
• LCD bias control
• High reliability
- Endurance, 100,000 data changes per bit
- Register data retention, 100 years
• DC bias adjustment
• R
TOTAL
values = 10kΩ, 50kΩ, 100kΩ
• Gain and offset trim
• Laser diode bias control
• Voltage regulator output control
• Packages
- 8 Ld SOIC, TSSOP, and MSOP
• Pb-free (RoHS compliant)
U/D
INC
R
99
H
UP/DOWN
COUNTER
V
(SUPPLY VOLTAGE)
CC
CS
98
97
96
R
R
UP/DOWN
(U/D)
H
7-BIT
NONVOLATILE
MEMORY
ONE
OF
ONE
CONTROL
AND
MEMORY
INCREMENT
(INC)
W
WIPER
SWITCHES
RESISTOR
ARRAY
HUNDRED
DECODER
DEVICE SELECT
(CS)
R
L
2
STORE AND
RECALL
CONTROL
CIRCUITRY
V
(GROUND)
1
0
SS
V
CC
SS
V
GENERAL
R
R
L
W
DETAILED
FIGURE 1. BLOCK DIAGRAM
FN8183 Rev.10.00
Dec 17, 2018
Page 1 of 14
X9317
Ordering Information
PART NUMBER
V
LIMITS
(V)
R
(kΩ)
TEMPERATURE
RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
CC
TOTAL
(Notes 1, 2, 3)
PART MARKING
X9317WM8Z
DCW
5 ±10%
10
0 to +70
-40 to +85
0 to +70
8 Ld MSOP
M8.118
X9317WM8IZ
X9317WS8Z
DCT
8 Ld MSOP
8 Ld SOIC
M8.118
M8.15E
M8.15E
M8.173
M8.173
M8.15E
M8.15E
M8.173
M8.173
M8.118
M8.118
M8.15E
M8.15E
M8.173
M8.173
M8.15E
M8.15E
M8.173
M8.173
X9317W Z
X9317W ZI
9317W Z
9317W IZ
X9317U Z
X9317U ZI
9317U Z
9317U IZ
DCX
X9317WS8IZ
X9317WV8Z
-40 to +85
0 to +70
8 Ld SOIC
8 Ld TSSOP
8 Ld TSSOP
8 Ld SOIC
X9317WV8IZ
X9317US8Z
-40 to +85
0 to +70
X9317US8IZ
-40 to +85
0 to +70
8 Ld SOIC
X9317UV8Z
8 Ld TSSOP
8 Ld TSSOP
8 Ld MSOP
8 Ld MSOP
8 Ld SOIC
X9317UV8IZ
-40 to +85
0 to +70
X9317WM8Z-2.7
X9317WM8IZ-2.7
X9317WS8Z-2.7
X9317WS8IZ-2.7
X9317WV8Z-2.7
X9317WV8IZ-2.7
X9317US8Z-2.7
X9317US8IZ-2.7
X9317UV8Z-2.7
X9317UV8IZ-2.7
NOTES:
2.7 to 5.5
10
DCU
-40 to +85
0 to +70
X9317W ZF
X9317W ZG
9317W FZ
AKZ
-40 to +85
0 to +70
8 Ld SOIC
8 Ld TSSOP
8 Ld TSSOP
8 Ld SOIC
-40 to +85
0 to +70
X9317U ZF
X9317U ZG
9317U FZ
9317U GZ
-40 to +85
0 to +70
8 Ld SOIC
8 Ld TSSOP
8 Ld TSSOP
-40 to +85
1. Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for X9317. For more information on MSL please see tech brief TB363.
FN8183 Rev.10.00
Dec 17, 2018
Page 2 of 14
X9317
Pin Configurations
Pin Descriptions
X9317
SOIC/MSOP
TSSOP
SYMBOL
BRIEF DESCRIPTION
(8 LD TSSOP)
TOP VIEW
1
3
INC
Increment Toggling INC while CS
is low moves the wiper either up
or down.
R
CS
1
2
3
4
8
7
6
5
L
V
2
3
4
5
U/D
Up/Down The U/D input controls
the direction of the wiper
movement.
R
V
CC
INC
U/D
W
SS
R
H
R
The high terminal is equivalent to
one of the fixed terminals of a
mechanical potentiometer.
H
X9317
(8 LD SOIC, 8 LD MSOP)
TOP VIEW
4
5
6
7
V
Ground
SS
R
The wiper terminal is equivalent
to the movable terminal of a
mechanical potentiometer.
W
V
INC
U/D
1
2
3
4
8
7
6
5
CC
6
7
8
1
The low terminal is equivalent to
one of the fixed terminals of a
mechanical potentiometer.
R
CS
L
R
L
R
H
V
R
SS
W
CS
Chip Select The device is
selected when the CS input is
LOW, and de-selected when CS is
high.
8
2
V
Supply Voltage
CC
FN8183 Rev.10.00
Dec 17, 2018
Page 3 of 14
X9317
Absolute Maximum Ratings
Thermal Information
I
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA
Thermal Resistance (Typical)
JA (°C/W)
115
JC (°C/W)
W
R , R , R to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
Voltage on CS, INC, U/D and V
SOIC Package (Notes 4, 5) . . . . . . . . . . . . .
MSOP Package (Notes 4, 5) . . . . . . . . . . . .
TSSOP Package (Notes 4, 5). . . . . . . . . . . .
Junction Temperature Under Bias . . . . . . . . . . . . . . . . . . . -65C to +135C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
60
55
49
H
W
L
145
155
CC
with Respect to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1V to +7V
SS
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. For , the “case temp” location is taken at the package top center.
JC
Potentiometer Specifications
V
= full range. Boldface limits apply across the operating temperature range, -40°C to +85°C
CC
(Industrial) and 0°C to +70°C (Commercial).
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS/NOTES
(Note 13) (Note 9) (Note 13)
UNIT
%
R
End-to-end Resistance Tolerance
See “Ordering Information” on page 2 for
values
-20 +20
TOTAL
V
/
R /R Terminal Voltage
V
= 0V
V
V
CC
V
mW
Ω
RH RL
H
L
SS
SS
Power Rating
R
≥ 10kΩ
10
TOTAL
R
Wiper Resistance
I
I
= [V(R ) - V(R )]/ R
, V = 5V
TOTAL CC
200
400
400
W
W
W
W
H
L
= [V(R ) - V(R )]/ R
, V = 2.7V
TOTAL CC
1000
+4.4
Ω
H
L
I
Wiper Current (Note 10)
Noise (Note 12)
See “Test Circuit” on page 5
Ref: 1kHz
-4.4
mA
dBV
%
-120
1
Resolution
Absolute Linearity (Note 6)
V(R ) = V , V(R ) = 0V
CC
-1
+1
MI
H
L
(Note 8)
Relative Linearity (Note 7)
V(R ) = V , V(R ) = 0V
CC
-0.2
+0.2
MI
H
L
(Note 8)
R
Temperature Coefficient (Note 10) V(R ) = V , V(R ) = 0V
CC
±300
±20
ppm/°C
ppm/°C
TOTAL
H
L
Ratiometric Temperature Coefficient
(Notes 10, 11)
C /C /C
W
Potentiometer Capacitances
See “Equivalent Circuit” on page 5
10/10/25
pF
H
L
(Note 10)
V
Supply Voltage
X9317
4.5
2.7
5.5
5.5
V
V
CC
X9317-2.7
FN8183 Rev.10.00
Dec 17, 2018
Page 4 of 14
X9317
DC Electrical Specifications
V
= 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C
CC
(Industrial) and 0°C to +70°C (Commercial).
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 13) (Note 9) (Note 13) UNIT
I
V
V
Active Current (Increment)
CS = V , U/D = V or V and INC = V /V at
80
µA
CC1
CC
IL
IL
IH
IL IH
min. t
CYC
R , R , R not connected
L
H
W
I
Active Current (Store)
CS = V , U/D = V or V and INC = V or V
IH IL IH IL
.
400
5
µA
µA
CC2
CC
IH
(non-volatile write)
R , R , R not connected
L H W
I
Standby Supply Current
CS V , U/D and INC = V
IH
SB
IL
R , R , R not connected
L
H
W
I
CS, INC, U/D Input Leakage Current
CS, INC, U/D Input HIGH Voltage
CS, INC, U/D Input LOW Voltage
V
= V to V
SS CC
-10
x 0.7
+10
µA
V
LI
IN
V
V
V
+ 0.5
IH
CC
CC
V
-0.5
V
x 0.1
V
IL
CC
C
(Note 10) CS, INC, U/D Input Capacitance
V
= 5V, V = V , T = +25°C, f = 1MHz
IN SS
10
pF
IN
CC
A
Endurance and Data Retention V = 5V ±10%, T = Full Operating Temperature Range.
CC
A
PARAMETER
Minimum Endurance
Data Retention
MIN
100,000
100
UNIT
Data changes per bit
Years
Test Circuit
Equivalent Circuit
AC Conditions of Test
Input pulse levels
0V to 3V
10ns
R
TOTAL
TEST POINT
R
L
Input rise and fall times
Input reference levels
R
H
C
L
C
W
C
1.5V
H
10pF
R
W
FORCE
25pF
CURRENT
10pF
R
W
AC Electrical Specifications
V
= 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C
CC
(Industrial) and 0°C to +70°C (Commercial).
MIN
TYP
MAX
SYMBOL
PARAMETER
(Note 13)
(Note 9)
(Note 13)
UNIT
t
CS to INC Setup
50
100
1
ns
ns
µs
ns
ns
µs
ms
ns
Cl
t
t
(Note 10)
(Note 10)
INC HIGH to U/D Change
U/D to INC Setup
INC LOW Period
lD
DI
t
960
960
1
lL
t
INC HIGH Period
lH
t
INC Inactive to CS Inactive
CS Deselect Time (STORE)
CS Deselect Time (NO STORE)
lC
t
10
CPHS
t
100
CPHNS
(Note 10)
t
INC to R Change
W
1
5
µs
µs
IW
t
INC Cycle Time
2
CYC
FN8183 Rev.10.00
Dec 17, 2018
Page 5 of 14
X9317
AC Electrical Specifications
V
= 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C
CC
(Industrial) and 0°C to +70°C (Commercial). (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
(Note 13)
(Note 9)
(Note 13)
UNIT
µs
t
t
INC Input Rise and Fall Time
500
R, F
(Note 10)
t
(Note 10)
Power-up to Wiper Stable
5
µs
PU
t
V
V
CC
Power-up Rate
0.2
50
V/ms
R
CC
(Note 10)
t
Store Cycle
5
10
ms
WR
NOTES:
6. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(R
)-V(R
)]/MI
W(n)(actual)
W(n)(expected)
V(R
) = n(V(R )-V(R ))/99 + V(R ), with n from 0 to 99.
W(n)(expected)
H L L
7. Relative linearity is a measure of the error in step size between taps = [V(R
W(n+1)
)-(V(R
W(n)
) - MI)]/MI.
8. 1 Ml = Minimum Increment = [V(R )-V(R )]/99.
H
L
9. Typical values are for T = +25°C and nominal supply voltage.
A
10. This parameter is not 100% tested.
6
11. Ratiometric temperature coefficient = (V(R
)
-V(R
)
)/[V(R (T1-T2) x 10 ], with T1 and T2 being 2 temperatures, and n from 0 to 99.
)
W T1(n)
W T2(n)
W T1(n)
12. Measured with wiper at tap position 99, R grounded, using test circuit.
L
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Power-up and Down
Requirements
The recommended power-up sequence is to apply V /V first,
CC SS
then the potentiometer voltages. During power-up, the data sheet
parameters for the DCP do not fully apply until 1ms after V
CC
reaches its final value. The V ramp spec is always in effect. In
CC
order to prevent unwanted tap position changes, or an
inadvertent store, bring the CS and INC high before or
concurrently with the V pin on power-up.
CC
FN8183 Rev.10.00
Dec 17, 2018
Page 6 of 14
X9317
AC Timing
CS
t
CYC
t
CPHNS
t
t
t
t
t
CPHS
CI
IL
IH
IC
90%
10%
90%
INC
U/D
t
t
t
t
R
ID
DI
F
t
IW
(3)
MI
R
W
Typical Performance Characteristic
0
-50
-100
-150
-200
-250
-300
-350
-55-45-35-25-15 -5
5
15 25 35 45 55 65 75 85 95 105115125
TEMPERATURE (°C)
FIGURE 2. TYPICAL TOTAL RESISTANCE TEMPERATURE COEFFICIENT
FN8183 Rev.10.00
Dec 17, 2018
Page 7 of 14
X9317
Pin Descriptions
Instructions and Programming
The INC, U/D and CS inputs control the movement of the wiper
along the resistor array. With CS set LOW, the device is selected
and enabled to respond to the U/D and INC inputs. HIGH-to-LOW
transitions on INC will increment or decrement (depending on the
state of the U/D input) a 7-bit counter. The output of this counter
is decoded to select one of one hundred wiper positions along
the resistive array.
R and R
H
L
The high (R ) and low (R ) terminals of the X9317 are equivalent
H
L
to the fixed terminals of a mechanical potentiometer. The
terminology of R and R references the relative position of the
L
H
terminal in relation to wiper movement direction selected by the
U/D input and not the voltage potential on the terminal.
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also HIGH.
R
W
R
is the wiper terminal and is equivalent to the movable
W
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs. The
wiper terminal series resistance is typically 200Ω.
The system may select the X9317, move the wiper and deselect
the device without having to store the latest wiper position in
nonvolatile memory. After the wiper movement is performed as
previously described and once the new position is reached, the
system must keep INC LOW while taking CS HIGH. The new wiper
position will be maintained until changed by the system or until a
power-up/down cycle recalls the previously stored data.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement and
whether the counter is incremented or decremented.
This procedure allows the system to always power-up to a preset
value stored in nonvolatile memory; then during system
operation minor adjustments could be made. The adjustments
might be based on user preference, system parameter changes
due to temperature drift, etc.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will move
the wiper and either increment or decrement the counter in the
direction indicated by the logic level on the U/D input.
The state of U/D may be changed while CS remains LOW. This
allows the host system to enable the device and then move the
wiper up and down until the proper trim is attained.
Chip Select (CS)
The device is selected when the CS input is LOW. The current
counter value is stored in nonvolatile memory when CS is
returned HIGH while the INC input is also HIGH. After the store
operation is complete, the X9317 will be placed in the low power
standby mode until the device is selected once again.
Mode Selection
CS
INC
U/D
MODE
L
H
Wiper up
Principles of Operation
L
L
Wiper down
There are three sections of the X9317: the control section, the
nonvolatile memory, and the resistor array. The control section
operates just like an up/down counter. The output of this counter
is decoded to turn on a single electronic switch connecting a
point on the resistor array to the wiper output. The contents of the
counter can be stored in nonvolatile memory and retained for
future use. The resistor array is comprised of 99 individual
resistors connected in series. Electronic switches at either end of
the array and between each resistor provide an electrical
H
X
Store wiper position to nonvolatile
memory
H
X
L
L
L
X
X
H
L
Standby
No store, return to standby
Wiper up (not recommended)
Wiper down (not recommended)
connection to the wiper pin, R .
W
Applications Information
Electronic digitally controlled (XDCP) potentiometers provide
three powerful application advantages:
The wiper acts like its mechanical equivalent and does not move
beyond the first or last position. That is, the counter does not
wrap around when clocked to either extreme.
The electronic switches on the device operate in a “make before
break” mode when the wiper changes tap positions. If the wiper
is moved several positions, multiple taps are connected to the
1. The variability and reliability of a solid-state potentiometer,
2. The flexibility of computer-based digital controls, and
3. The retentivity of nonvolatile memory used for the storage of
multiple potentiometer settings or data.
wiper for t (INC to V change). The R
value for the device
IW
W
TOTAL
can temporarily be reduced by a significant amount if the wiper
is moved several positions.
When the device is powered-down, the last wiper position stored
will be maintained in the nonvolatile memory. When power is
restored, the contents of the memory are recalled and the wiper
is set to the value last stored.
FN8183 Rev.10.00
Dec 17, 2018
Page 8 of 14
X9317
Basic Configurations of Electronic Potentiometers
V
REF
V
REF
R
H
R
W
R
L
I
FIGURE 3. THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE
DIVIDER
FIGURE 4. TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT
Basic Circuits
+V
+V
+5V
R
R
2
1
R
1
V
S
+V
X
+5V
R
W
R
LMC7101
V
W
-
+
-
V
100k
REF
V
+V
O
OUT
+
+5V
LMC7101
R
W
100k
(a)
(b)
V
= V /R
V = (R2/R1)V
O S
OUT
W
W
FIGURE 5. BUFFERED REFERENCE VOLTAGE
FIGURE 6. CASCADING TECHNIQUES
FIGURE 7. SINGLE SUPPLY INVERTING
AMPLIFIER
R
R
2
1
V
S
LT311A
V
IN
V (REG)
O
317
V
-
S
+5V
100kΩ
V
O
-
+
R
1
V
O
+
I
adj
LMC7101
10kΩ
10kΩ
R
2
R
R
2
1
10kΩ
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
= {R /(R +R )} V (min)
V
(REG) = 1.25V (1+R /R )+I R
adj 2
+5V
1 1 2 O
O
2
1
FIGURE 8. VOLTAGE REGULATOR
FIGURE 9. OFFSET VOLTAGE ADJUSTMENT
FIGURE 10. COMPARATOR WITH
HYSTERESIS
FN8183 Rev.10.00
Dec 17, 2018
Page 9 of 14
X9317
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
Dec 17, 2018
FN8183.10
Updated ordering information table by removing EOL parts.
Removed About Intersil section.
Updated disclaimer.
Nov 4, 2014
FN8183.9
Added Revision History
Converted to New Template and added new Intersil Standards.
Updated Ordering Information to show all U parts in column for Rtotal (kΩ) to show 50 as the value.
Added thermal information (Tja and Tjc).
FN8183 Rev.10.00
Dec 17, 2018
Page 10 of 14
X9317
For the most recent package outline drawing, see M8.118.
Package Outline Drawings
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
8
DETAIL "X"
D
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
TOP VIEW
PLANE
0.25
3°±3°
0.55 ± 0.15
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.10 C
0.25 - 0.36
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN8183 Rev.10.00
Dec 17, 2018
Page 11 of 14
X9317
For the most recent package outline drawing, see M8.173.
M8.173
8 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 01/10
A
2
4
3.0 ±0.5
SEE DETAIL "X"
8
5
6.40
C
4.40 ±0.10
L
3
4
PIN 1
ID MARK
1
4
0.20 CBA
B
0.09-0.20
0.65
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
6
SEATING
PLANE
GAUGE
PLANE
0.25
0.25 +0.05/-0.06
0.10 C B A
0.10 C
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
DETAIL "X"
SIDE VIEW
(1.45)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimension does not include mold flash, protrusions or
gate burrs. Mold flash, protrusions or gate burrs shall
not exceed 0.15 per side.
(5.65)
PACKAGE BODY
OUTLINE
3. Dimension does not include interlead flash or protrusion.
Interlead flash or protrusion shall not exceed 0.15 per side.
4. Dimensions are measured at datum plane H.
5. Dimensioning and tolerancing per ASME Y14.5M-1994.
6. Dimension on lead width does not include dambar protrusion.
Allowable protrusion shall be 0.08 mm total in excess of
dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm.
(0.35 TYP)
(0.65 TYP)
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153, variation AC. Issue E
FN8183 Rev.10.00
Dec 17, 2018
Page 12 of 14
X9317
For the most recent package outline drawing, see M8.15E.
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN8183 Rev.10.00
Dec 17, 2018
Page 13 of 14
Notice
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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
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(Rev.4.0-1 November 2017)
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