X9317TM8I-2.7_技术文档

X9317

®

Low Noise, Low Power, 100 Taps

Data Sheet

September 9, 2005

FN8183.1

Digitally Controlled Potentiometer

(XDCP™)

The Intersil X9317 is a digitally controlled potentiometer

(XDCP). The device consists of a resistor array, wiper

switches, a control section, and nonvolatile memory. The

wiper position is controlled by a 3-wire interface.

Features

• Solid-State Potentiometer

• 3-Wire Serial Up/Down Interface

• 100 Wiper Tap Points

- Wiper position stored in nonvolatile memory and

recalled on power-up

The potentiometer is implemented by a resistor array

composed of 99 resistive elements and a wiper switching

network. Between each element and at either end are tap

points accessible to the wiper terminal. The position of the

wiper element is controlled by the CS, U/D, and INC inputs.

The position of the wiper can be stored in nonvolatile

memory and then be recalled upon a subsequent power-up

operation.

• 99 Resistive Elements

- Temperature compensated

- End to end resistance range ±20%

• Low Power CMOS

- V

= 2.7V to 5.5V, and 5V ±10%

CC

- Standby current < 1µA

• High Reliability

- Endurance, 100,000 data changes per bit

- Register data retention, 100 years

The device can be used as a three-terminal potentiometer

for voltage control or as a two-terminal variable resistor for

current control in a wide variety of applications.

• R

TOTAL

Values = 1kΩ, 10kΩ, 50kΩ, 100kΩ

• Packages

- 8 Ld SOIC, DIP, TSSOP, and MSOP

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• LCD Bias Control

• DC Bias Adjustment

• Gain and Offset Trim

• Laser Diode Bias Control

• Voltage Regulator Output Control

Pinouts

X9317

(8 LD DIP, 8 LD SOIC, 8 LD MSOP)

TOP VIEW

(8 LD TSSOP)

TOP VIEW

R /V

CS

V

INC

U/D

R

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

L

CC

V

R

V

/V

CS

CC

INC

U/D

W

X9317

R

L

SS

H

V

R /V

R

SS

H

W

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

1

X9317

Ordering Information

TEMPERATURE

RANGE (°C)

PART NUMBER

X9317ZM8*

PART MARKING

V

LIMITS (V)

R

(kΩ)

PACKAGE

8 Ld MSOP

CC

TOTAL

5 ±10%

1

0 to 70

X9317ZM8Z* (Note)

X9317ZM8I*

DDA

AFI

8 Ld MSOP (Pb-free)

8 Ld MSOP

-40 to 85

0 to 70

X9317ZM8IZ* (Note)

X9317ZP

DCY

8 Ld MSOP (Pb-free)

8 Ld PDIP

X9317ZP

X9317Z

X9317Z Z

X9317Z I

X9317Z Z I

9317Z

X9317ZS8*

0 to 70

8 Ld SOIC

X9317ZS8Z* (Note)

X9317ZS8I*

0 to 70

8 Ld SOIC (Pb-free)

8 Ld SOIC

-40 to 85

0 to 70

X9317ZS8IZ* (Note)

X9317ZV8*

8 Ld SOIC (Pb-free)

8 Ld TSSOP

X9317ZV8Z* (Note)

X9317ZV8I*

9317Z Z

317ZI

0 to 70

8 Ld TSSOP (Pb-free)

8 Ld TSSOP

-40 to 85

0 to 70

X9317ZV8IZ* (Note)

X9317WM8*

9317ZI Z

ABF

8 Ld TSSOP (Pb-free)

8 Ld MSOP

10

X9317WM8Z* (Note)

X9317WM8I*

DCW

0 to 70

8 Ld MSOP (Pb-free)

8 Ld MSOP

ADS

-40 to 85

0 to 70

X9317WM8IZ* (Note)

X9317WP

DCT

8 Ld MSOP (Pb-free)

8 Ld PDIP

X9317WP

X9317WP I

X9317W

X9317W Z

X9317W I

X9317W Z I

9317W

9317W Z

317WI

X9317WPI

-40 to 85

0 to 70

8 Ld PDIP

X9317WS8*

8 Ld SOIC

X9317WS8Z* (Note)

X9317WS8I*

0 to 70

8 Ld SOIC (Pb-free)

8 Ld SOIC

-40 to 85

0 to 70

X9317WS8IZ* (Note)

X9317WV8*

8 Ld SOIC (Pb-free)

8 Ld TSSOP

X9317WV8Z* (Note)

X9317WV8I*

0 to 70

8 Ld TSSOP (Pb-free)

8 Ld TSSOP

-40 to 85

0 to 70

X9317WV8IZ* (Note)

X9317UM8*

9317WI Z

AEC

8 Ld TSSOP (Pb-free)

8 Ld MSOP

50

X9317UM8Z* (Note)

X9317UM8I*

DCS

0 to 70

8 Ld MSOP (Pb-free)

8 Ld MSOP

AFE

-40 to 85

0 to 70

X9317UM8IZ* (Note)

X9317UP

DCR

8 Ld MSOP (Pb-free)

8 Ld PDIP

X9317UP

X9317UP I

X9317UPI

-40 to 85

0 to 70

8 Ld PDIP

X9317US

8 Ld SOIC

X9317US8*

X9317U

X9317U Z

X9317U I

X9317U Z I

9317U

0 to 70

8 Ld SOIC

X9317US8Z* (Note)

X9317US8I*

0 to 70

8 Ld SOIC (Pb-free)

8 Ld SOIC

-40 to 85

0 to 70

X9317US8IZ* (Note)

X9317UV8*

8 Ld SOIC (Pb-free)

8 Ld TSSOP

X9317UV8Z* (Note)

X9317UV8I*

9317U Z

317UI

0 to 70

8 Ld TSSOP (Pb-free)

8 Ld TSSOP

-40 to 85

X9317UV8IZ* (Note)

9317UI Z

8 Ld TSSOP (Pb-free)

FN8183.1

2

September 9, 2005

X9317

Ordering Information (Continued)

TEMPERATURE

RANGE (°C)

PART NUMBER

X9317TM8*

PART MARKING

V

LIMITS (V)

R

(kΩ)

PACKAGE

8 Ld MSOP

CC

TOTAL

AGD

DCN

AGF

DCL

100

0 to 70

X9317TM8Z* (Note)

X9317TM8I*

8 Ld MSOP (Pb-free)

8 Ld MSOP

-40 to 85

0 to 70

X9317TM8IZ* (Note)

X9317TP

8 Ld MSOP (Pb-free)

8 Ld PDIP

X9317TPI

X9317TP I

X9317T

-40 to 85

0 to 70

8 Ld PDIP

X9317TS8

8 Ld SOIC

X9317TS8Z (Note)

X9317TS8I

X9317T Z

X9317T I

X9317T Z I

0 to 70

8 Ld SOIC (Pb-free)

8 Ld SOIC

-40 to 85

0 to 70

X9317TS8IZ (Note)

X9317TV8*

8 Ld SOIC (Pb-free)

8 Ld TSSOP

X9317TV8Z* (Note)

X9317TV8I*

9317T Z

0 to 70

8 Ld TSSOP (Pb-free)

8 Ld TSSOP

-40 to 85

0 to 70

X9317TV8IZ* (Note)

X9317ZM8-2.7*

9317TI Z

AFH

8 Ld TSSOP (Pb-free)

8 Ld MSOP

2.7-5.5

1

X9317ZM8Z-2.7* (Note)

X9317ZM8I-2.7*

AOA

0 to 70

8 Ld MSOP (Pb-free)

8 Ld MSOP

AFJ

-40 to 85

0 to 70

X9317ZM8IZ-2.7* (Note)

X9317ZS8-2.7*

DCZ

8 Ld MSOP (Pb-free)

8 Ld SOIC

X9317Z F

X9317Z Z F

X9317Z G

X9317Z Z G

317ZF

X9317ZS8Z-2.7* (Note)

X9317ZS8I-2.7*

0 to 70

8 Ld SOIC (Pb-free)

8 Ld SOIC

-40 to 85

0 to 70

X9317ZS8IZ-2.7* (Note)

X9317ZV8-2.7*

8 Ld SOIC (Pb-free)

8 Ld TSSOP

X9317ZV8Z-2.7* (Note)

X9317ZV8I-2.7*

9317ZF Z

317ZG

0 to 70

8 Ld TSSOP (Pb-free)

8 Ld TSSOP

-40 to 85

0 to 70

X9317ZV8IZ-2.7* (Note)

X9317WM8-2.7*

X9317WM8Z-2.7* (Note)

X9317WM8I-2.7*

X9317WP-2.7

317ZG Z

ACZ

8 Ld TSSOP (Pb-free)

8 Ld MSOP

10

DCX

0 to 70

8 Ld MSOP (Pb-free)

8 Ld MSOP

ADT

-40 to 85

0 to 70

X9317WP F

X9317WP G

X9317W F

X9317W Z F

X9317W G

X9317W Z G

317WF

8 Ld PDIP

X9317WPI-2.7

-40 to 85

0 to 70

8 Ld PDIP

X9317WS8-2.7*

8 Ld SOIC

X9317WS8Z-2.7* (Note)

X9317WS8I-2.7*

X9317WS8IZ-2.7* (Note)

X9317WV8-2.7*

0 to 70

8 Ld SOIC (Pb-free)

8 Ld SOIC

-40 to 85

0 to 70

8 Ld SOIC (Pb-free)

8 Ld TSSOP

X9317WV8Z-2.7* (Note)

X9317WV8I-2.7*

X9317WV8IZ-2.7* (Note)

9317WF Z

317WG

0 to 70

8 Ld TSSOP (Pb-free)

8 Ld TSSOP

-40 to 85

AKZ

8 Ld TSSOP (Pb-free)

FN8183.1

3

September 9, 2005

X9317

Ordering Information (Continued)

TEMPERATURE

RANGE (°C)

PART NUMBER

X9317UM8-2.7*

PART MARKING

V

LIMITS (V)

R

(kΩ)

PACKAGE

8 Ld MSOP

CC

TOTAL

AED

AOB

50

0 to 70

X9317UM8Z-2.7* (Note)

X9317UM8I-2.7*

8 Ld MSOP (Pb-free)

8 Ld MSOP

AFF

-40 to 85

0 to 70

X9317UM8IZ-2.7* (Note)

X9317UP-2.7

AOH

8 Ld MSOP (Pb-free)

8 Ld PDIP

X9317UP F

X9317UP G

X9317U F

X9317U Z F

X9317U G

X9317U Z G

9317UF

9317UF Z

9317UG

9317UG Z

AGE

X9317UPI-2.7

-40 to 85

0 to 70

8 Ld PDIP

X9317US8-2.7*

8 Ld SOIC

X9317US8Z-2.7* (Note)

X9317US8I-2.7*

0 to 70

8 Ld SOIC (Pb-free)

8 Ld SOIC

-40 to 85

0 to 70

X9317US8IZ-2.7* (Note)

X9317UV8-2.7*

8 Ld SOIC (Pb-free)

8 Ld TSSOP

X9317UV8Z-2.7* (Note)

X9317UV8I-2.7*

0 to 70

8 Ld TSSOP (Pb-free)

8 Ld TSSOP

-40 to 85

0 to 70

X9317UV8IZ-2.7* (Note)

X9317TM8-2.7*

8 Ld TSSOP (Pb-free)

8 Ld MSOP

100

X9317TM8Z-2.7* (Note)

X9317TM8I-2.7*

DCP

0 to 70

8 Ld MSOP (Pb-free)

8 Ld MSOP

AGG

-40 to 85

0 to 70

X9317TM8IZ-2.7* (Note)

X9317TP-2.7

DCM

8 Ld MSOP (Pb-free)

8 Ld PDIP

X9317TPI-2.7

X9317TP G

-40 to 85

0 to 70

8 Ld PDIP

X9317TS8-2.7*

8 Ld SOIC

X9317TS8Z-2.7* (Note)

X9317TS8I-2.7*

X9317T Z F

X9317T G

0 to 70

8 Ld SOIC (Pb-free)

8 Ld SOIC

-40 to 85

0 to 70

X9317TS8IZ-2.7* (Note)

X9317TV8-2.7*

X9317T Z G

8 Ld SOIC (Pb-free)

8 Ld TSSOP

X9317TV8Z-2.7* (Note)

X9317TV8I-2.7*

9317TF Z

317TG

0 to 70

8 Ld TSSOP (Pb-free)

8 Ld TSSOP

-40 to 85

X9317TV8IZ-2.7* (Note)

9317TG Z

8 Ld TSSOP (Pb-free)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Add "T1" suffix for tape and reel.

FN8183.1

4

September 9, 2005

X9317

Block Diagram

U/D

INC

CS

R

99

H

Up/Down

Counter

V

(Supply Voltage)

CC

98

97

96

R

Up/Down

(U/D)

H

7-Bit

Nonvolatile

Memory

One

of

One

Control

and

Memory

Increment

(INC)

W

Wiper

Switches

Resistor

Array

Hundred

Decoder

Device Select

(CS)

R

L

2

Store and

Recall

Control

Circuitry

V

SS

(Ground)

1

0

V

CC

SS

General

R

L

W

Detailed

Pin Descriptions

DIP/SOIC

SYMBOL

INC

BRIEF DESCRIPTION

1

2

3

4

5

6

7

8

Increment. Toggling INC while CS is low moves the wiper either up or down.

Up/Down. The U/D input controls the direction of the wiper movement.

U/D

R

The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.

Ground.

H

V

SS

R

The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer.

The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.

W

R

L

CS

Chip Select. The device is selected when the CS input is LOW, and de-selected when CS is high.

V

Supply Voltage.

CC

FN8183.1

September 9, 2005

5

X9317

Absolute Maximum Ratings

Junction Temperature Under Bias . . . . . . . . . . . . . .-65°C to +135°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Lead Temperature (soldering 10s). . . . . . . . . . . . . . . . . . . . . . 300°C

I (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA

W

Voltage on CS, INC, U/D and V

CC

with Respect to V . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

SS

R , R , R to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V

H

W

L

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation

of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Potentiometer Specifications V = Full Range, T = Full Operating Temperature Range unless otherwise stated

CC

A

TYP

SYMBOL

PARAMETER

TEST CONDITIONS/NOTES

MIN

(Note 4)

MAX

UNIT

%

R

End to end resistance tolerance

See ordering information for values

-20

+20

TOTAL

V

/

R /R terminal voltage

V

= 0V

V

CC

V

RH RL

H

L

SS

Power rating

R

≥ 10kΩ

10

25

mW

Ω

TOTAL

= 1kΩ

R

Wiper resistance

I

= 1mA, V

= 5V

200

400

1000

+4.4

W

CC

I

= 2.7V

Ω

I

Wiper current (Note 5)

Noise (Note 7)

See test circuit

Ref: 1kHz

-4.4

mA

dBV

%

W

-120

1

Resolution

Absolute linearity (Note 1)

V(RH) = V

,

-1

+1

MI

(Note 3)

CC

V(RL) = 0V

Relative linearity (Note 2)

-0.2

+0.2

MI

(Note 3)

R

temperature coefficient (Note 5)

±300

ppm/°C

TOTAL

Ratiometric temperature coefficient

(Notes 5, 6)

-20

+20

C /C /C

W

Potentiometer capacitances

See equivalent circuit

10/10/25

pF

H

L

(Note 5)

V

Supply Voltage

X9317

4.5

2.7

5.5

V

CC

X9317-2.7

DC Electrical Specifications

V

= 5V ±10%, T = Full Operating Temperature Range unless otherwise stated

A

CC

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 4)

MAX

UNIT

I

V

active current (Increment)

CS = V , U/D = V or V and INC =

50

µA

CC1

CC

IL

IH

V /V @ min. t

IL IH

CYC

R , R , R not connected

L

H

W

I

active current (Store)

(non-volatile write)

CS = V , U/D = V or V and INC = V

IH IL IH

400

1

µA

CC2

CC

IL

or V . R , R , R not connected

IH L H W

I

Standby supply current

CS ≥ V , U/D and INC = V

IH

SB

IL

R , R , R not connected

L

H

W

I

CS, INC, U/D input leakage current

CS, INC, U/D input HIGH voltage

V

= V to V

SS CC

-10

+10

µA

V

LI

IN

V

x

V

+

IH

CC

0.7

CC

0.5

V

CS, INC, U/D input LOW voltage

-0.5

V

x

V

IL

CC

0.1

FN8183.1

6

September 9, 2005

X9317

DC Electrical Specifications

V

= 5V ±10%, T = Full Operating Temperature Range unless otherwise stated (Continued)

CC

A

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 4)

MAX

UNIT

C

(Note 5) CS, INC, U/D input capacitance

V

= 5V, V = V , T = 25°C,

10

pF

IN

CC

f = 1MHz

IN SS

A

Endurance and Data Retention V = 5V ±10%, T = Full Operating Temperature Range

CC

A

PARAMETER

Minimum endurance

Data retention

MIN

100,000

100

UNIT

Data changes per bit

Years

NOTES:

1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(R

)-V(R

)]/MI

W(n)(actual)

) - MI)]/MI.

W(n)(expected)

V(R

) = n(V(R )-V(R ))/99 + V(R ), with n from 0 to 99.

W(n)(expected)

H L L

2. Relative linearity is a measure of the error in step size between taps = [V(R

)-(V(R

W(n+1)

W(n)

3. 1 Ml = Minimum Increment = [V(R )-V(R )]/99.

H

L

4. Typical values are for T = 25°C and nominal supply voltage.

A

5. This parameter is not 100% tested.

6. Ratiometric temperature coefficient = (V(R

6

)

-V(R

)

)/[V(R

)

(T1-T2) x 10 ], with T1 & T2 being 2 temperatures, and n from 0 to 99.

W T1(n)

W T2(n)

W T1(n)

7. Measured with wiper at tap position 99, R grounded, using test circuit.

L

Test Circuit

Equivalent Circuit

R

TOTAL

Test Point

R

L

H

C

L

C

W

C

H

10pF

R

W

Force

25pF

Current

10pF

R

W

AC Conditions of Test

Input pulse levels

0V to 3V

10ns

Input rise and fall times

Input reference levels

1.5V

AC Electrical Specifications

V

= 5V ±10%, T = Full Operating Temperature Range unless otherwise stated

CC A

SYMBOL

PARAMETER

MIN

50

TYP (Note 4)

MAX

UNIT

ns

t

CS to INC setup

Cl

t

(Note 5) INC HIGH to U/D change

(Note 5) U/D to INC setup

100

1

ns

lD

t

µs

DI

t

INC LOW period

960

1

ns

lL

t

INC HIGH period

ns

lH

lC

INC inactive to CS inactive

CS deselect time (STORE)

CS deselect time (NO STORE)

µs

t

10

ms

ns

CPHS

t

100

CPHNS

(Note 5)

t

INC to R change

1

5

µs

IW

W

FN8183.1

September 9, 2005

7

X9317

AC Electrical Specifications

V

= 5V ±10%, T = Full Operating Temperature Range unless otherwise stated (Continued)

CC

A

SYMBOL

PARAMETER

MIN

TYP (Note 4)

MAX

UNIT

µs

t

INC cycle time

INC input rise and fall time

2

CYC

t

500

µs

R, F

(Note 5)

t

(Note 5) Power up to wiper stable

5

µs

PU

t

V

power-up rate

0.2

50

V/ms

R

CC

(Note 5)

t

Store Cycle

5

10

ms

WR

spec is always in effect. In order to prevent unwanted tap

position changes, or an inadvertent store, bring the CS and

Power Up and Down Requirements

The recommended power up sequence is to apply V /V

CC SS

INC high before or concurrently with the V

powerup.

pin on

CC

first, then the potentiometer voltages. During power-up, the

data sheet parameters for the DCP do not fully apply until 1

millisecond after V

reaches its final value. The V

ramp

CC

AC Timing

CS

t

CYC

t

CPHNS

t

CPHS

CI

IL

IH

IC

90%

10%

90%

INC

U/D

t

R

ID

DI

F

t

IW

(3)

MI

R

W

Typical Performance Characteristics

0

-50

-100

-150

-200

-250

-300

-350

-55-45-35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95105115125

TEMPERATURE (°C)

FIGURE 1. TYPICAL TOTAL RESISTANCE TEMPERATURE

COEFFICIENT

FN8183.1

September 9, 2005

8

X9317

Pin Descriptions

Pin Names

R

and R

SYMBOL

DESCRIPTION

H

L

The high (R ) and low (R ) terminals of the X9317 are

H

L

R

High terminal

Wiper terminal

Low terminal

Ground

H

equivalent to the fixed terminals of a mechanical

potentiometer. The terminology of R and R references the

R

W

L

H

R

relative position of the terminal in relation to wiper movement

direction selected by the U/D input and not the voltage

potential on the terminal.

L

V

SS

CC

V

Supply voltage

R_W

U/D

INC

CS

Up/Down control input

Increment control input

Chip select control input

R

is the wiper terminal and is equivalent to the movable

w

terminal of a mechanical potentiometer. The position of the

wiper within the array is determined by the control inputs.

The wiper terminal series resistance is typically 200Ω.

Principles of Operation

Up/Down (U/D)

There are three sections of the X9317: the control section,

the nonvolatile memory, and the resistor array. The control

section operates just like an up/down counter. The output of

this counter is decoded to turn on a single electronic switch

connecting a point on the resistor array to the wiper output.

The contents of the counter can be stored in nonvolatile

memory and retained for future use. The resistor array is

comprised of 99 individual resistors connected in series.

Electronic switches at either end of the array and between

each resistor provide an electrical connection to the wiper

The U/D input controls the direction of the wiper movement

and whether the counter is incremented or decremented.

Increment (INC)

The INC input is negative-edge triggered. Toggling INC will

move the wiper and either increment or decrement the

counter in the direction indicated by the logic level on the

U/D input.

Chip Select (CS)

pin, R .

W

The device is selected when the CS input is LOW. The

current counter value is stored in nonvolatile memory when

CS is returned HIGH while the INC input is also HIGH. After

the store operation is complete the X9317 will be placed in

the low power standby mode until the device is selected

once again.

The wiper acts like its mechanical equivalent and does not

move beyond the first or last position. That is, the counter

does not wrap around when clocked to either extreme.

The electronic switches on the device operate in a “make

before break” mode when the wiper changes tap positions. If

the wiper is moved several positions, multiple taps are

Pin Configuration

connected to the wiper for t (INC to V change). The

IW

W

DIP/SOIC/MSOP

R

value for the device can temporarily be reduced by

TOTAL

a significant amount if the wiper is moved several positions.

V

INC

U/D

1

2

3

4

8

7

6

5

CC

CS

When the device is powered-down, the last wiper position

stored will be maintained in the nonvolatile memory. When

power is restored, the contents of the memory are recalled

and the wiper is set to the value last stored.

X9317

R

L

R

H

V

R

SS

W

TSSOP

Instructions and Programming

The INC, U/D and CS inputs control the movement of the

wiper along the resistor array. With CS set LOW the device

is selected and enabled to respond to the U/D and INC

inputs. HIGH to LOW transitions on INC will increment or

decrement (depending on the state of the U/D input) a seven

bit counter. The output of this counter is decoded to select

one of one hundred wiper positions along the resistive array.

R /V

CS

1

2

3

4

8

7

6

5

L

V

R

V

/V

CC

W

X9317

INC

U/D

SS

R /V

H

The value of the counter is stored in nonvolatile memory

whenever CS transitions HIGH while the INC input is also

HIGH.

FN8183.1

9

September 9, 2005

X9317

The system may select the X9317, move the wiper and

deselect the device without having to store the latest wiper

position in nonvolatile memory. After the wiper movement is

performed as described above and once the new position is

reached, the system must keep INC LOW while taking CS

HIGH. The new wiper position will be maintained until

changed by the system or until a powerup/down cycle

recalled the previously stored data.

This procedure allows the system to always power-up to a

preset value stored in nonvolatile memory; then during

system operation minor adjustments could be made. The

adjustments might be based on user preference, system

parameter changes due to temperature drift, etc.

The state of U/D may be changed while CS remains LOW.

This allows the host system to enable the device and then

move the wiper up and down until the proper trim is attained.

Mode Selection

CS

INC

U/D

MODE

L

H

Wiper up

L

Wiper down

H

X

Store wiper position to nonvolatile

memory

H

X

L

X

H

L

Standby

No store, return to standby

Wiper Up (not recommended)

Wiper Down (not recommended)

FN8183.1

10

September 9, 2005

X9317

computer-based digital controls, and (3) the retentivity of

nonvolatile memory used for the storage of multiple

potentiometer settings or data.

Applications Information

Electronic digitally controlled (XDCP) potentiometers provide

three powerful application advantages; (1) the variability and

reliability of a solid-state potentiometer, (2) the flexibility of

Basic Configurations of Electronic Potentiometers

V

REF

R

H

R

W

R

L

I

Three terminal potentiometer;

variable voltage divider

Two terminal variable resistor;

variable current

Basic Circuits

Single Supply Inverting Amplifier

+5V

Buffered Reference Voltage

Cascading Techniques

R

1

+V

R

2

1

+5V

V

S

R

W

LMC7101

V

+

-

V

REF

X

OUT

R

W

-

100K

V

O

+V

+

+5V

LMC7101

100K

R

V

= V /R

W W

W

OUT

(a)

(b)

V = (R2/R1)V

O S

Voltage Regulator

317

Offset Voltage Adjustment

Comparator with Hysteresis

LT311A

R

2

1

V

(REG)

O

IN

V

-

S

V

O

+5V

R

1

100kΩ

+

-

V

O

+

I

adj

R

2

LMC7101

10kΩ

R

2

1

10kΩ

V

= {R /(R +R )} V (max)

1 1 2 O

UL

LL

V

(REG) = 1.25V (1+R /R )+I

R

adj 2

V

= {R /(R +R )} V (min)

1 1 2 O

O

2

1

+5V

(for additional circuits see AN115)

FN8183.1

September 9, 2005

11

X9317

Packaging Information

8-Lead Plastic Dual In-Line (DIP) Package Type P

0.430 (10.92)

0.360 (9.14)

0.260 (6.60)

0.240 (6.10)

Pin 1 Index

Pin 1

0.060 (1.52)

0.020 (0.51)

0.300

(7.62) Ref.

Half Shoulder Width On

All End Pins Optional

0.145 (3.68)

0.128 (3.25)

Seating

Plane

0.025 (0.64)

0.015 (0.38)

0.065 (1.65)

0.150 (3.81)

0.125 (3.18)

0.045 (1.14)

0.110 (2.79)

0.090 (2.29)

0.020 (0.51)

0.016 (0.41)

0.325 (8.25)

0.300 (7.62)

.073 (1.84)

Max.

0°

15°

Typ. 0.010 (0.25)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

FN8183.1

12

September 9, 2005

X9317

Packaging Information

8-Lead Plastic Small Outline Gull Wing Package Type S (SOIC)

0.150 (3.80) 0.228 (5.80)

0.158 (4.00) 0.244 (6.20)

Pin 1 Index

Pin 1

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

(4X) 7°

0.053 (1.35)

0.069 (1.75)

0.004 (0.19)

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

0.050"Typical

X 45°

0.050"

Typical

0° - 8°

0.0075 (0.19)

0.010 (0.25)

0.250"

0.016 (0.410)

0.037 (0.937)

0.030"

Typical

8 Places

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

FN8183.1

13

September 9, 2005

X9317

Packaging Information

8-Lead Plastic, TSSOP, Package Type V

.025 (.65) BSC

.169 (4.3)

.252 (6.4) BSC

.177 (4.5)

.114 (2.9)

.122 (3.1)

.047 (1.20)

.0075 (.19)

.0118 (.30)

.002 (.05)

.006 (.15)

.010 (.25)

Gage Plane

0° - 8°

Seating Plane

.019 (.50)

.029 (.75)

(7.72)

(4.16)

Detail A (20X)

(1.78)

(0.42)

.031 (.80)

.041 (1.05)

(0.65)

All Measurements Are Typical

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

FN8183.1

14

September 9, 2005

X9317

Packaging Information

M Package

8-Lead Miniature Small Outline Gull Wing Package Type MSOP

0.118 ± 0.002

(3.00 ± 0.05)

0.012 + 0.006 / -0.002

0.0256 (0.65) Typ.

(0.30 + 0.15 / -0.05)

R 0.014 (0.36)

0.118 ± 0.002

(3.00 ± 0.05)

0.030 (0.76)

0.0216 (0.55)

7° Typ.

0.036 (0.91)

0.032 (0.81)

0.040 ± 0.002

(1.02 ± 0.05)

0.008 (0.20)

0.004 (0.10)

0.0256" Typical

0.025"

Typical

0.150 (3.81)

0.007 (0.18)

0.005 (0.13)

Ref.

0.193 (4.90)

Ref.

0.220"

0.020"

Typical

8 Places

FOOTPRINT

NOTE:

1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8183.1

15

September 9, 2005


型号：	X9317TM8I-2.7
厂家：	Intersil
描述：	Low Noise, Low Power, 100 Taps 低噪声，低功耗， 100丝锥
文件：	总15页 (文件大小：333K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X9317TM8I-2.7 [INTERSIL]

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