X90100M8IT1 [RENESAS]
SPECIALTY ANALOG CIRCUIT, PDSO8, MSOP-8;
| 型号： | X90100M8IT1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SPECIALTY ANALOG CIRCUIT, PDSO8, MSOP-8 光电二极管 |
| 文件： | 总7页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X90100
February 2, 2005
FN8156.0
NV Electronically Programmable
Capacitor
Features
• Non-volatile EEPROM storage of programmed trim codes
• Power On Recall of capacitance setting
• High-Performance Electronically Trimmable Capacitance
• Excellent linearity: <0.5 LSB error
The Intersil X90100 is a non-volatile electronically
programmable capacitor. The device is programmed through
a simple digital interface. After programming, the chosen
setting for the device is retained by internal EEPROM
storage whether or not DC power is maintained. There are
32 programmable capacitance values selectable, ranging
from 7.5pF to 14.5pF in 0.23pF increments, in single-ended
mode. The dielectric is highly stable, and the capacitance
exhibits a very low voltage coefficient. It has virtually no
dielectric absorbtion and has a very low temperature drift
coefficient in differential mode (<50ppm/°C).
• Very Simple Digital Interface
• Fast adjustments: 5µs max incremental change
• Eliminates the need for mechanical tuning
• Capacitance trimmable from 7.5pF to 14.5pF (single-
ended mode)
• Packages:
The X90100 is programmed through three digital interface
pins, which have Schmitt triggers and pullup resistors to
secure code retention. The three pins, INC, U/D, and CS,
are identical in operation to other Intersil chips with up/down
interface, such as the X9315 5-bit Digitally Controlled
Potentiometer (DCP).
- MSOP (1.1mm x 3.0mm x 3.0mm)
Applications
• Post-trim of low-cost regenerative receivers
• Tunable RF stages
Pinout
• Low-cost, Low temperature drift oscillators
• Garage door openers
X90100
(8 LD MSOP)
TOP VIEW
• Keyless entry
• Industrial wireless control
• Capacitive sensor trimming
• RFID tags
INC
1
2
3
4
8
7
6
5
V
CC
U/D
Vss
Cp
CS
N/C
Cm
Ordering Information
TEMP
ORDERING
NUMBER
RANGE
(°C)
C
PACKAGE
TOTAL
X90100M8I
7.5pF to 14.5pF,
Single Ended
8 Ld MSOP
-40 to +85
X90100M8IT1 7.5pF to 14.5pF,
Single Ended
8 Ld MSOP
Tape and Reel
-40 to +85
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X90100
Block Diagram
Cm
Cp
1*C
2*C
U
U
C
C
PAD
PAD
4*C
8*C
U
U
V
SS
16*C
U
U/D
INC
CS
2
Logic and E
V
CC
Power On Reset
Pin Descriptions
MSOP
SYMBOL
BRIEF DESCRIPTION
1
INC
U/D
Increment (INC). The INC input is negative-edge triggered. Toggling INC will move the capacitance value and
either increment or decrement the counter in the direction indicated by the logic level on the U/D input.
2
Up/Down (U/D). The U/D input controls the direction of the trimmed capacitor value and whether the counter
is incremented or decremented.
3
4
V
Ground.
SS
Cp
Cp. The high (Cp) and low (Cm) terminals of the X90100 are equivalent to the fixed terminals of a mechanical
trimmable capacitor. The minimum dc voltage is V
across the terminals is determined by digital inputs INC, U/D, and CS.
and the maximum is V . The value of capacitance
SS
CC
5
Cm
Cm. The high (Cp) and low (Cm) terminals of the X90100 are equivalent to the fixed terminals of a mechanical
trimmable capacitor. The minimum dc voltage is V
across the terminals is determined by digital inputs INC, U/D, and CS.
and the maximum is V . The value of capacitance
SS
CC
6
7
N/C
CS
Not Connected. Must be floating.
Chip Select (CS). The device is selected when the CS input is LOW. The current counter value is stored in
nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is
complete the X90100 will be placed in the low power standby mode until the device is selected once again.
8
V
Positive Supply Voltage.
CC
FN8156.0
February 2, 2005
2
X90100
Absolute Maximum Ratings
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65C to +135C
V = |V -V |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
CP CM
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead temperature (soldering 10 seconds). . . . . . . . . . . . . . . . 300°C
Voltage on CS, INC, U/D, C , and
P
C
M
with respect to V . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
SS
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Capacitor Specifications
V
= +5V, T = 25°C, single ended mode, C = 0V, unless otherwise stated.
CC
PARAMETER
Absolute accuracy
A
M
(4)
SYMBOL
TEST CONDITIONS/NOTES
MIN
TYP
MAX
UNIT
%
±15
V
C
C
terminal voltage
terminal voltage
0
0
V
V
V
Cp
p
CC
CC
V
V
Cm
m
C
C
Capacitance increments
Capacitance range
0.23
7
pF
pF
pF
pF
C
C
Capacitance at Code=0
Capacitance at Code=31
7.5
TOTAL
14.5
7
TOTAL
Q
(5)
Quality factor
f = 315MHz
Resolution
5
bits
lsb
(1)
INL
Absolute linearity error
±0.15
±0.15
±50
(2)
DNL
Relative linearity error
lsb
(5)
TC
C
Temperature Coefficient
Differential Mode
ppm/°C
V
1
TOTAL
V
Supply Voltage
2.7
5.5
CC
Notes: (1) Absolute linearity is used to determine actual capacitance versus expected capacitance = C (actual) - C (expected) = ±0.15 Ml.
(n)
(n)
(2) Relative linearity is a measure of the error in step size between settings = C
-[C + Ml] = ±0.15 Ml.
(n)
(n+1)
(3) lsb = least significant bit = C
/31.
TOT
(4) Typical values are for T = 25°C and nominal supply voltage.
A
(5) This parameter is not 100% tested.
DC Electrical Specifications
V
= 5V, T = 25°C unless otherwise specified.
CC A
(4)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
V
V
active current (Increment)
CS = V , U/D = V or V and
50
100
µA
CC1
CC
CC
IL IL IH
INC = 0.4V @ max. t
CYC
I
active current (Store) (EEPROM
CS = V , U/D = V or V and
IH IL IH
250
0.5
-15
500
2
µA
µA
CC2
Store)
INC = V @ max. t
IH
WR
- 0.3V, U/D and INC = V
SS
I
Standby supply current
CS = V
CC
SB
or V
- 0.3V
CC
I
CS, INC, U/D input leakage current
CS, INC, U/D input HIGH voltage
CS, INC, U/D input LOW voltage
CS, INC, U/D input capacitance
V
= V
µA
V
LI
IN
SS
V
V
x 0.7
V
+ 0.5
IH
CC
CC
V
-0.5
V
x 0.1
V
IL
(5)
CC
C
V
= 5V, V = V , T = 25°C,
IN SS
10
pF
IN
CC
A
f = 1MHz
FN8156.0
February 2, 2005
3
X90100
Endurance and Data Retention
PARAMETER
V
= 5V, T = 25°C unless otherwise specified
A
CC
MIN
100,000
100
UNIT
Data changes per bit
Years
Minimum endurance
Data retention
AC Conditions of Test
Input pulse levels
0V to 3V
Input rise and fall times
Input reference levels
10ns
1.5V
AC Electrical Specifications
V
= 5V, T = 25°C unless otherwise specified.
CC A
(4)
SYMBOL
PARAMETER
MIN
100
100
100
1
TYP
MAX
UNIT
ns
t
t
CS to INC setup
Cl
lD
INC HIGH to U/D change
U/D to INC setup
ns
t
ns
DI
(7)
t
INC LOW period
µs
lL
(7)
t
INC HIGH period
1
µs
lH
t
INC Inactive to CS inactive
CS Deselect time (NO STORE)
CS Deselect time (STORE)
1
µs
lC
(5)
CPHNS
t
1
µs
(5)
CPHS
t
10
ms
µs
t
INC to C
TOTAL
change
1
5
IW
t
INC cycle time
4
µs
CYC
(5)
t
t
INC input rise and fall time
500
5
µs
R, F
(5)
t
Power up to capacitance stable
µs
PU
(5)
CC
t
V
V
power-up rate
0.2
50
10
V/ms
ms
R
t
CC
(5)
WR
Store cycle
5
AC Timing
CS
t
CYC
(Store)
t
CPHS
t
CPHNS
t
t
t
t
CI
IL
IH
IC
90%
90%
10%
INC
U/D
t
t
t
t
R
ID
DI
F
t
IW
(6)
MI
C
TOTAL
Notes: (6) MI in the A.C. timing diagram refers to the minimum incremental change in the C
output due to a change in the counter value.
TOTAL
(7) t + t 4µs
IH IL
FN8156.0
February 2, 2005
4
X90100
Power Up Timing (Digital Inputs Floating, Internal Pullup Action Shown)
V
= 3.3 or 5.0V
CC
t V
CC
R
V
CC
CS
INC
U/D
Increment (INC)
Power Up and Down Requirements
The INC input is negative-edge triggered. Toggling INC will
move the capacitance value and either increment or
decrement the counter in the direction indicated by the logic
level on the U/D input. This pin has an active current source
pullup.
There are no restrictions on the power-up or power-down
conditions of V
and the voltages applied to the Cp, Cm
CC
pins provided that V
is always more positive than or equal
V , V . The V ramp rate spec
Cp Cm CC
CC
CC
to V , V , i.e., V
Cp Cm
is always in effect.
Chip Select (CS)
Powerup Requirements
The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory when
CS is returned HIGH while the INC input is also HIGH. After
the store operation is complete the X90100 will be placed in
the low power standby mode until the device is selected
once again. This pin has active circuit source pullup.
In order to prevent unwanted tap position changes or an
inadvertant store, bring the CS and INC high before or
concurrently with the V
pin. The logic inputs have internal
CC
active pullups to provide reliable powerup operation. See
powerup timing diagram.
Pin Configuration
N/C - This pin should be left floating.
MSOP
Pin Names
INC
1
2
3
4
8
7
6
5
V
CC
SYMBOL
DEFAULT
output
DESCRIPTION
Positive capacitor terminal
Negative capacitor terminal
Ground
U/D
Vss
Cp
CS
X90100
Cp
N/C (leave floating)
Cm
output
Cm
V
supply
supply
pull up
pull up
pull up
SS
V
Positive supply voltage
Up/Down control input
Increment control input
Chip Select control input
CC
Detailed Pin Descriptions
U/D
INC
CS
Cp and Cm
The high (Cp) and low (Cm) terminals of the X90100 are
equivalent to the fixed terminals of a mechanical trimmable
capacitor. The minimum dc voltage is V and the maximum
is V . The value of capacitance across the terminals is
CC
SS
Principles of Operation
There are three sections of the X90100: the input control,
counter and decode section; the nonvolatile memory; and
the capacitor array. The input control section operates just
like an up/down counter. The output of this counter is
decoded to turn on electronic switches connecting internal
units to the sum capacitor. Under the proper conditions the
contents of the counter can be stored in nonvolatile memory
determined by digital inputs INC, U/D, and CS.
Up/Down (U/D)
The U/D input controls the direction of the trimmed capacitor
value and whether the counter is incremented or
decremented. This pin has an active current source pullup.
FN8156.0
February 2, 2005
5
X90100
and retained for future use. The capacitor array is comprised
of 31 individual capacitors connected in parallel. At one end
of each element is an electronic switch that connects it to the
sum.
The system may select the X90100, move the capacitor
value and deselect the device without having to store the
latest count total in nonvolatile memory. After the count
movement is performed as described above and once the
new position is reached, the system must keep INC LOW
The capacitor, when at either end of the range, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
while taking CS HIGH. The new C
value will be
TOTAL
maintained until changed by the system or until a power-
up/down cycle recalled the previously stored data.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments can be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.
The electronic switches on the device operate in a “make
before break” mode when the counter changes positions. If
the counter is moved several positions, multiple units are
connected to the total for t (INC to C
change). The
value for the device can temporarily be increased by
IW TOTAL
C
TOTAL
a significant amount if the counter is moved several
positions.
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the counter up and down until the proper trim is
attained.
When the device is powered-down, the last counter position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the capacitor is set to the value last stored.
Mode Selection
CS
INC
U/D
H
L
MODE
Instructions and Programming
L
Cap Value Up
The INC, U/D and CS inputs control the movement of the
capacitor total value. With CS set LOW the device is
selected and enabled to respond to the U/D and INC inputs.
HIGH to LOW transitions on INC will increment or decrement
(depending on the state of the U/D input) a five bit counter.
The output of this counter is decoded to select one of thirty
two capacitor combinations for the capacitor array.
L
Cap Value Down
H
X
L
L
L
X
Store Cap Position
H
X
Standby Current
X
No Store, Return To Standby
Cap Value Up (not recommended)
Cap Value Down (not recommended)
H
L
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
Table of Values
Single-Ended Mode
Code
Differential Mode
C
= Code • 0.35 + 1.00 (pF)
OUT
C
=
• 7.0 + 7.5 (pF)
OUT
31
0 Code 31
0 Code 31
C
m
C
X1
p
C
C
p
s
Oscillator
Circuit
X90100
Oscillator
Circuit
C
p
C
X2
m
X90100
Example of a single-ended circuit
Example of a differential mode circuit
FN8156.0
February 2, 2005
6
X90100
Packaging Information
8-Lead Miniature Small Outline Gull Wing Package Type M
0.118 ± 0.002
(3.00 ± 0.05)
0.012 + 0.006 / -0.002
0.0256 (0.65) Typ.
(0.30 + 0.15 / -0.05)
R 0.014 (0.36)
0.118 ± 0.002
(3.00 ± 0.05)
0.030 (0.76)
0.0216 (0.55)
7° Typ.
0.036 (0.91)
0.032 (0.81)
0.0256" Typical
0.040 ± 0.002
(1.02 ± 0.05)
0.008 (0.20)
0.004 (0.10)
0.025"
Typical
0.220"
0.150 (3.81)
Ref.
0.193 (4.90)
Ref.
0.020"
Typical
8 Places
0.007 (0.18)
0.005 (0.13)
FOOTPRINT
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8156.0
February 2, 2005
7
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