X28HC256JM-15T1 [RENESAS]
32KX8 EEPROM 5V, 150ns, PQCC32, PLASTIC, MS-016AE, LCC-32;
| 型号： | X28HC256JM-15T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 32KX8 EEPROM 5V, 150ns, PQCC32, PLASTIC, MS-016AE, LCC-32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X28HC256
256k, 32k x 8-Bit
Data Sheet
September 21, 2011
FN8108.3
5V, Byte Alterable EEPROM
Features
The X28HC256 is a second generation high performance
CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s
proprietary, textured poly floating gate technology, providing
a highly reliable 5V only nonvolatile memory.
• Access time: 70ns
• Simple byte and page write
- Single 5V supply
- No external high voltages or VP-P control circuits
- Self-timed
The X28HC256 supports a 128-byte page write operation,
effectively providing a 24µs/byte write cycle, and enabling
the entire memory to be typically rewritten in less than 0.8
seconds. The X28HC256 also features DATA Polling and
Toggle Bit Polling, two methods of providing early end of
write detection. The X28HC256 also supports the JEDEC
standard Software Data Protection feature for protecting
against inadvertent writes during power-up and power-down.
- No erase before write
- No complex programming algorithms
- No overerase problem
• Low power CMOS
- Active: 60mA
- Standby: 500µA
Endurance for the X28HC256 is specified as a minimum
1,000,000 write cycles per byte and an inherent data
retention of 100 years.
• Software data protection
- Protects data against system level inadvertent writes
• High speed page write capability
• Highly reliable Direct Write™ cell
- Endurance: 1,000,000 cycles
- Data retention: 100 years
• Early end of write detection
- DATA polling
- Toggle bit polling
• Pb-free available (RoHS compliant)
Block Diagram
256kBIT
EEPROM
ARRAY
X BUFFERS
LATCHES AND
DECODER
A
TO A
14
0
ADDRESS
INPUTS
I/O BUFFERS
Y BUFFERS
LATCHES AND
DECODER
AND LATCHES
I/O TO I/O
0
7
DATA INPUTS/OUTPUTS
CE
CONTROL
LOGIC AND
TIMING
OE
WE
V
CC
SS
V
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2005-2007, 2010, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
X28HC256
Ordering Information
ACCESS TIME TEMP. RANGE
PART NUMBER
X28HC256J-15*
PART MARKING
(ns)
(°C)
PACKAGE
PKG. DWG. #
N32.45x55
N32.45x55
N32.45x55
N32.45x55
E28.6
X28HC256J-15 HY
X28HC256J-15 ZHY
X28HC256JI-15 HY
X28HC256JI-15 ZHY
X28HC256P-15 HY
0 to +70
32 Ld PLCC
X28HC256JZ-15* (Note)
X28HC256JI-15*, **
0 to +70
32 Ld PLCC (Pb-free)
32 Ld PLCC
-40 to +85
-40 to +85
0 to +70
X28HC256JIZ-15* (Note)
X28HC256P-15****
32 Ld PLCC (Pb-free)
28 Ld PDIP
X28HC256PZ-15*** (Note) X28HC256P-15 HYZ
X28HC256PI-15**** X28HC256PI-15 HY
X28HC256PIZ-15*** (Note) X28HC256PI-15 HYZ
0 to +70
28 Ld PDIP (Pb-free)
28 Ld PDIP
E28.6
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
E28.6
28 Ld PDIP (Pb-free)
28 Ld SOIC (300 mil)
28 Ld SOIC (300 mil) (Pb-free)
32 Ld PLCC
E28.6
X28HC256SI-15*
X28HC256SI-15 HY
X28HC256SI-15 HYZ
X28HC256J-12 HY
X28HC256J-12 ZHY
X28HC256JI-12 HY
X28HC256JI-12 ZHY
X28HC256P-12 HY
MDP0027
MDP0027
N32.45x55
N32.45x55
N32.45x55
N32.45x55
E28.6
X28HC256SIZ-15 (Note)
X28HC256J-12*
X28HC256JZ-12* (Note)
X28HC256JI-12*
0 to +70
32 Ld PLCC (Pb-free)
32 Ld PLCC
-40 to +85
-40 to +85
0 to +70
X28HC256JIZ-12* (Note)
X28HC256P-12****
32 Ld PLCC (Pb-free)
28 Ld PDIP
X28HC256PZ-12*** (Note) X28HC256P-12 HYZ
X28HC256PI-12**** X28HC256PI-12 HY
X28HC256PIZ-12*** (Note) X28HC256PI-12 HYZ
0 to +70
28 Ld PDIP (Pb-free)
28 Ld PDIP
E28.6
-40 to +85
-40 to +85
0 to +70
E28.6
28 Ld PDIP (Pb-free)
28 Ld SOIC (300 mils)
28 Ld SOIC (300 mils) (Pb-free)
28 Ld SOIC (300 mils)
28 Ld SOIC (300 mils) (Pb-free)
32 Ld PLCC (Pb-free)
32 Ld PLCC
E28.6
X28HC256S-12
X28HC256S-12 HY
X28HC256S-12 HYZ
X28HC256SI-12 HY
X28HC256SI-12 HYZ
X28HC256J-90 ZHY
X28HC256JI-90 HY
X28HC256JI-90 ZHY
X28HC256P-90 HY
120
MDP0027
MDP0027
MDP0027
MDP0027
N32.45x55
N32.45x55
N32.45x55
E28.6
X28HC256SZ-12 (Note)
X28HC256SI-12
0 to +70
-40 to +85
-40 to +85
0 to +70
X28HC256SIZ-12 (Note)
X28HC256JZ-90* (Note)
X28HC256JI-90*
-40 to +85
-40 to +85
0 to +70
X28HC256JIZ-90* (Note)
X28HC256P-90****
32 Ld PLCC (Pb-free)
28 Ld PDIP
90
X28HC256PZ-90*** (Note) X28HC256P-90 HYZ
0 to +70
28 Ld PDIP (Pb-free)
28 Ld PDIP (Pb-free)
28 Ld SOIC (300 mils)
28 Ld SOIC (300 mils)
28 Ld SOIC (300 mils) (Pb-free)
E28.6
X28HC256PIZ-90 (Note)
X28HC256S-90
X28HC256PI-90 HYZ
X28HC256S-90 HY
X28HC256SI-90 HY
X28HC256SI-90 HYZ
-40 to +85
0 to +70
E28.6
MDP0027
MDP0027
MDP0027
X28HC256SI-90
-40 to +85
-40 to +85
X28HC256SIZ-90 (Note)
*Add "T1" suffix for tape and reel.
**Add "T2" suffix for tape and reel.
***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
****Part at Prenotification (will become obsolete).
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8108.3
September 21, 2011
2
X28HC256
Pinouts
X28HC256
(28 LD FLATPACK, PDIP, SOIC)
TOP VIEW
X28HC256
(32 LD PLCC, LCC)
TOP VIEW
A
A
1
28
27
26
25
24
23
22
V
CC
14
12
2
WE
4
3
2
1 32 31 30
29
3
A
A
A
A
A
A
A
A
A
13
7
6
5
4
3
2
1
0
A
A
A
A
A
A
A
5
6
7
8
9
A
8
6
5
4
3
2
1
0
4
A
8
28
27
26
25
24
23
22
21
A
9
5
A
9
A
11
6
A
11
NC
OE
7
OE
X28HC256
X28HC256
8
21
20
19
18
17
16
15
A
10
A
10
11
12
13
10
9
CE
I/O
CE
I/O
10
11
12
13
14
7
NC
I/O
7
I/O
I/O
I/O
I/O
I/O
I/O
6
5
4
3
0
1
2
I/O
0
6
14 15 16 17 18 19 20
I/O
V
SS
Pin Descriptions
Pin Names
SYMBOL
A0 to A14
I/O0 to I/O7
WE
DESCRIPTION
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Addresses (A to A )
0
14
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
CE
OE
VCC
Output Enable (OE)
VSS
Ground
The Output Enable input controls the data output buffers,
and is used to initiate read operations.
NC
No Connect
Data In/Data Out (I/O to I/O )
0
7
Device Operation
Data is written to or read from the X28HC256 through the I/O
pins.
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE or CE is HIGH.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC256.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28HC256 supports both a CE
and WE controlled write cycle. That is, the address is latched
by the falling edge of either CE or WE, whichever occurs
last. Similarly, the data is latched internally by the rising edge
of either CE or WE, whichever occurs first. A byte write
operation, once initiated, will automatically continue to
completion, typically within 3ms.
FN8108.3
September 21, 2011
3
X28HC256
cease, and the device will be accessible for additional read
Page Write Operation
and write operations.
The page write feature of the X28HC256 allows the entire
memory to be written in typically 0.8 seconds. Page write
allows up to one hundred twenty-eight bytes of data to be
consecutively written to the X28HC256, prior to the
commencement of the internal programming cycle. The host
can fetch data from another device within the system during
a page write operation (change the source address), but the
page address (A7 through A14) for each subsequent valid
write cycle to the part during this operation must be the same
as the initial page address.
DATA Polling I/O
DATA Polling can effectively halve the time for writing to the
X28HC256. The timing diagram in Figure 2 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 3 illustrates one method of implementing the routine.
The Toggle Bit I/O
The Toggle Bit can eliminate the chore of saving and fetching
the last address and data in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28HC256 memories that is frequently updated.
The timing diagram in Figure 4 illustrates the sequence of
events on the bus. The software flow diagram in Figure 5
illustrates a method for polling the Toggle Bit.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to one hundred twenty-seven bytes in
the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of the
preceding WE. If a subsequent WE HIGH to LOW transition
is not detected within 100µs, the internal automatic
Hardware Data Protection
The X28HC256 provides two hardware features that protect
nonvolatile data from inadvertent writes.
programming cycle will commence. There is no page write
window limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access the
device within the byte load cycle time of 100µs.
• Default VCC Sense—All write functions are inhibited when
VCC is 3.5V typically.
Write Operation Status Bits
Write Inhibit—Holding either OE LOW, WE HIGH, or CE
HIGH will prevent an inadvertent write cycle during power-up
and power-down, maintaining data integrity.
The X28HC256 provides the user two write operation status
bits. These can be used to optimize a system write cycle
time. The status bits are mapped onto the I/O bus as shown
in Figure 1.
I/O
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
FIGURE 1. STATUS BIT ASSIGNMENT
DATA Polling (I/O )
7
The X28HC256 features DATA Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28HC256. This eliminates
additional interrupt inputs or external hardware. During the
internal programming cycle, any attempt to read the last byte
written will produce the complement of that data on I/O7 (i.e.,
write data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O7 will reflect true data.
Toggle Bit (I/O )
6
The X28HC256 also provides another method for
determining when the internal write cycle is complete. During
the internal programming cycle I/O6 will toggle from HIGH to
LOW and LOW to HIGH on subsequent attempts to read the
device. When the internal cycle is complete the toggling will
FN8108.3
September 21, 2011
4
X28HC256
LAST
WRITE
WE
CE
OE
V
IH
V
OH
HIGH Z
I/O
7
V
OL
X28HC256
READY
A
TO A
14
An
An
An
An
An
An
An
0
FIGURE 2. DATA POLLING BUS SEQUENCE
WRITE DATA
WRITES
NO
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
7
NO
COMPARE?
YES
X28HC256
READY
FIGURE 3. DATA POLLING SOFTWARE FLOW
FN8108.3
September 21, 2011
5
X28HC256
LAST
WRITE
WE
CE
OE
V
OH
HIGH Z
I/O
6
*
*
V
OL
X28C512, X28C513
READY
* I/O6 Beginning and ending state of I/O6 will vary.
FIGURE 4. TOGGLE BIT BUS SEQUENCE
¬
The internal software data protection circuit is enabled after
the first write operation, utilizing the software algorithm. This
circuit is nonvolatile, and will remain set for the life of the
device unless the reset command is issued.
LAST WRITE
YES
Once the software protection is enabled, the X28HC256 is
also protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be
issued prior to writing additional data to the device.
LOAD ACCUM
FROM ADDR n
Software Algorithm
Selecting the software data protection mode requires the
host system to precede data write operations by a series of
three write operations to three specific addresses. Refer to
Figures 6 and 7 for the sequence. The three-byte sequence
opens the page write window, enabling the host to write from
one to one hundred twenty-eight bytes of data. Once the
page load cycle has been completed, the device will
automatically be returned to the data protected state.
COMPARE
ACCUM WITH
ADDR n
NO
COMPARE
OK?
YES
X28C256
READY
FIGURE 5. TOGGLE BIT SOFTWARE FLOW
Software Data Protection
The X28HC256 offers a software-controlled data protection
feature. The X28HC256 is shipped from Intersil with the
software data protection NOT ENABLED; that is, the device
will be in the standard operating mode. In this mode data
should be protected during power-up/down operations
through the use of external circuits. The host would then
have open read and write access of the device once VCC
was stable.
The X28HC256 can be automatically protected during
power-up and power-down (without the need for external
circuits) by employing the software data protection feature.
FN8108.3
September 21, 2011
6
X28HC256
Software Data Protection
V
CC
(V
)
CC
0V
DATA
ADDRESS
AA
5555
55
2AAA
A0
5555
WRITES
OK
WRITE
PROTECTED
t
WC
CE
≤t
BYTE
OR
BLC MAX
WE
AGE
FIGURE 6. TIMING SEQUENCE—BYTE OR PAGE WRITE
Regardless of whether the device has previously been
protected or not, once the software data protection algorithm
is used and data has been written, the X28HC256 will
automatically disable further writes unless another command
is issued to cancel it. If no further commands are issued the
X28HC256 will be write protected during power-down and
after any subsequent power-up.
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA A0
TO ADDRESS
5555
Resetting Software Data Protection
BYTE/PAGE
LOAD ENABLED
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an
EEPROM programmer, the following six step algorithm will
reset the internal protection circuit. After tWC, the X28HC256
will be in standard operating mode.
WRITE DATA XX
TO ANY
ADDRESS
OPTIONAL
BYTE/PAGE
LOAD OPERATION
WRITE LAST
BYTE TO
LAST ADDRESS
Note: Once initiated, the sequence of write operations
should not be interrupted.
AFTER t
WC
RE-ENTERS DATA
PROTECTED STATE
FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA
PROTECTION
V
CC
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
STANDARD
OPERATING
MODE
DATA
ADDRESS
t
WC
CE
WE
FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE
FN8108.3
September 21, 2011
7
X28HC256
System Considerations
WRITE DATA AA
TO ADDRESS
5555
Because the X28HC256 is frequently used in large memory
arrays, it is provided with a two line control architecture for
both read and write operations. Proper usage can provide
the lowest possible power dissipation, and eliminate the
possibility of contention where multiple I/O pins share the
same bus.
WRITE DATA 55
TO ADDRESS
2AAA
To gain the most benefit, it is recommended that CE be
decoded from the address bus and be used as the primary
device selection input. Both OE and WE would then be
common among all devices in the array. For a read
operation, this assures that all deselected devices are in
their standby mode, and that only the selected device(s)
is/are outputting data on the bus.
WRITE DATA 80
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
Because the X28HC256 has two power modes, standby and
active, proper decoupling of the memory array is of prime
concern. Enabling CE will cause transient current spikes.
The magnitude of these spikes is dependent on the output
capacitive loading of the l/Os. Therefore, the larger the array
sharing a common bus, the larger the transient spikes. The
voltage peaks associated with the current transients can be
suppressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recommended that
a 0.1µF high frequency ceramic capacitor be used between
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 20
TO ADDRESS
5555
VCC and VSS at each device. Depending on the size of the
array, the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic bulk
capacitor be placed between VCC and VSS for each eight
devices employed in the array. This bulk capacitor is
employed to overcome the voltage droop caused by the
inductive effects of the PC board traces.
AFTER t
,
WC
RE-ENTERS
UNPROTECTED
STATE
FIGURE 9. WRITE SEQUENCE FOR RESETTING SOFTWARE
DATA PROTECTION
FN8108.3
September 21, 2011
8
X28HC256
Absolute Maximum Ratings
Thermal Information
Voltage on any Pin with Respect to VSS . . . . . . . . . . . . . -1V to +7V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
X28HC256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
X28HC256I, X28HC256M . . . . . . . . . . . . . . . . . .-65°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
DC Electrical Specifications Over Recommended Operating Conditions, Unless Otherwise Specified.
LIMITS
TYP
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 1)
MAX
UNIT
V
CC Active Current
ICC
CE = OE = VIL, WE = VIH, All I/O’s = open,
address inputs = .4V/2.4V levels @ f = 10MHz
30
60
mA
(TTL Inputs)
V
CC Standby Current
ISB1
CE = VIH, OE = VIL, All I/O’s = open, other inputs = VIH
1
2
mA
µA
(TTL Inputs)
VCC Standby Current
(CMOS Inputs)
ISB2
CE = VCC - 0.3V, OE = GND, All I/Os = open, other
inputs = VCC - 0.3V
200
500
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
NOTES:
ILI
VIN = VSS to VCC
10
10
µA
µA
V
ILO
VOUT = VSS to VCC, CE = VIH
V
lL (Note 2)
IH (Note 2)
VOL
-1
2
0.8
V
VCC + 1
0.4
V
IOL = 6mA
V
VOH
IOH = -4mA
2.4
V
1. Typical values are for TA = +25°C and nominal supply voltage.
2. VIL min. and VIH max. are for reference only and are not tested.
Power-Up Timing
PARAMETER
SYMBOL
PUR, (Note 3)
PUW, (Note 3)
MAX
100
5
UNIT
µs
Power-up to read
Power-up to write
NOTE:
t
t
ms
3. This parameter is periodically sampled and not 100% tested.
Capacitance
T
= +25°C, f = 1MHz, VCC = 5V.
A
SYMBOL
TEST
CONDITIONS
VI/O = 0V
VIN = 0V
MAX
UNIT
CI/O (Note 9)
Input/output capacitance
Input capacitance
10
6
pF
pF
CIN (Note 9)
FN8108.3
September 21, 2011
9
X28HC256
Endurance and Data Retention
PARAMETER
MIN
MAX
UNIT
Cycles
Years
Endurance
1,000,000
100
Data retention
AC Conditions of Test
Symbol Table
Input pulse levels
0V to 3V
WAVEFORM
INPUTS
OUTPUTS
Input rise and fall times
Input and output timing levels
5ns
Must be
steady
Will be
steady
1.5V
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
Mode Selection
CE
OE
WE
MODE
Read
Write
I/O
DOUT
DIN
POWER
active
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
L
L
H
L
H
L
active
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
H
X
X
Standby and write High Z
inhibit
standby
N/A
Center Line
is High
Impedance
X
X
L
X
H
Write inhibit
Write inhibit
—
—
—
—
X
Equivalent AC Load Circuit
5V
1.92kΩ
OUTPUT
1.37kΩ
30pF
AC Electrical Specifications Over Recommended Operating Conditions, Unless Otherwise Specified.
X28HC256-70 X28HC256-90 X28HC256-12
X28HC256-15
PARAMETER
Read Cycle Time
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ns
t
RC (Note 5)
70
90
120
150
Chip Enable Access Time
Address Access Time
t
CE (Note 5)
70
70
35
90
90
40
120
120
50
150
150
50
ns
tAA (Note 5)
tOE
ns
Output Enable Access Time
CE LOW to Active Output
OE LOW to Active Output
CE HIGH to High Z Output
OE HIGH to High Z Output
Output Hold from Address Change
ns
tLZ (Note 4)
tOLZ (Note 4)
tHZ (Note 4)
tOHZ (Note4)
tOH
0
0
0
0
0
0
0
0
ns
ns
35
35
40
40
50
50
50
50
ns
ns
0
0
0
0
ns
FN8108.3
September 21, 2011
10
X28HC256
Read Cycle
ADDRESS
CE
t
RC
t
CE
t
OE
OE
V
IH
WE
t
t
OHZ
OLZ
t
t
t
t
HZ
LZ
OH
AA
HIGH Z
DATA VALID
DATA VALID
DATA I/O
NOTES:
4. tLZ min., tHZ, tOLZ min. and tOHZ are periodically sampled and not 100% tested, tHZ and tOHZ are measured with CL = 5pF, from the point when
CE, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
5. For faster 256k products, refer to X28VC256 product line.
Write Cycle Limits
TYP
PARAMETER
SYMBOL
WC (Note 7)
tAS
MIN
(Note 6)
MAX
UNIT
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
t
3
5
0
50
0
tAH
tCS
tCH
0
CE Pulse Width
tCW
50
0
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
tOES
tOEH
0
tWP
50
50
WE HIGH Recovery (page write only)
tWPH (Note 8)
Data Valid
tDV
tDS
tDH
1
Data Setup
50
0
Data Hold
Delay to Next Write After Polling is True
Byte Load Cycle
t
DW (Note 8)
tBLC
10
0.15
100
NOTES:
6. Typical values are for TA = +25°C and nominal supply voltage.
7. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to automatically complete the internal write operation.
8. tWPH and tDW are periodically sampled and not 100% tested.
FN8108.3
September 21, 2011
11
X28HC256
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
t
CS
CH
CE
OE
t
t
OEH
OES
t
WP
WE
DATA IN
DATA VALID
HIGH Z
t
t
DH
DS
DATA OUT
CE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
CW
CE
OE
t
OES
t
OEH
t
t
t
CS
CH
WE
DATA VALID
DATA IN
t
DS
DH
HIGH Z
DATA OUT
FN8108.3
September 21, 2011
12
X28HC256
Page Write Cycle
OE
(NOTE 9)
CE
t
t
BLC
WP
WE
t
WPH
ADDRESS
(NOTE 10)
LAST BYTE
BYTE n + 2
I/O
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n + 1
t
WC
*For each successive write within the page write operation, A7 to A15 should be the same or
writes to an unknown address could occur.
NOTES:
9. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch
data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
10. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the
CE or WE controlled write cycle timing.
DATA Polling Timing Diagram (Note 11)
ADDRESS
CE
A
A
A
n
n
n
WE
t
t
OEH
OES
OE
t
DW
D
= X
D
= X
D = X
OUT
I/O
7
IN
OUT
t
WC
FN8108.3
September 21, 2011
13
X28HC256
Toggle Bit Timing Diagram (Note 11)
CE
WE
t
OES
t
OEH
OE
t
DW
HIGH Z
I/O
*
6
*
t
WC
* I/O6 beginning and ending state will vary, depending upon actual tWC
.
NOTE:
11. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
FN8108.3
September 21, 2011
14
X28HC256
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.056 (1.42)
PIN (1)
IDENTIFIER
0.004 (0.10)
C
N32.45x55 (JEDEC MS-016AE ISSUE A)
0.042 (1.07)
0.048 (1.22)
32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
0.050 (1.27) TP
ND
0.025 (0.64)
0.045 (1.14)
R
INCHES
MILLIMETERS
C
L
SYMBOL
MIN
MAX
MIN
3.18
MAX
3.55
NOTES
A
A1
D
0.125
0.060
0.485
0.447
0.188
0.585
0.547
0.238
0.140
0.095
0.495
0.453
0.223
0.595
0.553
0.273
-
1.53
2.41
-
D2/E2
D2/E2
12.32
11.36
4.78
12.57
11.50
5.66
-
C
L
D1
D2
E
3
E1
E
4, 5
NE
14.86
13.90
6.05
15.11
14.04
6.93
-
VIEW “A”
E1
E2
N
3
4, 5
0.015 (0.38)
MIN
28
7
28
7
6
A1
A
ND
NE
7
7
D1
D
9
9
SEATING
PLANE
0.020 (0.51) MAX
3 PLCS
-C-
Rev. 0 7/98
NOTES:
0.026 (0.66)
0.032 (0.81)
0.050 (1.27)
MIN
1. Controlling dimension: INCH. Converted millimeter dimen-
sions are not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Al-
lowable mold protrusion is 0.010 inch (0.25mm) per side.
Dimensions D1 and E1 include mold mismatch and are mea-
sured at the extreme material condition at the body parting
line.
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
(0.12)
0.005
M
A S - B S D S
-C-
4. To be measured at seating plane
contact point.
VIEW “A” TYP.
5. Centerline to be determined where center leads exit plastic
body.
6. “N” is the number of terminal positions.
7. ND denotes the number of leads on the two shorts sides of the
package, one of which contains pin #1. NE denotes the num-
ber of leads on the two long sides of the package.
FN8108.3
September 21, 2011
15
X28HC256
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
0.010
A1
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8108.3
September 21, 2011
16
X28HC256
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
N
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INCHES
MILLIMETERS
INDEX
1
2
3
N/2
AREA
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.125
0.014
0.030
0.008
1.380
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
D
E
0.195
0.022
0.070
0.015
1.565
-
4.95
0.558
1.77
0.381
39.7
-
-
BASE
PLANE
A2
A
-
SEATING
PLANE
B1
C
8
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
35.1
5
eC
C
B
D1
E
0.13
15.24
12.32
5
eB
0.010 (0.25) M
C
B S
0.625
0.580
15.87
14.73
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
eA
eB
L
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
28
28
JEDEC seating plane gauge GS-3.
Rev. 1 12/00
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
eA
6. E and
ular to datum
7. eB and eC are measured at the lead tips with the leads unconstrained.
C must be zero or greater.
are measured with the leads constrained to be perpendic-
-C-
.
e
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
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FN8108.3
September 21, 2011
17
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