X28HC256JM-70 [INTERSIL]
5 Volt, Byte Alterable EEPROM; 5伏，可变的字节EEPROM
| 型号： | X28HC256JM-70 |
| 厂家： | 
Intersil |
| 描述： | 5 Volt, Byte Alterable EEPROM |
| 文件： | 总14页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X28HC256
®
256K, 32K x 8 Bit
Data Sheet
June 1, 2005
FN8108.0
DESCRIPTION
5 Volt, Byte Alterable EEPROM
The X28HC256 is a second generation high perfor-
mance CMOS 32K x 8 EEPROM. It is fabricated with
Intersil’s proprietary, textured poly floating gate tech-
nology, providing a highly reliable 5 Volt only nonvola-
tile memory.
FEATURES
• Access time: 70ns
• Simple byte and page write
—Single 5V supply
—No external high voltages or V control circuits
—Self-timed
—No erase before write
—No complex programming algorithms
—No overerase problem
• Low power CMOS
—Active: 60mA
—Standby: 500µA
• Software data protection
—Protects data against system level inadvertent
writes
PP
The X28HC256 supports a 128-byte page write opera-
tion, effectively providing a 24µs/byte write cycle, and
enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28HC256 also features
DATA Polling and Toggle Bit Polling, two methods of
providing early end of write detection. The X28HC256
also supports the JEDEC standard Software Data Pro-
tection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a mini-
mum 1,000,000 write cycles per byte and an inherent
data retention of 100 years.
• High speed page write capability
™
• Highly reliable Direct Write cell
—Endurance: 1,000,000 cycles
—Data retention: 100 years
• Early end of write detection
—DATA polling
—Toggle bit polling
BLOCK DIAGRAM
256Kbit
EEPROM
Array
X Buffers
Latches and
Decoder
A0–A14
Address
Inputs
I/O Buffers
and Latches
Y Buffers
Latches and
DECODER
I/O0–I/O7
Data Inputs/Outputs
CE
Control
OE
Logic and
Timing
WE
VCC
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X28HC256
PIN CONFIGURATION
TSOP
Plastic DIP
CERDIP
Flat Plastic
SOIC
LCC
PLCC
A
A
A
A
A
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
3
4
5
A
1
A
0
I/O
0
6
A
A
A
I/O
1
28
27
26
25
24
23
22
21
20
19
18
17
7
12
14
A14
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
I/O
2
4
3
2
1
32 31 30
NC
WE
A13
A8
A12
A7
NC
V
V
A6
A5
A4
A3
A2
A1
A0
5
29
A8
A9
SS
NC
X28HC256
CC
6
7
28
27
NC
I/O
I/O
I/O
I/O
I/O
A6
3
4
5
6
7
WE
A
A11
NC
OE
A10
A9
A5
13
8
9
26
25
A
8
A11
A4
X28HC256
(Top View)
A
9
A3
OE
A10
A
CE
11
10
11
24
23
X28HC256
A
OE
10
A2
CE
A1
CE
I/O7
I/O6
12
13
22
21
NC
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
A0
I/O0
PGA
14 15 16 17 18 19 20
I/O0
I/O1
I/O1
12
I/O2
13
I/O3
15
I/O5
17
I/O6
18
I/O2
VSS
I/O0
11
A0
10
VSS
14
I/O4
16
I/O7
19
A1
A3
A2
8
X28HC256
A4
CE
20
A10
21
9
7
5
OE
22
A11
23
6
2
A5
A6
A12
VCC
28
A9
24
A8
25
A7
3
WE
27
A13
26
A14
4
1
(Bottom View)
PIN DESCRIPTIONS
Addresses (A -A )
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28HC256.
0
14
The Address inputs select an 8-bit memory location
during a read or write operation.
PIN NAMES
Symbol
A0-A14
I/O0-I/O7
WE
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power con-
sumption is reduced.
CE
Output Enable (OE)
OE
The Output Enable input controls the data output buff-
ers, and is used to initiate read operations.
VCC
VSS
Ground
Data In/Data Out (I/O -I/O )
0
7
NC
No Connect
Data is written to or read from the X28HC256 through
the I/O pins.
FN8108.0
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June 1, 2005
X28HC256
DEVICE OPERATION
Read
Write Operation Status Bits
The X28HC256 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Read operations are initiated by both OE and CE
LOW. The read operation is terminated by either CE or
OE returning HIGH. This two line control architecture
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE or CE is HIGH.
Figure 1. Status Bit Assignment
I/O DP TB
5
4
3
2
1
0
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28HC256 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 3ms.
Reserved
Toggle Bit
DATA Polling
DATA Polling (I/O )
7
The X28HC256 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the
X28HC256. This eliminates additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
Page Write Operation
The page write feature of the X28HC256 allows the
entire memory to be written in typically 0.8 seconds.
Page write allows up to one hundred twenty-eight
bytes of data to be consecutively written to the
X28HC256, prior to the commencement of the internal
programming cycle. The host can fetch data from
another device within the system during a page write
operation (change the source address), but the page
duce the complement of that data on I/O (i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the pro-
7
gramming cycle is complete, I/O will reflect true data.
7
Toggle Bit (I/O )
6
The X28HC256 also provides another method for
determining when the internal write cycle is complete.
address (A through A ) for each subsequent valid
write cycle to the part during this operation must be the
same as the initial page address.
7
14
During the internal programming cycle I/O will toggle
6
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease, and the device will be
accessible for additional read and write operations.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the
host can write an additional one to one hundred
twenty-seven bytes in the same manner as the first
byte was written. Each successive byte load cycle,
started by the WE HIGH to LOW transition, must begin
within 100µs of the falling edge of the preceding WE. If
a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic program-
ming cycle will commence. There is no page write win-
dow limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 100µs.
FN8108.0
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June 1, 2005
X28HC256
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
Last
Write
WE
CE
OE
VIH
VOH
HIGH Z
I/O7
VOL
X28HC256
Ready
A0–A14
An
An
An
An
An
An
An
Figure 3. DATA Polling Software Flow
DATA Polling can effectively halve the time for writing
to the X28HC256. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The soft-
ware flow diagram in Figure 3 illustrates one method
of implementing the routine.
Write Data
No
Writes
Complete?
Yes
Save Last Data
and Address
Read Last
Address
IO7
Compare?
No
Yes
X28HC256
Ready
FN8108.0
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June 1, 2005
X28HC256
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
Last
Write
WE
CE
OE
VOH
HIGH Z
I/O6
*
*
VOL
X28C512/513
Ready
* I/O6 Beginning and ending state of I/O6 will vary.
Figure 5. Toggle Bit Software Flow
HARDWARE DATA PROTECTION
¬
The X28HC256 provides two hardware features that
protect nonvolatile data from inadvertent writes.
Last Write
Yes
– Default V Sense—All write functions are inhibited
CC
when V is 3.5V typically.
CC
– Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
Load Accum
From Addr n
SOFTWARE DATA PROTECTION
The X28HC256 offers a software-controlled data pro-
tection feature. The X28HC256 is shipped from Intersil
with the software data protection NOT ENABLED; that
is, the device will be in the standard operating mode.
In this mode data should be protected during power-
up/down operations through the use of external cir-
cuits. The host would then have open read and write
Compare
Accum with
Addr n
No
Compare
ok?
access of the device once V was stable.
CC
Yes
The X28HC256 can be automatically protected during
power-up and power-down (without the need for exter-
nal circuits) by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation, utilizing the soft-
ware algorithm. This circuit is nonvolatile, and will
remain set for the life of the device unless the reset
command is issued.
X28C256
Ready
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an
array comprised of multiple X28HC256 memories that
is frequently updated. The timing diagram in Figure 4
illustrates the sequence of events on the bus. The
software flow diagram in Figure 5 illustrates a method
for polling the Toggle Bit.
Once the software protection is enabled, the X28HC256 is
also protected from inadvertent and accidental writes in
the powered-up state. That is, the software algorithm must
be issued prior to writing additional data to the device.
FN8108.0
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June 1, 2005
X28HC256
SOFTWARE ALGORITHM
The three-byte sequence opens the page write window,
enabling the host to write from one to one hundred
twenty-eight bytes of data. Once the page load cycle
has been completed, the device will automatically be
returned to the data protected state.
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figure 6 and 7 for the sequence.
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
VCC
0V
(VCC
)
Data
Address
AAA
5555
55
2AAA
A0
5555
Writes
ok
Write
Protected
tWC
CE
≤ tBLC MAX
Byte
or
Age
WE
Figure 7. Write Sequence for Software Data
Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the
X28HC256 will automatically disable further writes
unless another command is issued to cancel it. If no
further commands are issued the X28HC256 will be
write protected during power-down and after any sub-
sequent power-up.
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data A0
to Address
5555
Byte/Page
Load Enabled
Write Data XX
to Any
Address
Optional
Byte/Page
Load Operation
Write Last
Byte to
Last Address
After tWC
Re-Enters Data
Protected State
FN8108.0
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June 1, 2005
X28HC256
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
VCC
AAA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
Standard
Operating
Mode
Data
Address
tWC
CE
WE
Figure 9. Write Sequence for resetting Software
Data Protection
Note: Once initiated, the sequence of write operations
should not be interrupted.
SYSTEM CONSIDERATIONS
Write Data AA
to Address
5555
Because the X28HC256 is frequently used in large
memory arrays, it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipa-
tion, and eliminate the possibility of contention where
multiple I/O pins share the same bus.
Write Data 55
to Address
2AAA
To gain the most benefit, it is recommended that CE
be decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected
devices are in their standby mode, and that only the
selected device(s) is/are outputting data on the bus.
Write Data 80
to Address
5555
Write Data AA
to Address
5555
Because the X28HC256 has two power modes,
standby and active, proper decoupling of the memory
array is of prime concern. Enabling CE will cause tran-
sient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the l/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be sup-
pressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recom-
mended that a 0.1µF high frequency ceramic capacitor
Write Data 55
to Address
2AAA
Write Data 20
to Address
5555
be used between V
Depending on the size of the array, the value of the
capacitor may have to be larger.
and V
at each device.
CC
SS
After tWC
,
Re-Enters
Unprotected
State
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V
and V
for
CC
SS
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an EEPROM programmer, the following six step algo-
each eight devices employed in the array. This bulk
capacitor is employed to overcome the voltage droop
caused by the inductive effects of the PC board traces.
rithm will reset the internal protection circuit. After t
the X28HC256 will be in standard operating mode.
,
WC
FN8108.0
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June 1, 2005
X28HC256
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
X28HC256 ....................................... -10°C to +85°C
X28HC256I, X28HC256M.............. -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on any pin with
respect to V
........................................ -1V to +7V
SS
D.C. output current.............................................10mA
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
+125°C
Supply Voltage
Limits
X28HC256
5V ±10%
-40°C
-55°C
Military
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
(7)
Symbol
Parameter
Min. Typ.
Max.
Unit
Test Conditions
ICC
VCC active current (TTL
Inputs)
30
60
mA CE = OE = VIL, WE = VIH, All I/O’s = open,
address inputs = .4V/2.4V levels @ f = 10MHz
ISB1
ISB2
VCC standby current
(TTL Inputs)
1
2
mA CE = VIH, OE = VIL, All I/O’s = open, other
inputs = VIH
VCC standby current
(CMOS Inputs)
200
500
µA
CE = VCC - 0.3V, OE = GND, All I/Os = open,
other inputs = VCC - 0.3V
ILI
Input leakage current
Output leakage current
Input LOW voltage
10
10
µA
µA
V
VIN = VSS to VCC
ILO
VOUT = VSS to VCC, CE = VIH
(2)
VlL
-1
2
0.8
(2)
VIH
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
VCC + 1
0.4
V
VOL
VOH
V
IOL = 6mA
2.4
V
IOH = -4mA
Notes: (1) Typical values are for TA = 25°C and nominal supply voltage.
(2) VIL min. and VIH max. are for reference only and are not tested.
POWER-UP TIMING
Symbol
Parameter
Max.
100
5
Unit
µs
(3)
tPUR
Power-up to read
Power-up to write
(3)
tPUW
ms
Note: (3) This parameter is periodically sampled and not 100% tested.
FN8108.0
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June 1, 2005
X28HC256
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Test
Max.
10
Unit
pF
Conditions
VI/O = 0V
VIN = 0V
(9)
CI/O
Input/output capacitance
Input capacitance
(9)
CIN
6
pF
ENDURANCE AND DATA RETENTION
Parameter
Endurance
Min.
1,000,000
100
Max.
Unit
Cycles
Years
Data retention
A.C. CONDITIONS OF TEST
SYMBOL TABLE
Input pulse levels
0V to 3V
WAVEFORM
INPUTS
OUTPUTS
Input rise and fall times
Input and output timing levels
5ns
Must be
steady
Will be
steady
1.5V
MODE SELECTION
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
CE
L
OE WE
Mode
Read
Write
I/O
DOUT
DIN
Power
active
active
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
L
H
X
H
L
L
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
H
X
Standby and High Z standby
write inhibit
N/A
Center Line
is High
Impedance
X
X
L
X
H
Write inhibit
Write inhibit
—
—
—
—
X
EQUIVALENT A.C. LOAD CIRCUIT
5V
1.92kΩ
OUTPUT
1.37kΩ
30pF
FN8108.0
June 1, 2005
9
X28HC256
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28HC256-70 X28HC256-90 X28HC256-12 X28HC256-15
Symbol
Parameter
Read cycle time
Min. Max. Min. Max. Min. Max. Min.
Max. Unit
(5)
tRC
70
90
120
150
ns
(5)
tCE
Chip enable access time
Address access time
70
70
35
90
90
40
120
120
50
150
150
50
ns
ns
ns
ns
ns
ns
ns
ns
(5)
tAA
tOE
(4)
Output enable access time
CE LOW to active output
OE LOW to active output
CE HIGH to high Z output
OE HIGH to high Z output
Output hold from address change
tLZ
0
0
0
0
0
0
0
0
(4)
tOLZ
(4)
tHZ
35
35
40
40
50
50
50
50
(4)
tOHZ
tOH
0
0
0
0
Read Cycle
tRC
Address
tCE
CE
tOE
OE
VIH
WE
tOLZ
tOHZ
tLZ
tOH
tHZ
Data Valid
HIGH Z
Data Valid
Data I/O
tAA
Notes: (4) tLZ min., tHZ, tOLZ min. and tOHZ are periodically sampled and not 100% tested, tHZ and tOHZ are measured with CL = 5pF, from the
point when CE, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
(5) For faster 256K products, refer to X28VC256 product line.
FN8108.0
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June 1, 2005
X28HC256
Write Cycle Limits
(6)
Symbol
Parameter
Min.
Typ.
Max.
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
(7)
tWC
Write cycle time
3
5
tAS
tAH
tCS
Address setup time
Address hold time
Write setup time
Write hold time
0
50
0
tCH
0
tCW
tOES
tOEH
tWP
CE pulse width
50
0
OE HIGH setup time
OE HIGH hold time
WE pulse width
0
50
50
(8)
tWPH
tDV
WE HIGH recovery (page write only)
Data valid
1
tDS
Data setup
50
0
tDH
Data hold
(8)
tDW
Delay to next write after polling is true
Byte load cycle
10
tBLC
0.15
100
Notes: (6) Typical values are for TA = 25°C and nominal supply voltage.
(7) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time
the device requires to automatically complete the internal write operation.
(8) tWPH and tDW are periodically sampled and not 100% tested.
WE Controlled Write Cycle
tWC
Address
tAS
tAH
tCS
tCH
CE
OE
tOES
tOEH
tWP
WE
Data In
Data Out
Data Valid
tDS
tDH
HIGH Z
FN8108.0
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June 1, 2005
X28HC256
CE Controlled Write Cycle
tWC
Address
tAS
tAH
tCW
CE
tOES
OE
tOEH
tCS
tCH
WE
Data Valid
Data In
tDS
tDH
HIGH Z
Data Out
Page Write Cycle
OE(9)
CE
tBLC
tWP
WE
tWPH
Address(10)
Last Byte
I/O
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
Byte n+2
tWC
*For each successive write within the page write operation, A7–A15 should be the same or
writes to an unknown address could occur.
Notes: (9) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH
to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a
polling operation.
(10)The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
either the CE or WE controlled write cycle timing.
FN8108.0
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June 1, 2005
X28HC256
(11)
DATA Polling Timing Diagram
Address
CE
An
An
An
WE
tOEH
tOES
OE
tDW
DOUT = X
DIN = X
DOUT = X
tWC
I/O7
(11)
Toggle Bit Timing Diagram
CE
WE
tOES
tOEH
OE
tDW
HIGH Z
I/O6
*
*
tWC
* I/O6 beginning and ending state will vary, depending upon actual tWC
.
Note: (11)Polling operations are by definition read cycles and are therefore subject to read cycle timings.
FN8108.0
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June 1, 2005
X28HC256
Ordering Information
Device
X28HC256
X
X
-X
Access Time
-70 = 70ns
-90 = 90ns
-12 = 120ns
-15 = 150ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
M = Military = -55°C to +125°C
MB = MIL-STD-883
Package
P = 28-Lead Plastic DIP
D = 28-Lead CERDIP
J = 32-Lead PLCC
S = 28-Lead plastic SOIC
E = 32-Pad LCC
K = 28-Pin grid array
F = 28-Lead flat pack
T = 32-Lead TSOP
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8108.0
14
June 1, 2005
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