UPD77115GK-9EU-A [RENESAS]
IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC;
| 型号： | UPD77115GK-9EU-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC |
| 文件： | 总56页 (文件大小：475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD77115, 77115A
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR
DESCRIPTION
The µPD77115 and µPD77115A are 16-bit fixed-point digital signal processors (DSP).
The µPD77115 and µPD77115A are RAM based DSP and have the specific circuit for audio application.
Unless otherwise specified, the µPD77115 refers to µPD77115 and 77115A.
For details of the functions of the µPD77115, refer to the following User’s Manuals:
µPD77111 Family User’s Manual - Architecture : U14623E
µPD77016 Family User’s Manual - Instructions
: U13116E
FEATURES
•
•
Instruction cycle (operating clock)
13.3 ns MIN. (75 MHz MAX.)
Memory
•
Internal instruction RAM
Internal data RAM
11.5K words × 32 bits
•
16K words × 16 bits × 2 banks
•
•
•
Peripherals
• Audio serial interface
• Secure Digital (SD) card interface
• 16-bit timer
• 16-bit host interface
• 8-bit port
Supply voltage
• DSP core voltage
2.0 to 2.7 V (MAX. operation speed 50 MHz)
2.3 to 2.7 V (MAX. operation speed 75 MHz)
• I/O pin voltage
2.7 to 3.6 V
Power consumption
TYP. 50 mW (2.0 V, 50 MHz operation)
ORDERING INFORMATION
Part Number
Package
µPD77115F1-CN6
80-pin plastic FBGA (9 × 9)
µPD77115GK-9EU
µPD77115AF1-xxx-CN6
80-pin plastic TQFP (fine pitch) (12 × 12)
80-pin plastic FBGA (9 × 9)
Remark xxx indicates ROM code suffix.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U14867EJ5V0DS00 (5th edition)
Date Published August 2004 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2000, 2004
X bus
Y bus
Data memory unit
Peripheral units
X memory
data
addressing
unit
Y memory
data
addressing
unit
Audio serial
interface
R0 to R7
X memory
Y memory
SD card
interface
DMA bus
Main bus
MAC
16 x 16 + 40 -> 40
ALU(40)
BSFT
Port
Program
control unit
Loop control
Instruction
memory
PC stack
Host
interface
stack
Interrupt
control
Operation unit
CPU control
PLL
Timer
INT1 to INT4
RESET WAKEUP CLKOUT
CLKIN PLL0 to PLL3Note
Note The PLL0 to PLL3 pins are multiplexed with the P4 to P7 pins.
Debug
interface
µPD77115, 77115A
FUNCTION PIN GROUPS
+ 2.5 V
IVDD
+ 3 V
EVDD
SO
RESET
INT1 to INT4
Reset,
Interrupt
SOEN/LRCLK
SCK/BCLK
SI
Audio
Serial
Interface
(4)
CLKIN
CLKOUT
SIEN/MCLK
Clock
SDDAT
SDCR
SDCLK
SD Card
Interface
System Control
WAKEUP
P0 to P3,P4/PLL0 to P7/PLL3
Port
(8)
(2)
HCS
HA0,HA1
HRD
HRE
HWR
Host
Interface
HWE
HD0 to HD15
(16)
Debug
Interface
TDO,TICE
TCK,TDI,TMS,TRST
GND
(2)
(4)
Remark The P4 to P7 pins are multiplexed with PLL0 to PLL3 pins.
3
Data Sheet U14867EJ5V0DS
DSP FUNCTION LIST
µPD77110
35.5 K × 32
None
µPD77111
µPD77112
µPD77113A
3.5 K × 32
48 K × 32
µPD77114
µPD77115,77115A
11.5 K × 32
µPD77210
31.5 K × 32
µPD77213
15.5 K × 32
64K × 32
Item
1 K × 32
Int. instruction RAM
Int. instruction ROM
Memory
space
31.75 K × 32
3 K × 16 each
None
(words ×
bits)
24 K × 16 each
16 K × 16 each
32 K × 16 each
None
16 K × 16 each
30 K × 16 each
18 K × 16 each
Data RAM
(X/Y memory)
16 K × 16 each
32 K × 16 each
Data ROM
None
None
(X/Y memory)
Ext. instruction
32 K × 16 each
16 K × 16 each
8 K × 16 each
1 M × 16
1 M × 16 (8 K ×
Ext. data memory (X/Y
memory)
None
None
None
16, using SD I/F)
Instruction cycle (at maximum
operating speed)
15.3 ns
13.3 ns
6.25 ns
8.33 ns
(65 MHz)
(75 MHz)
(160 MHz)
(120 MHz)
Integer multiple
of ×1 to 16
Integer multiple
of ×1 to 8
Integer multiple of ×1 to 16
Integer multiple of ×10 to 64
Multiple
(mask option)
(external pin)
(external pin)
(external pin)
Serial interface
Host interface
2 channels
1 channel
2 channels (time-division, audio)
Peripheral
(speech CODEC)
(audio CODEC)
8-bit bus
4 bits
16-bit bus
General-purpose
port (I/O
8 bits
16 bits (some are alternative with
host)
programmable)
Timer
None
1 channel
2 channels
(16-bit resolution)
(16-bit resolution)
−
−
−
−
−
−
Others
SD card I/F
SD card I/F
DSP core: 1.5 V
Supply voltage
DSP core: 2.5 V
I/O pins: 3 V
I/O pins: 3 V
Package
100-pin TQFP
80-pin TQFP
80-pin FBGA
100-pin TQFP
80-pin FBGA
100-pin TQFP
80-pin TQFP
80-pin FBGA
161-pin FBGA
144-pin LQFP
µPD77115, 77115A
PIN CONFIGURATIONS
80-pin plastic fine pitch BGA (9 × 9)
µPD77115F1-CN6
µPD77115AF1-xxx-CN6
(Bottom View)
(Top View)
9
8
7
6
5
4
3
2
1
J
H
G
F
E
D
C
B
A
A
B
C
D
E
F
G
H
J
Index mark
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
Pin Name
EVDD
NC
Pin No.
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
E1
Pin Name
SDDAT
GND
Pin No.
Pin Name
GND
HWR
EVDD
CLKOUT
EVDD
P0
Pin No.
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
J1
Pin Name
HRE
EVDD
GND
EVDD
HD12
EVDD
GND
HD2
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
EVDD
IVDD
INT3
TRST
TICE
INT2
RESET
TDI
TDO
HA0
P3
I.C.
SOEN/LRCLK
P5/PLL1
SO
HD9
I.C.
HD4
IVDD
NC
HRD
HWE
CLKIN
HCS
HD0
SI
P7/PLL3
SDCLK
INT4
GND
NC
SDCR
GND
J2
GND
HD13
HD10
HD7
WAKEUP
INT1
IVDD
P1
J3
HA1
HD15
HD14
HD11
HD8
J4
TMS
GND
J5
TCK
P6/PLL2
P4/PLL0
GND
J6
HD6
I.C.
E2
J7
HD3
SIEN/MCLK
SCK/BCLK
E3
HD5
J8
GND
I.C.
E4
P2
HD1
J9
5
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
80-pin plastic TQFP (fine pitch) (12 × 12) (Top view)
µPD77115GK-9EU
SI
NC
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
TICE
I.C.
2
SIEN/MCLK
SCK/BCLK
SO
3
I.C.
4
TDO
HA1
5
SOEN/LRCLK
P7/PLL3
GND
6
HA0
7
GND
IVDD
8
P6/PLL2
P5/PLL1
P4/PLL0
EVDD
9
GND
EVDD
CLKIN
CLKOUT
HWR
HRD
HCS
HWE
HRE
EVDD
GND
HD0
10
11
12
13
14
15
16
17
18
19
20
P3
P2
P1
P0
HD15
GND
NC
HD14
6
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Pin No.
1
Pin Name
SI
Pin No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin Name
EVDD
GND
HD13
HD12
HD11
HD10
HD9
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Pin Name
HD0
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Name
TCK
2
NC
GND
EVDD
HRE
I.C.
3
SIEN/MCLK
SCK/BCLK
SO
TDI
4
TMS
5
HWE
HCS
TRST
RESET
INT4
6
SOEN/LRCLK
P7/PLL3
GND
7
HRD
HWR
CLKOUT
CLKIN
EVDD
GND
IVDD
8
HD8
INT3
9
P6/PLL2
P5/PLL1
P4/PLL0
EVDD
HD7
INT2
10
11
12
13
14
15
16
17
18
19
20
EVDD
GND
HD6
INT1
WAKEUP
IVDD
P3
HD5
GND
P2
HD4
GND
HA0
SDCLK
EVDD
GND
P1
HD3
P0
HD2
HA1
HD15
IVDD
TDO
SDCR
NC
GND
GND
I.C.
I.C.
NC
I.C.
SDDAT
EVDD
HD14
HD1
TICE
7
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
PIN NAME
CLKIN
CLKOUT
EVDD
: Clock Input
: Clock Output
: Power Supply for I/O Pins
: Ground
GND
HA0, HA1
HCS
: Host Data Access
: Host Chip Select
: Host Data Bus
: Host Read
HD0 to HD15
HRD
HRE
: Host Read Enable
: Host Write Enable
: Host Write
HWE
HWR
I.C.
: Internally Connected
: Interrupt
INT1 to INT4
IVDD
: Power Supply for DSP Core
: Non-Connection
: Port
NC
P0 to P3
P4/PLL0 to P7/PLL3 : Port/ PLL Setting Input
RESET
SCK/BCLK
SDCLK
SDCR
: Reset
: Serial Clock Input/ Output
: SD Card Clock Output
: SD Card Command Output/ Response Input
: SD Card Data Input/ Output
: Serial Data Input
SDDAT
SI
SIEN/MCLK
SO
: Serial Input Enable/ Master Clock Input
: Serial Data Output
SOEN/LRCLK : Serial Output Enable/ Left Right Clock Input/ Output
TCK
: Test Clock Input
TDI
: Test Data Input
TDO
: Test Data Output
: Test In-Circuit Emulator
: Test Mode Select
: Test Reset
TICE
TMS
TRST
WAKEUP
: Wakeup from STOP Mode
8
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
CONTENTS
1. PIN FUNCTION................................................................................................................................. 10
1.1 Pin Function Description ......................................................................................................... 10
1.2 Connection of Unused Pins..................................................................................................... 14
2. FUNCTION OUTLINE....................................................................................................................... 15
2.1 Program Control Unit ............................................................................................................... 15
2.2 Arithmetic Unit .......................................................................................................................... 16
2.3 Data Memory Unit ..................................................................................................................... 17
2.4 Peripheral Unit .......................................................................................................................... 17
3. RESET FUNCTION........................................................................................................................... 18
3.1 Hardware Reset......................................................................................................................... 18
3.2 Initializing PLL........................................................................................................................... 18
4. FUNCTIONS OF BOOT-UP ROM.................................................................................................. 18
4.1 Boot at Reset............................................................................................................................. 18
4.2 Reboot........................................................................................................................................ 19
4.3 Signature Operation ................................................................................................................. 19
5. STANDBY MODES........................................................................................................................... 20
5.1 HALT Mode................................................................................................................................ 20
5.2 STOP Mode................................................................................................................................ 20
6. MEMORY MAP ................................................................................................................................. 21
6.1 Instruction Memory................................................................................................................... 21
6.2 Data Memory ............................................................................................................................. 23
7. INSTRUCTIONS ................................................................................................................................ 25
7.1 Outline of Instructions.............................................................................................................. 25
7.2 Instruction Set and Operation ................................................................................................. 26
8. ELECTRICAL SPECIFICATIONS.................................................................................................... 32
9. PACKAGES....................................................................................................................................... 51
10. RECOMMENDED SOLDERING CONDITIONS................................................................................ 53
9
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
1. PIN FUNCTION
Because the pin numbers differ depending on the package, refer to the diagram of the package to be used.
1.1 Pin Function Description
• Power supply
Pin No.
Pin Name
I/O
Function
Shared by:
80-pin FBGA
A4,D7,H7
80-pin TQFP
37,53,72
−
−
−
−
IVDD
Power to DSP core (+2.5 V)
Power to I/O pins (+3 V)
EVDD
A1,A3,E8,F1,
G9,H2,H4
12,21,30,43,51,
75,80
−
−
GND
B4,C4,D9,E3,
E6,H1,H5,H9,
J2,J8
8,18,22,31,
38,42,52,54,
73,76
Ground
• System control
Pin No.
80-pin FBGA 80-pin TQFP
Pin Name
I/O
Function
Shared by:
−
−
CLKIN
F8
E9
50
Input
Output
Input
System clock input
CLKOUT
49
Internal system clock output
PLL multiple rate setting pin
PLL0 to PLL3 E2,D2,E1,D4
11,10,9,7
P4 to P7
PLL3 to PLL0:
0000 : x16, 0001 : x1, 0010 : x2, 0011 : x3,
0100 : x4, 0101 : x5, 0110 : x6, 0111 : x7,
1000 : x8, 1001 : x9, 1010 : x10, 1011 : x11,
1100 : x12, 1101 : x13, 1110 : x14,
1111 : x15
−
−
RESET
A6
B5
66
71
Input
Input
Internal system reset signal input
WAKEUP
Stop mode release signal input.
•
When this pin is asserted active, the stop
mode is released.
• Interrupt
Pin No.
Pin Name
I/O
Function
Shared by:
80-pin FBGA
80-pin TQFP
70,69,68,67
−
INT1 to INT4 B6,A5,C5,D6
Input
External maskable interrupt input.
Detected at the falling edge.
•
10
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
• Serial interface
Pin No.
80-pin FBGA 80-pin TQFP
Pin Name
I/O
I/O
Function
Shared by:
−
SCK/BCLK
C2
4
Serial clock input/output
SCK : Standard serial interface(input)
BCLK : Audio serial interface(I/O)
−
SOEN/LRCLK
D1
6
I/O
Serial output enable / Left Right clock
input/output
SOEN : Standard serial interface(input)
LRCLK : Audio serial interface(I/O)
−
−
SO
D3
C1
5
3
Output
(3S)
Serial data output
SIEN/MCLK
Input
Serial input enable / Master clock input
SIEN : Standard serial interface
MCLK : Audio serial interface (Master clock input
when master mode)
−
SI
B2
1
Input
Serial data input
Remark The pins marked “3S” under the heading “I/O” go into a high-impedance state on completion of data
transfer and input of the hardware reset (RESET) signal.
• SD card interface
Pin No.
Pin Name
I/O
Function
Shared by:
80-pin FBGA
D5
80-pin TQFP
74
−
−
SDCLK
Output
I/O
SD card clock output
SDCR
B3
77
79
SD card command/response
Input : Response
(3S)
Output : Command
•Leave pulled up.
−
SDDAT
C3
I/O
SD card data input/output
Input : Read data
(3S)
Output : Write data
•Leave pulled up.
Remark The pins marked “3S” under the heading “I/O” go into a high-impedance state when the SD card
interface is not being accessed.
11
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
• Host interface
Pin No.
80-pin FBGA 80-pin TQFP
Pin Name
I/O
Function
Shared by:
−
HA1
D8
56
Input
Specifies the register to be accessed by HD15 to
HD0.
•
1: Accesses the host interface status
register (HST).
•
0: Accesses the host transmit data register
(HDT (out)) when read (HRD = 0), and
host receive data register (HDT (in)) when
written (HWR = 0).
−
HA0
C9
55
Input
Specifies the register to be accessed by HD15 to
HD0.
•
1: Accesses bits 15 to 8 of HST, HDT (in),
and HDT (out).
•
0: Accesses bits 7 to 0 of HST, HDT (in),
and HDT (out).
When 8-bit mode, this signal becomes valid.
When 16-bit mode, this signal becomes invalid.
−
−
−
−
−
−
HCS
HRD
HWR
HRE
HWE
F9
F6
E7
G8
F7
46
47
48
44
45
Input
Input
Chip select input
Host read input
Input
Host write input
Output
Output
Host read enable output
Host write enable output
16-bit host data bus
HD0 to HD15 H8,G7,H6,J7,
F5,G6,J6,J5,
41,40,36,35,
34,33,32,29,
28,27,26,25,
24,23,20,17
I/O
(3S)
G5,F4,J4,G4,
H3,J3,G3,G2
Remark The pins marked “3S” under the heading “I/O” go into a high-impedance state when the host interface is
not being accessed.
• I/O ports
Pin No.
80-pin FBGA 80-pin TQFP
Pin Name
I/O
Function
Shared by:
General-purpose I/O port
−
−
P0
F2
G1
E4
F3
E2
D2
E1
D4
16
15
14
13
11
10
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P1
P2
P3
P4
P5
P6
P7
−
−
PLL0
PLL1
PLL2
PLL3
7
12
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
• Debugging interface
Pin No.
80-pin FBGA 80-pin TQFP
Pin Name
I/O
Function
Shared by:
−
−
−
−
−
−
TDO
TICE
TCK
TDI
C8
C7
B8
A7
B7
C6
57
60
61
63
64
65
Output
Output
Input
For debugging
Input
TMS
TRST
Input
Input
• Others
Pin No.
Pin Name
I/O
Function
Shared by:
80-pin FBGA
80-pin TQFP
−
−
I.C.
NC
A8,A9,B9,J9
39,58,59,62
Internally connected. Leave this pin
unconnected.
−
−
A2,B1,J1
2,19,78
No-connect pins. Leave these pins
unconnected.
Caution If any signal is input to these pins or if an attempt is made to read these pins, the normal
operation of the µPD77115 is not guaranteed.
13
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
1.2 Connection of Unused Pins
1.2.1 Connection of function pins
When mounting, connect unused pins as follows:
Pin
INT1 to INT4
SCK/BCLK
SI
I/O
Input
I/O
Recommended Connection
Connect to EVDD.
Connect to EVDD or GND.
Input
Input
I/O
SIEN/MCLK
SOEN/LRCLK
SO
Connect to GND.
Output
Output
I/O
Leave unconnected
SDCLK
SDCR
Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor.
SDDAT
I/O
HA0, HA1
HCS, HRD, HWR
HRE, HWE
HD0 to HD15Note
P0 to P3
Input
Input
Output
I/O
Connect to EVDD or GND.
Connect to EVDD.
Leave unconnected.
Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor.
I/O
TCK
Input
Output
Input
Input
Output
Input
Connect to GND via pull-down resistor.
Leave unconnected.
TDO, TICE
TMS, TDI
TRST
Leave unconnected. (internally pulled up).
Leave unconnected. (internally pulled down).
Leave unconnected.
CLKOUT
WAKEUP
Connect to EVDD.
Note These pins may be left unconnected if HCS, HRD, and HWR are fixed to the high level.
However, connect these pins as recommended in the halt and stop modes when the power consumption
must be lowered.
1.2.2 Connection of no-function pins
Pin
I/O
−
Recommended Connection
I.C.
NC
Leave unconnected.
Leave unconnected.
−
14
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
2. FUNCTION OUTLINE
2.1 Program Control Unit
This unit is used to execute instructions, and control branching, loops, interrupts, the clock, and the standby mode
of the DSP.
2.1.1 CPU control
A three-stage pipeline architecture is employed and almost all the instructions, except some instructions such as
branch instructions, are executed in one system clock.
2.1.2 Interrupt control
Interrupt requests input from external pins (INT1 to INT4) or generated by the internal peripherals (serial interface
and host interface) are serviced. The interrupt of each interrupt source can be enabled or disabled. Multiple interrupts
are also supported.
2.1.3 Loop control task
A loop function without any hardware overhead is provided. A loop stack with four levels is provided to support
multiple loops.
2.1.4 PC stack
A 15-level PC stack that stores the program counter supports multiple interrupts and subroutine calls.
2.1.5 PLL
A PLL is provided as a clock generator that can multiply an external clock input to supply an operating clock to the
DSP. A multiple of ×1 to ×16 can be set by pins(PLL0 to PLL3).
Two standby modes are available for lowering the power consumption while the DSP is not in use.
•
•
HALT mode : Set by execution of the HALT instruction. The current consumption drops to several mA. The
normal operation mode is recovered by an interrupt or hardware reset.
STOP mode: Set by execution of the STOP instruction. The current consumption drops to several 10 µA. The
normal operation mode is recovered by hardware reset or WAKEUP pin.
2.1.6 Instruction memory
64 words of the instruction RAM are allocated to interrupt vectors.
A boot-up ROM that boots up the instruction RAM is provided, and the instruction RAM can be initialized or
rewritten by host boot (boot via host interface).
The µPD77115 has 11.5K-word instruction RAM.
15
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
2.2 Arithmetic Unit
This unit performs multiplication, addition, logical operations, and shift, and consists of a 40-bit multiply accumulator,
40-bit data ALU, 40-bit barrel shifter, and eight 40-bit general-purpose registers.
2.2.1 General-purpose registers (R0 to R7)
These eight 40-bit registers are used to input/output data for arithmetic operations, and load or store data from/to
data memory.
A general-purpose register (R0 to R7) is made up of three parts: R0L to R7L (bits 15 to 0), R0H to R7H (bits 31 to
16), and R0E to R7E (bits 39 to 32). Depending on the type of operation, RnL, RnH, and RnE are used as one
register or in different combinations.
2.2.2 Multiply accumulator (MAC)
The MAC multiplies two 16-bit values, and adds or subtracts the multiplication result from one 40-bit value, and
outputs a 40-bit value.
The MAC is provided with a shifter (MSFT: MAC ShiFTer) at the stage preceding the input stage. This shifter can
arithmetically shift the 40-bit value to be added to or subtracted from the multiplication result 1 or 16 bits to the right .
2.2.3 Arithmetic logic unit (ALU)
This unit inputs one or two 40-bit values, executes an arithmetic or logical operation, and outputs a 40-bit value.
2.2.4 Barrel shifter (BSFT: Barrel ShiFTer)
The barrel shifter inputs a 40-bit value, shifts it to the left or right by any number of bits, and outputs a 40-bit value.
The data may be arithmetically shifted to the right shifted to the right, in which case the data is sign-extended, or
logically shifted to the right, in which case 0 is inserted from the MSB.
16
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
2.3 Data Memory Unit
The data memory unit consists of two banks of data memory and two data addressing units.
2.3.1 Data memory
The DSP have two banks of data memory (X data memory and Y data memory). A 64-word peripheral area is
assigned in the data memory space.
The µPD77115 has 16K words × 2 banks data RAM.
2.3.2 Data addressing unit
An independent data addressing unit is provided for each of the X data memory and Y data memory spaces.
Each data addressing unit has four data pointers (DPn), four index registers (DNn), one modulo register (DMX or
DMY), and an address ALU.
2.4 Peripheral Unit
A serial interface, host interface, general-purpose I/O port, and wait cycle register are provided. All these internal
peripherals are mapped to the X data memory and Y data memory spaces, and are accessed from program as
memory-mapped I/Os.
2.4.1 Audio Serial interface (ASIO)
One serial interface is provided. This serial interface has two mode which are the audio serial and the standard
serial. The standard serial is compatible other µPD77111 family DSP.
The audio serial interfaces have the following features:
•
Mode : Master mode or Slave mode
Master mode : MCLK (input), BCLK (output), LRCLK (output), support 256 fs, 384 fs and 512 fs
Slave mode : MCLK (unused), BCLK (input), LRCLK (input)
•
•
Frame format : 32 or 64 bits audio format (LRCLK format), MSB first input/output.
Handshake
:Handshaking with the external devices is implemented with a dedicated frame signal (LRCLK).
Handshaking with the internal units, polling, wait, or interrupt are used.
The standard serial interfaces have the following features:
•
Serial clock
: Supplied from external source to each interface. The same clock is used for input and output
on the interface.
•
•
Frame length : 8 or 16 bits, and MSB or LSB first selectable for each input or output
Handshake
: Handshaking with external devices is implemented with a dedicated status signal. With the
internal units, polling, wait, or interrupt are used.
2.4.2 Host interface (HIO)
This is an 16-bit parallel port that inputs data from or outputs data to an external host CPU or DMA controller. In
the DSP, a 16-bit register is mapped to memory for input data, output data, and status. Handshaking with an external
device is implemented by using a dedicated status signal or a dedicated status register. Handshaking with internal
units is achieved by means of polling, wait, or interrupts.
17
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
2.4.3 General-purpose I/O port (PIO)
This is a 8-bit I/O port that can be set in the input or output mode in 1-bit units.
2.4.4 SD card interface (SDCIF)
This interface is for access SD card. It supports the DMA transfer for input data to internal data RAM. The SD card
is accessed by using a dedicated routine of system ROM.
2.4.5 Timer
This is 16-bit timer unit. The count source can be selected from system clock, SD card clock, serial clock and INT4
input. Timer unit generates interrupt for interface internal units.
3. RESET FUNCTION
When a low level of a specified width is input to the RESET pin, the device is initialized.
3.1 Hardware Reset
If the RESET pin is asserted active (low level) for a specified period, the internal circuitry of the DSP is initialized. If
the RESET pin is then deasserted inactive (high level), boot processing of the instruction RAM is performed according
to the status of the port pins (P0 and P1). After boot processing, processing is executed starting from the instruction
at address 0x200 of instruction memory (reset entry).
No power-ON reset function is available.
3.2 Initializing PLL
Initializing the PLL starts during boot up program at reset. The pins (PLL0 to PLL3) that specify the PLL multiple
rate must be kept stable for the duration of 3 clocks before and for the duration of 50 clocks after reset has been
cleared (the clock is input from CLKIN). It takes the PLL 100 µs to be locked. Until the PLL is lacked, the DSP internal
is operated by the CLKIN clock.
To use the PLL clock as an internal operating clock, set the clock control register (internal peripheral) by user
program.
4. FUNCTIONS OF BOOT-UP ROM
To rewrite the contents of the instruction memory on power application or from program, boot up the instruction
RAM by using the internal boot-up ROM.
The µPD77115 has a function to verify the contents of the internal instruction RAM.
4.1 Boot at Reset
After hardware reset has been cleared, the boot program first reads the general-purpose I/O ports P0 and P1 and,
depending on their bit pattern, determines the boot mode (host boot or non boot). After boot processing, processing is
executed starting from the instruction at address 0x200 (reset entry) of the instruction memory.
The pins (P0 and P1) that specify the boot mode must be kept stable for the duration of 3 clocks before and for the
duration of 12 clocks after reset has been cleared (the clock is input from CLKIN).
18
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
P1
0
P0
0
Boot Mode
Does not execute boot but branches to address 0x200Note
.
0
1
Executes host byte boot and then branches to address 0x200.
Setting prohibited
1
0
1
1
Executes host word boot and then branches to address 0x200.
Note This setting is used when the DSP must be reset to recover from the standby mode after reset boot has
been executed once.
A boot parameter and instruction code are obtained via the host interface, and transferred to the instruction RAM.
The data transfer support byte mode and word mode.
4.2 Reboot
By calling the reboot entry address from the program, the contents of the instruction RAM can be rewritten. An
instruction code is obtained via the host interface and transferred to the instruction RAM. The data transfer support
byte mode and word mode.
The entry address is 0x6. Host reboot is executed by calling this address after setting the following parameter:
•
•
R7L : Number of instruction steps for rebooting
DP3: First address of instruction memory to be loaded
4.3 Signature Operation
The µPD77115 has a signature operation function so that the contents of the internal instruction RAM can be
verified. The signature operation performs a specific arithmetic operation on the data in the instruction RAM booted
up, and returns the result to a register. Perform the signature operation in advance on the device when it is operating
normally, and repeat the signature operation later to check whether the data in RAM is correct by comparing the
operation result with the previous result. If the results are identical, there is no problem.
The entry address is 0x9. Execute the operation by calling this address after setting the following parameter. The
operation result is stored in register R7.
•
•
R7L: Number of instruction steps for operation
DP3: First address of instruction memory for operation
19
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
5. STANDBY MODES
Two standby modes are available. By executing the corresponding instruction, each mode is set and the power
consumption can be reduced.
5.1 HALT Mode
To set this mode, execute the HALT instruction. In this mode, functions other than clock circuit and PLL are
stopped to reduce the current consumption.
To release the HALT mode, use an interrupt or hardware reset. When releasing the HALT mode using an interrupt,
the contents of the internal registers and memory are retained. It takes several 10 system clocks to release the HALT
mode when the HALT mode is released using an interrupt.
In the HALT Mode, the clock circuit of the µPD77115 supplies the following clock as the internal system clock. The
clock output from the CLKOUT pin is also as follows.
The clock output from the CLKOUT pin, however, has a high-level width that is equivalent to 1 cycle of the normal
operation (i.e., the duty factor is not 50%).
•
µPD77115: 1/l of internal system clock (l = integer from 1 to 16, specified by register)
5.2 STOP Mode
To set the STOP mode, execute the STOP instruction. In the STOP mode, all the functions, including the clock
circuit and PLL, can be stopped and the power consumption is minimized with only leakage current flowing.
To release the STOP mode, use hardware reset or WAKEUP pin.
When releasing the STOP mode by using the WAKEUP pin, the contents of the internal registers and memory are
retained, but it takes several 100 µs to release the mode.
20
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
6. MEMORY MAP
A Harvard architecture, in which the instruction memory space and data memory space are separated is employed.
6.1 Instruction Memory
6.1.1 Instruction memory map
0xFFFF
System
0xA000
0x9FFF
Instruction RAM
(8K words)
0x8000
0x7FFF
System
0x1000
0x0FFF
Instruction RAM
(3.5K words)
0x0240
0x023F
Vector area (64 words)
0x0200
0x01FF
Boot-up ROM
(512 words)
0x0000
Caution Programs and data cannot be placed at addresses reserved for the system, nor can these
addresses be accessed. If these addresses are accessed, the normal operation of the device
cannot be guaranteed.
21
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
6.1.2 Interrupt vector table
Addresses 0x200 to 0x23F of the instruction memory are entry points (vectors) of interrupts. Four instruction
addresses are assigned to each interrupt source.
Vector
Interrupt Source
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220
0x224
0x228
0x22C
0x230
0x234
0x238
0x23C
Reset
Reserved
INT1
INT2
INT3
INT4
SI input
SO output
SDDAT input / PBU
SDDAT output
HI input
HO output
SDCR input
Timer
Cautions 1. Although reset is not an interrupt, it is handled like an interrupt as an entry to a vector.
2. It is recommended that unused interrupt source vectors be used to branch an error
processing routine.
22
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
6.2 Data Memory
6.2.1 Data memory map
0xFFFF
System
0x6000
0x5FFF
Data RAM
(8K words)
0x4000
0x3FFF
System
0x3840
0x383F
0x3800
0x37FF
0x3000
0x2FFF
0x2000
0x1FFF
0x1000
0x0FFF
0x0000
Peripheral (64 words)
System
Data RAM (4K words)
System
Data RAM (4K words)
Caution Programs and data cannot be placed at addresses reserved for the system, nor can these
addresses be accessed. If these addresses are accessed, the normal operation of the device
cannot be guaranteed.
23
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
6.2.2 Internal peripherals
The internal peripherals are mapped to the internal data memory space.
X/Y Memory Address
0x3800
Register Name
SDT/ASDT
SST
Function
Peripheral Name
ASIO
Serial data register
Serial status register
0x3801
0x3802
ASST
Audio serial status register
Caution Do not access this area.
Port data register
−
0x3803
Reserved area
PDT
0x3804
PIO
0x3805
PCD
Port command register
0x3806
HDT
Host data register
HIO
0x3807
HST
Host status register
−
0x3808 to 0x380F
0x3810
Reserved area
SDDR
Caution Do not access this area.
SD card data register
SDCIF
0x3811
SDCMD_IDX
SDCMD_AGH
SDCMD_AGL
SDCTL
SD card command register index
SD card command register argument high
SD card command register argument low
SD card control register
0x3812
0x3813
0x3814
0x3815
SDRPR
SD card response register
SD card CRC status busy register
Caution Do not access this area.
Timer initialize value register
Timer count register
0x3816
SDSBR
−
0x3817 to 0x381F
0x3820
Reserved area
TIR
Timer
0x3821
TCR
0x3822
TCSR
Timer control / status register
Timer count enable register
Caution Do not access this area.
Clock control register
0x3823
TENR
−
PLL
−
0x3824 to 0x382D
0x382E
Reserved area
CLKCNTL
Reserved area
PSAR
0x382F
Caution Do not access this area.
DMA start address register
DMA size register
0x3830
SDCIF
0x3831
PSR
0x3832
PRR
DMA pointer register
0x3833
PCR
DMA control register
−
0x3834 to 0x383F
Reserved area
Caution Do not access this area.
Cautions 1. The register names listed in this table are not reserved words of the assembler or the C
language. Therefore, when using these names in assembler or C, the user must define them.
2. The same register is accessed, as long as the address is the same, regardless of whether
the X memory space or Y memory space is accessed.
3. Even different registers cannot be accessed at the same time from both the X and Y memory
spaces.
24
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
7. INSTRUCTIONS
7.1 Outline of Instructions
An instruction consists of 32 bits. Almost all the instructions, except some such as branch instructions, are
executed with one system clock. The maximum instruction cycle of the µPD77115 is 13.3 ns. The following nine
types of instructions are available:
(1) Trinomial operation instructions
These instructions specify an operation by the MAC. As the operands, three general-purpose registers can be
specified.
(2) Binomial operation instructions
These instructions specify an operation by the MAC, ALU, or BSFT. As the operands, two general-purpose
registers can be specified. An immediate value can be specified for some of these instructions, instead of a
general-purpose register, for one input.
(3) Uninominal operation instructions
These instructions specify an operation by the ALU. As the operands, one general-purpose register can be
specified.
(4) Load/store instructions
These instructions transfer 16-bit values between memory and a general-purpose register. Any general-purpose
register can be specified as the transfer source or destination.
(5) Register-to-register transfer instructions
These instructions transfer data from one general-purpose register to another.
(6) Immediate value setting instructions
These instructions write an immediate value to a general-purpose register and the registers of the address
operation unit.
(7) Branch instructions
These instruction specify branching of program execution.
(8) Hardware loop instructions
These instruction specify repetitive execution of an instruction.
(9) Control instructions
These instructions are used to control the program.
25
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
7.2 Instruction Set and Operation
An operation is written in the operation field for each instruction in accordance with the operation representation
format of that instruction. If two or more parameters can be written, select one of them.
(a) Representation formats and selectable registers
The following table shows the representation formats and selectable registers.
Representation Format
Selectable Register
r0, r0’, r0”
rI, rI’
R0 to R7
R0L to R7L
R0H to R7H
R0E to R7E
R0EH to R7EH
DP0 to DP7
DN0 to DN7
DMX, DMY
DP0 to DP3
DP4 to DP7
rh, rh’
re
reh
dp
dn
dm
dpx
dpy
DPn, DPn++, DPn− −, DPn##, DPn%%, !DPn## (n = 0 to 3)
DPn, DPn++, DPn− −, DPn##, DPn%%, !DPn## (n = 4 to 7)
DPn##imm (n = 0 to 7)
dpx_mod
dpy_mod
dp_imm
*xxx
Contents of memory with address xxx
<Example> If the contents of the DP0 register are 1000, *DP0 indicates the contents of
address 1000 of the memory.
26
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
(b) Modifying data pointer
The data pointer is modified after the memory has been accessed. The result of modification becomes valid
starting from the instruction that immediately follows. The data pointer cannot be modified.
Example
Operation
Nothing is done (value of DPn is not changed.)
DPn
DPn ← DPn + 1
DPn ← DPn − 1
DPn++
DPn− −
DPn##
DPn ← DPn + DNn
(Adds value of corresponding DN0 to DN7 to DP0 to DP7.)
Example: DP0 ← DP0 + DN0
DPn%%
(n = 0 to 3) DPn = ((DPL + DNn) mod (DMX + 1)) + DPH
(n = 4 to 7) DPn = ((DPL + DNn) mod (DMY + 1)) + DPH
!DPn##
Reverses bits of DPn and then accesses memory.
After memory access, DPn ← DPn + DNn
DPn ← DPn + imm
DPn##imm
(c) Instructions that can be simultaneously written
Instructions that can be simultaneously written are indicated by O.
(d) Status of overflow flag (OV)
The status of the overflow flag is indicated by the following symbol:
• : Not affected
: Set to 1 when overflow occurs
Caution If an overflow does not occur as a result of an operation, the overflow flag is not reset but
retains the status before the operation.
27
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Instruction Set
Instructions Simultaneously Written
Flag
OV
Instruc-
tion
Instruction
Name
Imme-
diate
Mnemonic
Operation
Trino- Bino- Unino- Load/ Trans-
Bran-
ch
Cont-
rol
Loop
mial
mial minal store fer
value
ro ← ro + rh * rh’
ro ← ro − rh * rh’
ro ← ro + rh * rl
√
√
√
Trinomial Multiply add
ro = ro + rh * rh’
operation
ro = ro − rh * rh’
Multiply sub
Sign unsign
multiply add
ro = ro + rh * rl
(rl is in positive integer
format.)
ro ← ro + rl * rl’
√
Unsign unsign
multiply add
ro = ro + rl * rl’
(rl and rl’ are in
positive integer
format.)
ro
ro ←
ro ←
+ rh * rh’
+ rh * rh’
√
√
1-bit shift multiply ro = (ro>>1) + rh * rh’
add
2
ro
•
•
216
16-bit shift multiply ro = (ro>>16) + rh * rh’
add
ro ← rh * rh’
ro” ← ro + ro’
√
√
Binomial
operation
Multiply
ro = rh * rh’
Add
ro” = ro + ro’
ro’ = ro + imm
ro’ ← ro + imm
(where imm ≠ 1)
Immediate add
ro” = ro − ro’
ro” ← ro − ro’
√
√
Sub
ro’ = ro − imm
ro’ ← ro − imm
(where imm ≠ 1)
Immediate sub
ro’ ← ro >> rl
•
•
Arithmetic right
shift
ro’ = ro SRA rl
ro’ ← ro >> imm
Immediate
arithmetic right
shift
ro’ = ro SRA imm
ro’ ← ro >> rl
√
√
•
•
Logical right shift
ro’ = ro SRL rl
ro’ ← ro >> imm
Immediate logical ro’ = ro SRL imm
right shift
ro’ ← ro << rl
•
•
Logical left shift
ro’ = ro SLL rl
ro’ ← ro << imm
Immediate logical ro’ = ro SLL imm
left shift
ro” ← ro & ro’
ro’ ← ro & imm
ro” ← ro ro’
ro’ ← ro imm
ro” ← ro ∧ ro’
√
√
√
•
•
•
•
•
AND
ro” = ro & ro’
ro’ = ro & imm
ro” = ro ro’
ro’ = ro imm
Immediate AND
OR
Immediate OR
Exclusive OR
ro” = ro ∧ ro’
ro’ = ro ∧ imm
ro’ ← ro ∧ imm
•
Immediate
exclusive OR
28
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Instructions Simultaneously Written
Flag
OV
•
Instruc-
tion
Instruction
Name
Imme-
diate
Mnemonic
Operation
Trino- Bino- Unino- Load/ Trans-
Bran-
ch
Cont-
rol
Loop
mial
mial minal store fer
value
√
Binomial
operation
Less than
ro” = LT (ro, ro’)
if (ro < ro
{ro” 0x0000000001}
else {ro” 0x0000000000}
’)
←
←
ro
←
0x0000000000
√
√
√
√
√
√
√
√
•
Clear
CLR (ro)
Uninom-
inal
ro’ ← ro + 1
ro’ ← ro − 1
Increment
Decrement
Absolute value
ro’ = ro + 1
ro’ = ro − 1
ro’ = ABS (ro)
operation
if (ro < 0)
{ro’ ← −ro}
else {ro’ ← ro}
~
~
ro’ ← ro
√
√
√
√
√
√
•
•
1’s complement
2’s complement
Clip
ro’ = ro
ro’ = −ro
ro’ ← −ro
ro’ = CLIP (ro)
if ( ro > 0x007FFFFFFF)
{ro’
elseif {ro < 0xFF80000000}
{ro’ 0xFF80000000}
else {ro’ ro}
← 0x007FFFFFFF}
←
←
√
√
•
Round
ro’ = ROUND (ro)
if (ro > 0x007FFF0000)
{ro 0x007FFF0000}
elseif {ro < 0xFF80000000}
{ro 0xFF80000000}
else {ro (ro + 0x8000)
’
←
’
←
’
←
& 0xFFFFFF0000}
1
ro’ ← log
ro’ ← ro
2
(
)
√
√
√
√
√
√
•
•
Exponent
ro’ = EXP (ro)
ro’ = ro
ro
Substitution
ro’ ← ro’ + ro
Accumulated
addition
ro’ + = ro
ro’ − = ro
ro’ ← ro’ − ro
√
√
√
√
Accumulated
subtraction
Division
ro’ / = ro
if (sign (ro’) == sign (ro))
{ro
else
{ro
’
←
(ro
’
− ro) << 1}
’
←
(ro’
+ ro)<<1}
if (sign (ro
’
)==0)
+ 1}
{ro’ ← ro’
29
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Instructions Simultaneously Written
Flag
OV
•
Instruc-
tion
Instruction
Name
Imme-
diate
Mnemonic
Operation
Trino- Bino- Unino- Load/ Trans-
Bran-
ch
Cont-
rol
Loop
mial
mial minal store fer
value
ro
ro
←
←
*dpx, ro
’
←
*dpy
√
√
√
Load/
store
Parallel
ro = *dpx_mod
load/storeNotes 1, 2 ro’ =*dpy_mod
*dpx, *dpy
←rh
ro = *dpx_mod
*dpy_mod = rh
*dpx
*dpx
←
←
rh, ro ← *dpy
*dpx_mod = rh
ro = *dpy_mod
rh, *dpy
← rh’
*dpx_mod = rh
*dpy_mod = rh’
dest ← *dpx,
dest′ ← *dpy
•
Partial load/
storeNotes 1, 2, 3
dest = *dpx_mod
dest′ = *dpy_mod
dest ← *dpx,
dest = *dpx_mod
*dpy ← source
*dpy_mod = source
*dpx ← source,
dest ← *dpy
*dpx_mod = source
dest = *dpy_mod
*dpx ← source,
*dpy ← source’
*dpx_mod = source
*dpy_mod = source’
dest ← *addr
•
•
•
•
Direct
dest = *addr
addressing
load/storeNote 4
*addr ← source
*addr = source
dest ← *dp
Immediate
dest = *dp_imm
value index
load/storeNote 5
*dp ← source
*dp_imm = source
dest ← rl
√
Register-
Register-to-
dest = rl
to-register register
rl ← source
rl = source
transfer
transferNote 6
rl ← imm
Immediate Immediate
rl = imm
value
value setting
(where imm = 0 to 0xFFFF)
setting
dp ← imm
dn ← imm
dm ← imm
dp = imm
(where imm = 0 to 0xFFFF)
dn = imm
(where imm = 0 to 0xFFFF)
dm = imm
(where imm = 1 to 0xFFFF)
Notes 1. Of the two mnemonics, either one of them or both can be written.
2. After transfer, modification specified by mod is performed.
3. Select any of dest, dest’ = {ro, reh, re, rh, rl}, source, source’ = {re, rh, rl}.
0: X-0xFFF : X (X memory)
4. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, addr =
.
0: Y-0xFFFF: Y (Y memory)
5. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}.
6. Select any register other than general-purpose registers as dest and source.
30
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Instructions Simultaneously Written
Flag
OV
Instruc-
tion
Instruction
Name
Imme-
diate
Mnemonic
Operation
Trino- Bino- Unino- Load/ Trans-
mial mial minal store fer
Bran-
ch
Cont-
rol
Loop
value
PC ← imm
√
√
•
•
Branch Jump
Register
JMP imm
PC ← dp
JMP dp
indirect jump
SP ← SP + 1
STK ← PC + 1
PC ← imm
√
√
•
•
Subroutine
call
CALL imm
SP ← SP + 1
STK ← PC + 1
PC ← dp
Register
CALL dp
indirect
subroutine call
PC ← STK
SP ← SP − 1
√
√
•
•
Return
RET
PC ← STK
Interrupt
return
RETI
STK ← SP − 1
Recovery of interrupt
enable flag
Start
RC
RF
PC
RC
PC
RF
←
←
←
←
←
←
count
0
•
•
•
Hard-
ware
loop
Repeat
REP count
During repeat
End
PC
RC
−
1
PC + 1
1
Start
RC
RF
PC
RC
PC
RF
←
←
←
←
←
←
count
0
Loop
LOOP count
(instruction of two or
more lines)
During repeat
End
PC
RC
−
1
PC + 1
1
LC ← LSR3
LE ← LSR2
LS ← LSR1
Loop pop
LPOP
LSP ← LSP − 1
PC ← PC + 1
CPU stops.
•
•
•
Control No operation
NOP
Halt
HALT
STOP
Stop
CPU, PLL, and
OSC stop
√
√
√
•
•
Condition
IF (ro cond)
FINT
Condition test
Forget
Discard interrupt
request
interrupt
31
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°C)
Parameter
Supply voltage
Symbol
IVDD
EVDD
VI
Condition
For DSP core
Rating
Unit
−0.5 to +3.6
−0.5 to +4.6
−0.5 to +4.1
−0.5 to +4.1
−65 to +150
−40 to +85
V
V
For I/O pins
Input voltage
VI < EVDD + 0.5 V
V
Output voltage
Storage temperature
VO
V
°C
°C
Tstg
Operating ambient
temperature
TA
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter
Symbol
IVDD
Condition
MIN.
2.0
2.7
0
TYP.
MAX.
2.7
Unit
V
Operating voltage
For DSP core
For I/O pins
EVDD
VI
3.6
V
Input voltage
EVDD
V
Capacitance (TA = +25°C, IVDD = 0 V, EVDD = 0 V)
Parameter
Input capacitance
Symbol
CI
Condition
f = 1 MHz,
MIN.
TYP.
10
MAX.
Unit
pF
Pins other than those
tested: 0 V
Output capacitance
I/O capacitance
CO
10
pF
CIO
10
pF
32
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
DC Characteristics (Unless otherwise specified, TA = − 40 to + 85°C, with IVDD and EVDD within recommended
operating condition range)
Parameter
Symbol
VIHN
Condition
MIN.
TYP.
MAX.
EVDD
EVDD
Unit
V
High-level input voltage
Pins other than below
0.7 EVDD
0.8 EVDD
VIHS
RESET, INT1 to INT4,
SCK, SIEN, SOEN
V
VIHC
CLKIN
0.5 EVDD
+0.25
EVDD
V
Low-level input voltage
VIL
Pins other than below
CLKIN
0
0
0.2 EVDD
V
V
VIC
0.5 EVDD
–0.25
IOH = −2.0 mA
IOH = −100 µA
IOL = 2.0 mA
High-level output voltage
Low-level output voltage
VOH
0.7 EVDD
0.8 EVDD
V
V
VOL
ILH
0.2 EVDD
10
V
µA
High-level input leakage
current
Other than TDI, TMS, and TRST
VI = EVDD
0
−10
µA
Low-level input leakage
current
ILL
Other than TDI, TMS, and TRST
VI = 0 V
0
TDI, TMS, 0 V ≤ VI ≤ EVDD
TRST, 0 V ≤ VI ≤ EVDD
−250
µA
µA
Pull-up pin current
IPUI
IPDI
0
Pull-down pin current
0
250
75
Note
Internal supply current
[VIHN = VIHS = EVDD, VIL = 0 V,
no load]
IDD
During operating, 30 ns, IVDD =
2.7 V
TBD
TBD
mA
IDDH
In halt mode, tcC = 30 ns, divided
by eight, IVDD = 2.7 V
10
mA
In stop mode, 0°C < TA < 60°C
µA
IDDS
100
Note The TYP. values are when an ordinary program is executed.
The MAX. values are when a special program that brings about frequent switching inside the device is
executed.
33
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Common Test Criteria of Switching Characteristics
0.8 EVDD
0.8 EVDD
0.5 EVDD
0.2 EVDD
RESET, INT1 to INT4,
SCK, SIEN, SOEN
0.5 EVDD
0.2 EVDD
Test points
Test points
Test points
+
+
0.5 EVDD 0.25
0.5 EVDD
0.5 EVDD 0.25
CLKIN
0.5 EVDD
−
−
0.5 EVDD 0.25
0.5 EVDD 0.25
0.7 EVDD
0.5 EVDD
0.2 EVDD
0.7 EVDD
0.5 EVDD
0.2 EVDD
Input
(other than above)
Output
0.5 EVDD
Test points
0.5 EVDD
34
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
AC Characteristics (TA = − 40 to + 85°C, with IVDD and EVDD within recommended operating condition range)
Clock
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
ns
CLKIN cycle timeNote 1
tcCX
25
15 × m
50 × m
50 × m
PLL lock
rangeNote 2
IVDD = 2.0
to 2.7 V
ns
10 × m
IVDD = 2.3
to 2.7 V
ns
CLKIN high-level width
CLKIN low-level width
CLKIN rise/fall time
twCXH
twCXL
trfCX
12.5
12.5
ns
ns
ns
ns
ns
5
Internal clock cycle time
requirementsNote 3
tcC (R)
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
20
13.3
Notes 1. m: Multiple
2. This is the range in which the PLL is locked (stably oscillates). Input tcCX within this range.
3. Input tcCX so that the value of (tcCX ÷ m × n) satisfies this condition. m: Multiple, n: Division ratio
Switching characteristics
Parameter
Symbol
Condition
External clock operation
PLL clock operation
In HALT mode
MIN.
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
Internal clock cycleNote
tcC
tcCX
(tcCX
÷ m) × n
(tcCX
÷
m)
tcC
× n × l
CLKOUT cycle time
CLKOUT width
tcCO
twCO
tcC ÷ 2 − 3
tcC ÷ n − 3
During
n = 1, or even number
normal
n = odd number
(other than 1)
operation
tcC ÷ n − 3
In HALT mode
ns
ns
ns
ns
CLKOUT rise/fall time
CLKOUT delay time
trfCO
tdCO
5
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
20
15
Note m: Multiple, n: Division ratio, l: HALT division ratio
35
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Clock I/O timing
t
cCX
t
rfCX
t
rfCX
t
wCXH
t
wCXL
CLKIN
t
cC, tcC(R)
Internal clock
t
cCO
t
dCO
t
rfCO
t
rfCO
t
wCO
t
wCO
CLKOUT
36
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Reset, Interrupt
Timing requirements
Parameter
Symbol
tw (RL)
Condition
MIN.
TYP.
MAX.
Unit
Note
RESET low-level width
WAKEUP low-level width
INT1 to INT4 low-level width
INT1 to INT4 recovery time
6 tcC
6 tcC
ns
µs
ns
ns
tw (WAKEUPL)
tw (INTL)
Note
3 tcC
trec (INT)
3 tcC
Note Note that tcC is I (I = integer of 1 to 16) times that during normal operation in the HALT mode.
Reset timing
t
w(RL)
RESET
WAKEUP timing
t
w (WAKEUPL)
WAKEUP
Interrupt timing
t
rec(INT)
t
w(INTL)
INT1 to INT4
37
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Serial Interface (Audio Serial mode)
Timing requirements
Parameter
MCLK cycle time
Symbol
tcMC
Condition
Master mode
MIN.
TYP.
MAX.
Note
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
0.4 × tcMC
MCLK high-/low-level width
MCLK rise/fall time
BCLK cycle time
twMC
Master mode
Master mode
Slave mode
Slave mode
Slave mode
Slave mode
trfMC
tcBC
300
120
BCLK high-/low-level width
BCLK rise/fall time
LRCLK setup time
SI setup time
twBC
trfBC
tsu(BC-LR)
tsuSI
50
50
50
SI hold time
thSI
Note 5 or maximum value of 0.1 × tcMC
Switching characteristics
Parameter
BCLK cycle time
Symbol
Condition
MIN.
TYP.
1/64 fs
1/32 fs
MAX.
Unit
ns
ns
ns
ns
ns
ns
tcBC
Master mode, 64-bit mode
Master mode, 32-bit mode
Master mode
BCLK high-/low-level width
BCLK rise/fall time
twBC
trfBC
0.4 tcBC
Master mode
20
−40
−40
+40
+40
LRCLK delay time
td(BC-LR)
tdSO
Master mode
SO output delay time
38
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Audio Serial clock timing
t
cMC
t
rfMC
t
rfMC
t
wMC
t
wMC
MCLK
Audio Serial Master mode timing
t
cBC
trfBC
t
rfBC
t
wBC
t
wBC
BCLK
(OUTPUT)
t
d(BC-LR)
t
d(BC-LR)
LRCLK
(OUTPUT)
t
dSO
SO
SI
t
suSI
thSI
Audio Serial Slave mode timing
t
cBC
t
rfBC
trfBC
t
wBC
t
wBC
BCLK
(INPUT)
t
su(BC-LR)
tsu(BC-LR)
LRCLK
(INPUT)
t
dSO
SO
SI
t
suSI
thSI
39
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Serial Interface (Standard Serial mode)
Timing requirements
Parameter
SCK cycle time
Symbol
tcSC
Condition
MIN.
60 and 2tcC
25
TYP.
MAX.
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK high-/low-level width
SCK rise/fall time
twSC
trfSC
SOEN setup time
tsuSOE
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
10
5
SOEN hold time
SIEN setup time
SIEN hold time
SI setup time
thSOE
tsuSIE
thSIE
tsuSI
thSI
15
10
10
5
15
10
10
5
SI hold time
15
10
Switching characteristics
Parameter
Symbol
Condition
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
MIN.
TYP.
MAX.
30
Unit
ns
SO output delay time
tdSO
25
ns
SO hold time
thSO
0
ns
40
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Serial output timing 1
tcSC
t
rfSC
t
rfSC
twSC
t
wSC
SCK
t
suSOE
t
suSOE
t
hSOE
t
hSOE
SOEN
SO
tdSO
t
dSO
t
hSO
Hi-Z
1st
Last
Serial output timing 2 (during successive output)
tcSC
trfSC
trfSC
twSC
twSC
SCK
tsuSOE
thSOE
SOEN
SO
tdSO
thSO
Last
1st
Last
41
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Serial input timing 1
tcSC
trfSC
trfSC
t
wSC
twSC
SCK
tsuSIE
tsuSIE
thSIE
t
hSIE
SIEN
SI
tsuSI
t
hSI
3rd
2nd
1st
Serial input timing 2 (during successive input)
t
cSC
t
rfSC
t
rfSC
t
wSC
t
wSC
SCK
t
suSIE
t
hSIE
SIEN
SI
tsuSI
t
hSI
Last–1
Last
1st
2nd
3rd
42
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in
mind the following points when designing your system:
•
Reinforce the wiring for power supply and ground (if noise is superimposed on the power and
ground lines, it has the same effect as if noise were superimposed on the serial clock).
Shorten the wiring between the device's SCK pin, and clock supply source.
•
•
Do not cross the signal lines of the serial clock with any other signal lines. Do not route the
serial clock line in the vicinity of a line through which a high alternating current flows.
Supply the clock to the SCK pin of the device from the clock source on a one-to-one basis. Do
not supply clock to several devices from one clock source.
•
•
Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure
that the rising and falling of the serial clock waveform are clear.
×
×
The serial clock must not bound. Noise
must not be superimposed on the serial clock.
Make sure that the serial clock
rises and falls linearly.
The serial clock must not rise or
fall step-wise.
43
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Host Interface
Timing requirements
Parameter
Symbol
Condition
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
MIN.
15
5
TYP.
MAX.
Unit
ns
HRD delay time
tdHR
ns
HRD width
twHR
40
0
ns
HCS, HA0, HA1, read hold
time
thHCAR
ns
HCS, HA0, HA1 write hold
time
thHCAW
0
ns
HRD, HWR recovery time
HWR delay time
trecHS
tdHW
3tcC
15
10
40
0
ns
ns
ns
ns
ns
ns
ns
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
HWR width
twHW
thHDW
tsuHDW
HWR hold time
HWR setup time
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
15
10
Switching characteristics
Parameter
Symbol
Condition
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
MIN.
TYP.
MAX.
30
Unit
ns
ns
ns
ns
ns
ns
ns
HRE, HWE output delay time
tdHE
25
HRE, HWE hold time
HRD valid time
thHE
tvHDR
thHDR
30
25
30
25
HRD hold time
0
44
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Host read interface timing
CLKIN
HCS, HA0, HA1
t
hHCAR
t
dHR
t
wHR
t
recHS
HRD
HD0 to HD15
HRE
t
hHDR
t
vHDR
Hi-Z
Hi-Z
t
dHE
thHE
Host write interface timing
CLKIN
HCS, HA0, HA1
thHCAW
tdHW
twHW
trecHS
HWR
thHDW
tsuHDW
HD0 to HD15
tdHE
thHE
HWE
45
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
General-purpose I/O Port
Timing requirements
Parameter
Port input setup time
Port input hold time
Symbol
tsuPI
Condition
MIN.
0
TYP.
MAX.
Unit
ns
thPI
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
15
10
ns
ns
Switching characteristics
Parameter
Symbol
Condition
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
MIN.
TYP.
MAX.
30
Unit
ns
Port output delay time
tdPO
25
ns
General-purpose I/O port timing
CLKIN
tdPO
P0 to P7
(Output)
tsuPI
t
hPI
P0 to P7
(Input)
46
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
SD card Interface
Timing requirements
Parameter
Symbol
tsuSDCR
thSDCR
tsuSDD
Condition
Input Response
MIN.
TYP.
MAX.
Unit
ns
SDCR input setup time
SDCR input hold time
SDDAT input setup time
SDDAT input hold time
5
0
5
0
Input Response
Input data
ns
ns
thSDD
Input data
ns
Switching characteristics
Parameter
Symbol
tcSDC
Condition
MIN.
40
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
SDCLK cycle time
SDCLK high- level width
SDCLK low-level width
SDCLK rise/fall time
twSDCH
twSDCL
trfSDC
10
10
10
10
SDCR output delay time
SDCR output valid time
SDDAT output delay time
SDDAT output valid time
tdSDCR
tvSDCR
tdSDD
Output Command
Output Command
Output data
0
0
10
tvSDD
Output data
47
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
SDCR timing
tcSDC
t
rfSDC
t
rfSDC
t
wSDCL
t
wSDCH
SDCLK
tdSDCR
tvSDCR
SDCR
(Output)
tsuSDCR
t
hSDCR
SDCR
(Input)
SDDAT timing
tcSDC
t
rfSDC
t
rfSDC
t
wSDCL
t
wSDCH
SDCLK
tdSDD
t
vSDD
SDDAT
(Output)
tsuSDD
thSDD
SDDAT
(Input)
48
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Debugging Interface (JTAG)
Timing requirements
Parameter
TCK cycle time
Symbol
tcTCK
Condition
MIN.
120
50
TYP.
MAX.
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK high-/low-level width
TCK rise/fall time
twTCK
trfTCK
TMS, TDI setup time
tsuDI
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
25
20
25
20
25
20
25
20
100
TMS, TDI hold time
Input pin setup time
Input pin hold time
thDI
tsuJIN
thJIN
TRST setup time
tsuTRST
Switching characteristics
Parameter
Symbol
Condition
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
IVDD = 2.0 to 2.7 V
IVDD = 2.3 to 2.7 V
MIN.
TYP.
MAX.
25
Unit
ns
TDO output delay time
tdDO
20
ns
Output pin output delay time
tdJOUT
25
ns
20
ns
49
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Debugging interface timing
tcTCK
t
rfTCK
t
rfTCK
twTCK
t
wTCK
TCK
tsuTRST
TRST
t
suDI
hDI
t
TMS, TDI
Valid
Valid
Valid
tdDO
TDO
t
suJIN
t
hJIN
Capture state
Valid
tdJOUT
Update state
Remark For details of JTAG, refer to IEEE1149.1.
50
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
9. PACKAGES
80-PIN PLASTIC FBGA (9x9)
A
D
w S
A
ZE
ZD
9
8
7
6
5
4
3
2
1
B
E
J H G F E D C B A
INDEX MARK
w
S B
A
A2
y1
S
(UNIT:mm)
ITEM DIMENSIONS
S
D
E
9.00 0.10
9.00 0.10
0.20
w
y
e
A1
A B
S
A
1.28 0.10
0.35 0.06
0.93
A1
A2
e
M
φ
φ
x
b
S
0.80
+0.05
0.50
b
–0.10
x
0.08
0.10
0.20
1.30
y
y1
ZD
ZE
1.30
P80F1-80-CN6
51
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A
B
60
41
61
40
detail of lead end
S
C
D
Q
R
80
21
1
20
F
G
J
M
I
H
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
G
H
I
14.0 0.2
12.0 0.2
12.0 0.2
14.0 0.2
1.25
1.25
0.22 0.05
0.10
J
0.5 (T.P.)
1.0 0.2
0.5 0.2
0.145 0.05
0.10
K
L
M
N
P
Q
1.0 0.05
0.1 0.05
+7°
3°
R
S
−3°
1.2 MAX.
S80GK-50-9EU-1
52
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
10. RECOMMENDED SOLDERING CONDITIONS
It is recommended to solder this product under the following conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Surface-Mount Type
• µ PD77115GK-9EU: 80-pin plastic TQFP (fine-pitch) (12 × 12)
Soldering Process
Infrared ray reflow
Soldering Conditions
Symbol
Package peak temperature: 235°C, Time: 30 seconds MAX (210°C MIN),
Number of times: 2 MAX, Number of days: 3Note (after that, prebaking is necessary
for 10 to 72 hours at 125°C))
IR35-103-2
VPS
Package peak temperature: 215°C, Time: 40 seconds MAX (200°C MIN),
Number of times: 2 MAX, Number of days: 3Note (after that, prebaking isnecessary
for 10 to 72 hours at 125°C)
VP15-103-2
−
Partial heating method
Pin temperature: 300°C MAX, Time: 3 seconds MAX (per side of device)
• µ PD77115F1-CN6: 80-pin plastic FBGA (9 × 9)
• µ PD77115AF1-xxx-CN6: 80-pin plastic FBGA (9 × 9)
Soldering Process
Soldering Conditions
Symbol
Infrared ray reflow
VPS
Package peak temperature: 235°C, Time: 30 seconds MAX (210°C MIN),
Number of times: 2 MAX, Number of days: 3Note (after that, prebaking is necessary
for 10 to 72 hours at 125°C))
IR35-103-2
Package peak temperature: 215°C, Time: 40 seconds MAX (200°C MIN),
Number of times: 2 MAX, Number of days: 3Note (after that, prebaking isnecessary
for 10 to 72 hours at 125°C)
VP15-103-2
Note Number of days in storage after the dry pack has been opened. The storage conditions are at 25°C, 65%
RH MAX.
Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with
the package.
53
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
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http://www.necel.com/en/support/support.html
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Santa Clara, California
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
800-366-9782
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Tel: 02-558-3737
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Tel: 02-66 75 41
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Tel: 02-2719-2377
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Tyskland Filial
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Tel: 08-63 80 820
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J04.1
54
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
55
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of August, 2004. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
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representative for availability and additional information.
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appear in this document.
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(Note)
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M8E 02. 11-1
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