UPD6379LGR-A [RENESAS]
IC,D/A CONVERTER,SINGLE,16-BIT,CMOS,SOP,8PIN;
| 型号： | UPD6379LGR-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,D/A CONVERTER,SINGLE,16-BIT,CMOS,SOP,8PIN |
| 文件： | 总18页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 1st, 2010
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD6379, 6379A, 6379L, 6379AL
2-CHANNEL 16-BIT D/A CONVERTER FOR AUDIO APPLICATION
The µPD6379 and 6379A are 2-channel 16-bit D/A converters for digital audio signal demodulation. These D/A
converters employ the resistor string conversion method which has been tested by existing model µPD6376 but they
are more compact and require fewer external components than the µPD6376. In addition, low-voltage models, the
µPD6379L and 6379AL (minimum operating supply voltage = +3.0 V) are also available for applications in portable
systems.
FEATURES
•
•
•
Resistor string conversion method
0-point digital shift circuit
× 4 oversampling
Sampling frequency: 200 kHz MAX.
Signal processing format for 2’s complement, MSB first, and backward justification data accommodated
Left and right in-phase output
•
•
•
High performance (at VDD = +5.0 V)
S/N ratio: 100 dB TYP.
Dynamic range: 96 dB TYP.
•
•
•
Low-voltage models available
Bipolar LR clock (LRCK)
Low power dissipation: 10 mW TYP.
(with µPD6379L, 6379AL at VDD = +3.3 V)
LRCK
LRCK = L
LRCK = H
Supply voltage
when L-ch data is input
when L-ch data is input
+3.3 V (VDD = +3.0 to 5.5 V)
+5.0 V (VDD = +4.5 to 5.5 V)
µPD6379L
µPD6379
µPD6379AL
µPD6379A
•
•
Few external components
Internal output operational amplifier
Only one electrolytic capacitor required for smoothing reference voltage, instead of two capacitors required by
existing D/A converters
Small package: 8-pin plastic SOP (5.72 mm (225))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S11588EJ5V0DS00 (5th edition)
Date Published June 2002 N CP(K)
Printed in Japan
The mark shows major revised points.
1996
©
µPD6379, 6379A, 6379L, 6379AL
ORDERING INFORMATION
Part number
Package
µPD6379GR
8-pin plastic SOP (5.72 mm (225))
8-pin plastic SOP (5.72 mm (225))
8-pin plastic SOP (5.72 mm (225))
8-pin plastic SOP (5.72 mm (225))
µPD6379LGR
µPD6379AGR
µPD6379ALGR
BLOCK DIAGRAM
REF
L. OUT
Main DAC
LRCK
Sub DAC
Sub DAC
Main DAC
CLK
SI
GND
R. OUT
VDD
Data Sheet S11588EJ5V0DS
2
µPD6379, 6379A, 6379L, 6379AL
PIN CONFIGURATIONS (Top View)
8-pin plastic SOP (5.72 mm (225))
•
µPD6379GR, 6379LGR
LRCK
SI
1
2
3
4
8
7
6
5
L. OUT
GND
CLK
REF
VDD
R. OUT
•
µPD6379AGR, 6379ALGR
R. OUT
REF
1
2
3
4
8
7
6
5
V
DD
CLK
SI
GND
L. OUT
LRCK
Remark The pin configuration of the µPD6379 and 6379L is different from that of the µPD6379A and 6379AL.
Data Sheet S11588EJ5V0DS
3
µPD6379, 6379A, 6379L, 6379AL
1. PIN FUNCTIONS
Table 1-1 Pin Functions
Pin No.
Name
Symbol
LRCK
I/O
Function
µPD6379,
µPD6379A,
6379L
6379AL
1
5
Left/Right Clock
Input
Input pin to identify left or right input data.
µPD6379, 6379L: Input “L” to this pin when
inputting L-ch data to SI pin.
µPD6379A, 6379AL: Input “H” to this pin
when
inputting L-ch data to SI pin.
2
6
Serial Input
SI
Input
Serial data input pin.
Input data on 2’s complement, MSB first, and
backward justification.
3
4
5
6
7
8
1
2
Clock
CLK
VDD
Input
Serial input data read clock (bit clock) input pin
Positive power supply pin
Supply Voltage
R-ch Output
Reference Voltage
–
Output
–
R. OUT
REF
Right analog signal output pin
Reference voltage pin. Connect this pin to GND
through capacitor.
7
8
3
4
Ground
GND
–
GND pin
L-ch Output
L. OUT
Output
Left analog signal output pin
Data Sheet S11588EJ5V0DS
4
µPD6379, 6379A, 6379L, 6379AL
2. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Parameter
Supply voltage
Symbol
VDD
VI
Ratings
Unit
V
– 0.3 to +7.0
Input voltage
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
220 (TA = 75 ˚C)
V
Output voltage
VO
V
Permissible package
power dissipation
PD
mW
Operating ambient temperature
Storage temperature
TA
–20 to +75
°C
°C
Tstg
–40 to +125
Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently. The
device should be operated within the limits specified under DC and AC Characteristics.
Data Sheet S11588EJ5V0DS
5
µPD6379, 6379A, 6379L, 6379AL
µPD6379, 6379A
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply voltage
Symbol
VDD
VIH
VIL
Condition
MIN.
4.5
TYP.
5.0
MAX.
5.5
Unit
V
Logic input voltage (HIGH)
Logic input voltage (LOW)
Operating ambient temperature
Output load resistance
Conversion frequency
Clock frequency
0.7 VDD
0
VDD
V
0.3 VDD
+75
V
TA
–20
5
+25
°C
kΩ
kHz
MHz
ns
RL
R. OUT, L. OUT pins
fS
200
10
fCLK
tSCK
tDC
Clock pulse width
40
12
12
SI, LRCK setup time
SI, LRCK hold time
ns
tCD
ns
ELECTRICAL CHARACTERISTICS (TA = 25 °C, VDD = +5 V, fS = 176.4 kHz)
Parameter
Resolution
Symbol
RES
Condition
MIN.
TYP.
16
MAX.
Unit
Bit
%
Total harmonic distortion
THD
fIN = 1 kHz, 0 dB
0.04
0.09
2.3
Full-scale output voltage
S/N ratio
VFS
S/N
D.R
C.T
IDD
1.7
93
89
82
2.0
100
96
96
5
Vp-p
dB
With A-weight filter
Dynamic range
Crosstalk
fIN = 1 kHz, –60 dB
dB
One side channel = 0 dB, fIN = 1 kHz
fIN = 1 kHz, 0 dB
dB
Current dissipation
12
mA
Data Sheet S11588EJ5V0DS
6
µPD6379, 6379A, 6379L, 6379AL
µPD6379L, 6379AL
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply voltage
Symbol
VDD
VIH
VIL
Condition
MIN.
3.0
TYP.
3.3
MAX.
5.5
Unit
V
Logic input voltage (HIGH)
Logic input voltage (LOW)
Operating ambient temperature
Output load resistance
Conversion frequency
Clock frequency
0.7 VDD
0
VDD
V
0.3 VDD
+75
V
TA
–20
10
+25
°C
kΩ
kHz
MHz
ns
RL
R. OUT, L. OUT pins
fS
200
10
fCLK
tSCK
tDC
Clock pulse width
40
12
12
SI, LRCK setup time
SI, LRCK hold time
ns
tCD
ns
ELECTRICAL CHARACTERISTICS (TA = 25 °C, VDD = +3.3 V, fS = 176.4 kHz)
Parameter
Resolution
Symbol
RES
Condition
MIN.
TYP.
16
MAX.
Unit
Bit
%
Total harmonic distortion
THD
fIN = 1 kHz, 0 dB
0.04
0.09
1.52
Full-scale output voltage
S/N ratio
VFS
S/N
D.R
C.T
IDD
1.12
93
1.32
98
93
93
3
Vp-p
dB
With A-weight filter
Dynamic range
Crosstalk
fIN = 1 kHz, –60 dB
89
dB
One side channel = 0 dB, fIN = 1 kHz
fIN = 1 kHz, 0 dB
82
dB
Current dissipation
6
mA
Data Sheet S11588EJ5V0DS
7
µPD6379, 6379A, 6379L, 6379AL
Timing Chart
CLK
LSB
LSB
10 11 12 13 14 15 16
MSB
1
MSB
1
SI
16
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
10 11
N
N
LRCK
PD6379A,
6379AL)
(L-ch)
(L-ch)
(R-ch)
(R-ch)
(
µ
LRCK
(µPD6379,
6379L)
N–1
N–1
L. OUT
R. OUT
t
SCK
tSCK
CLK
SI
CLK
t
DC
tCD
LRCK
t
DC
t
CD
Data Sheet S11588EJ5V0DS
8
µPD6379, 6379A, 6379L, 6379AL
3. APPLICATION CIRCUIT EXAMPLE
µ
µ
µ
µ
PD6379
VCC
PD6379A
PD6379L
PD6379AL
+
–
+
Signal processor
L-ch
output
LRCK L.OUT
LRCKO
SO
1
2
VCC
SI
GND
47 µF
+
BCKO
CLK REF
VCC
VDD
R.OUT
+
–
+
R-ch
output
+
47
µ
µ
F
F
1
2
VCC
VDD
0.1
Data Sheet S11588EJ5V0DS
9
µPD6379, 6379A, 6379L, 6379AL
4. NOTES ON USE
(1) Input signal format
•
Input data must be input as 2’s complement, MSB first, and backward justification.
2’s complement is a method of expressing both positive numbers and negative numbers as binary numbers.
See the table below.
2’s Complement
Decimal Number
L.OUT, R.OUT Pin Voltage TYP. (V)
Note 1
(Reference Values)
Note 2
(MSB)
(LSB)
1111
VDD = 5.0 V
3.0
VDD = 3.3 V
1.98
0111
1111
1111
1111
+32767
+32766
0111
1111
1110
0000
0000
1111
0000
0000
1111
0000
0000
1111
0001
0000
1111
+1
0
2.0
1.0
1.32
0.66
–1
1000
1000
0000
0000
0000
0000
0001
0000
–32767
–32768
Notes 1. Values differ depending on IC fabrication variations, supply voltage fluctuations, and ambient
temperature.
2. µPD6379L, 6379AL
•
•
•
Make sure that the delimiter of each bit of the data (SI) and the changing timing of LRCK coincide with the
falling edge of CLK.
It is necessary that 16 clocks be input during 1 sample data period (16 bits). Make sure that the time width
of 1 bit coincides with one cycle of the clock.
In the input data, the 16 bits preceding the change point of LRCK (shown in “1 sample data period” in Fig.
4-1, and Fig. 4-2) are considered to be valid data and are incorporated for use in D/A conversion.
Data Sheet S11588EJ5V0DS
10
µPD6379, 6379A, 6379L, 6379AL
•
If the clock is also supplied to CLK while data is not sampled (refer to Fig. 4-1), make sure that the changing
timing of LRCK coincides with the falling edge (point A) of CLK after the LSB has been input.
Fig. 4-1 Input Timing Chart (1)
A
A
1 sample data period
CLK
SI
LSB
16
MSB
1
LSB
10 11 12 13 14 15 16
MSB
1
Invalid
2
3
4
5
6
7
8
9
Invalid
2
3
4
LRCK
•
If the clock is supplied to CLK only while data is sampled (refer to Fig. 4-2), set the changing timing of LRCK
in between the falling edge (point A) of CLK after the LSB has been input and the start of inputting the next
MSB (point B) (points A and B are included).
Fig. 4-2 Input Timing Chart (2)
A
B
A
B
1 sample data period
CLK
SI
LSB
16 Invalid
MSB
LSB
10 11 12 13 14 15 16
MSB
1
2
3
4
5
6
7
8
9
Invalid
1
2
3
4
LRCK
Changing period of LRCK
Changing period of LRCK
Data Sheet S11588EJ5V0DS
11
µPD6379, 6379A, 6379L, 6379AL
(2) Output signal updating timing
The L.OUT and R.OUT signals are updated after the input of 3.5 clocks following the change point indicating
the end of the LRCK pin R-ch data input period. Therefore, when the clock is supplied to CLK only during
D/A conversion, the clock must be stopped after the L.OUT and R.OUT signals corresponding to the last input
data are output. Be aware that the L.OUT and R.OUT signals corresponding to the last sample data are not output,
especially when the clock is supplied to CLK only during a sample data period.
Fig. 4-3 Output Timing Chart (1) (for continuous clocks)
3.5 CLK
CLK
MSB
1
LSB
MSB
1
LSB
16
16 Invalid
Invalid
4
13 14 15
4
13 14 15
SI
2
3
2
3
1
2
3
L-ch data (N)
R-ch data (N)
LRCK
(
µ
PD6379, 6379L)
LRCK
(
µ
PD6379A, 6379AL)
L.OUT
Delay
L-ch output (N–1)
R-ch output (N–1)
L-ch output (N)
R-ch output (N)
R.OUT
Fig. 4-4 Output Timing Chart (2) (when there is an interval which the clock is stopped)
3.5 CLK
CLK stop
CLK stop
CLK
MSB
1
LSB
MSB
1
LSB
16 Invalid
16 Invalid
4
13 14 15
4
13 14 15
SI
2
3
2
3
1
2
3
4
5
L-ch data (N)
R-ch data (N)
LRCK
µ
( PD6379, 6379L)
LRCK
( PD6379A, 6379AL)
µ
Delay
L-ch output
(N)
L-ch output (N–1)
R-ch output (N–1)
L.OUT
R.OUT
R-ch output
(N)
(3) Countermeasures against shock noise
It is recommended that a mute circuit be connected to the next stage of the D/A converter. If a mute circuit is
not provided, shock noise may occur when power is applied.
Data Sheet S11588EJ5V0DS
12
µPD6379, 6379A, 6379L, 6379AL
5. PACKAGE DRAWING
8-PIN PLASTIC SOP (5.72 mm (225))
8
5
detail of lead end
P
1
4
A
H
F
I
J
G
S
B
L
N
S
C
K
M
D
M
E
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
+0.17
5.2
A
−0.20
B
C
0.78 MAX.
1.27 (T.P.)
+0.08
0.42
D
−0.07
E
F
G
H
I
0.1 0.1
1.59 0.21
1.49
6.5 0.3
4.4 0.15
1.1 0.2
J
+0.08
0.17
K
−0.07
L
M
N
0.6 0.2
0.12
0.10
+7°
3°
P
−3°
S8GM-50-225B-6
Data Sheet S11588EJ5V0DS
13
µPD6379, 6379A, 6379L, 6379AL
6. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met for soldering conditions of the product.
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”
(C10535E).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under
different conditions.
Table 6-1 Soldering Conditions
µPD6379GR, 6379AGR, 6379LGR, 6379ALGR : 8-pin plastic SOP (5.72 mm (225))
Soldering
Soldering Conditions
Symbol
Process
Infrared ray
reflow
Peak temperature of package surface: 235 °C or below,
Reflow time: 30 seconds or less (at 210 °C or higher),
Number of reflow processes: MAX. 2.
IR35-00-2
VPS
Peak temperature of package surface: 215 °C or below,
Reflow time: 40 seconds or less (at 200 °C or higher),
Number of reflow processes: MAX. 2.
VP15-00-2
WS60-00-1
Wave soldering
Solder temperature: 260 °C or below,
Flow time: 10 seconds or less,
Pre-heating temperature: 120 °C or below (Package surface),
Number of flow processes: MAX. 1.
Partial heating
method
Terminal temperature: 300 °C or below,
Time: 3 seconds or less (Per one side of the device).
—
Caution Do not apply more than one soldering method at any one time, except for “Partial heating
method”.
Data Sheet S11588EJ5V0DS
14
µPD6379, 6379A, 6379L, 6379AL
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S11588EJ5V0DS
15
µPD6379, 6379A, 6379L, 6379AL
•
The information in this document is current as of May, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
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Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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