UPD44325362BF5-E35-FQ1-A [RENESAS]
1MX36 QDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165;
| 型号： | UPD44325362BF5-E35-FQ1-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1MX36 QDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165 时钟 静态存储器 内存集成电路 |
| 文件： | 总36页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
μPD44325092B
μPD44325182B
μPD44325362B
R10DS0038EJ0200
Rev.2.00
36M-BIT QDRTM II SRAM
2-WORD BURST OPERATION
August 11, 2011
Description
The μPD44325092B is a 4,194,304-word by 9-bit, the μPD44325182B is a 2,097,152-word by 18-bit and the
μPD44325362B is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with
advanced CMOS technology using full CMOS six-transistor memory cell.
The μPD44325092B, μPD44325182B and μPD44325362B integrate unique synchronous peripheral circuitry
and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the
positive edge of K and K#. These products are suitable for application which require synchronous operation,
high speed, low voltage, high density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply
• 165-pin PLASTIC BGA (15 x 17)
• HSTL interface
• PLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR READ and WRITE operation
• Two-tick burst for low DDR transaction size
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two output clocks (C and C#) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
• User programmable impedance output (35 to 70 Ω)
• Fast clock cycle time : 3.3 ns (300 MHz), 3.5 ns (287 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 1 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Ordering Information (1/2)
Organization
(word x bit)
4M x 9
Operating Ambient
Temperature
Cycle
time
Clock
frequency
Part No.
Package
μPD44325092BF5-E33-FQ1-A
μPD44325092BF5-E35-FQ1-A
μPD44325092BF5-E40-FQ1-A
μPD44325092BF5-E50-FQ1-A
μPD44325182BF5-E33-FQ1-A
μPD44325182BF5-E35-FQ1-A
μPD44325182BF5-E40-FQ1-A
μPD44325182BF5-E50-FQ1-A
μPD44325362BF5-E33-FQ1-A
μPD44325362BF5-E35-FQ1-A
μPD44325362BF5-E40-FQ1-A
μPD44325362BF5-E50-FQ1-A
μPD44325092BF5-E33-FQ1
μPD44325092BF5-E35-FQ1
μPD44325092BF5-E40-FQ1
μPD44325092BF5-E50-FQ1
μPD44325182BF5-E33-FQ1
μPD44325182BF5-E35-FQ1
μPD44325182BF5-E40-FQ1
μPD44325182BF5-E50-FQ1
μPD44325362BF5-E33-FQ1
μPD44325362BF5-E35-FQ1
μPD44325362BF5-E40-FQ1
μPD44325362BF5-E50-FQ1
3.3ns
3.5ns
4.0ns
5.0ns
3.3ns
3.5ns
4.0ns
5.0ns
3.3ns
3.5ns
4.0ns
5.0ns
3.3ns
3.5ns
4.0ns
5.0ns
3.3ns
3.5ns
4.0ns
5.0ns
3.3ns
3.5ns
4.0ns
5.0ns
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
165-pin
PLASTIC BGA
(15 x 17)
Ta = 0 to 70°C
Lead-free
2M x 18
1M x 36
4M x 9
165-pin
PLASTIC BGA
(15 x 17)
Ta = 0 to 70°C
Lead
2M x 18
1M x 36
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 2 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Ordering Information (2/2)
Organization
(word x bit)
4M x 9
Operating Ambient
Temperature
Cycle
time
Clock
frequency
Part No.
Package
μPD44325092BF5-E33Y-FQ1-A
μPD44325092BF5-E35Y-FQ1-A
μPD44325092BF5-E40Y-FQ1-A
μPD44325092BF5-E50Y-FQ1-A
μPD44325182BF5-E33Y-FQ1-A
μPD44325182BF5-E35Y-FQ1-A
μPD44325182BF5-E40Y-FQ1-A
μPD44325182BF5-E50Y-FQ1-A
μPD44325362BF5-E33Y-FQ1-A
μPD44325362BF5-E35Y-FQ1-A
μPD44325362BF5-E40Y-FQ1-A
μPD44325362BF5-E50Y-FQ1-A
μPD44325092BF5-E33Y-FQ1
μPD44325092BF5-E35Y-FQ1
μPD44325092BF5-E40Y-FQ1
μPD44325092BF5-E50Y-FQ1
μPD44325182BF5-E33Y-FQ1
μPD44325182BF5-E35Y-FQ1
μPD44325182BF5-E40Y-FQ1
μPD44325182BF5-E50Y-FQ1
μPD44325362BF5-E33Y-FQ1
μPD44325362BF5-E35Y-FQ1
μPD44325362BF5-E40Y-FQ1
μPD44325362BF5-E50Y-FQ1
3.3ns
3.5ns
4.0ns
5.0ns
3.3ns
3.5ns
4.0ns
5.0ns
3.3ns
3.5ns
4.0ns
5.0ns
3.3ns
3.5ns
4.0ns
5.0ns
3.3ns
3.5ns
4.0ns
5.0ns
3.3ns
3.5ns
4.0ns
5.0ns
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
165-pin
PLASTIC BGA
(15 x 17)
Ta = −40 to 85°C
Lead-free
2M x 18
1M x 36
4M x 9
165-pin
PLASTIC BGA
(15 x 17)
Ta = −40 to 85°C
Lead
2M x 18
1M x 36
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 3 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Pin Arrangement
165-pin PLASTIC BGA (15 x 17)
(Top View)
[μPD44325092B]
4M x 9
1
CQ#
NC
2
3
A
4
5
6
7
NC/144M
BW0#
A
8
9
A
10
A
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
A
B
C
D
E
F
W#
NC
NC/288M
A
K#
K
R#
VSS/72M
NC
NC
NC
NC
Q5
NC
Q6
VDDQ
NC
NC
D7
NC
NC
Q8
A
A
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
NC
NC
D3
NC
NC
VSS
A
VSS
NC
D5
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
G
H
J
NC
D6
DLL#
NC
VREF
NC
K
L
NC
NC
NC
Q7
M
N
P
R
NC
NC
NC
D8
VSS
VSS
NC
NC
A
A
C
A
A
TDO
TCK
A
A
C#
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
D0 to D8
Q0 to Q8
R#
TDI
TCK
TDO
VREF
VDD
W#
: Write input
BW0#
K, K#
C, C#
CQ, CQ#
ZQ
: Byte Write data select
: Input clock
V
DDQ
: Power Supply
: Output clock
VSS
NC
: Ground
: Echo clock
: No connection
: Output impedance matching
: PLL disable
NC/xxM : Expansion address for xxMb
DLL#
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 7A and 5B are expansion addresses : 2A for 72Mb
: 2A and 7A for 144Mb
: 2A, 7A and 5B for 288Mb
2A of this product can also be used as NC.
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 4 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Pin Arrangement
165-pin PLASTIC BGA (15 x 17)
(Top View)
[μPD44325182B]
2M x 18
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ#
NC
A
W#
A
BW1#
NC
A
K#
K
R#
A
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
VSS/144M
Q9
NC/288M
BW0#
A
VSS/72M
NC
D9
NC
NC
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
VSS
A
VSS
Q7
NC
D11
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
D6
NC
Q12
D13
VREF
NC
NC
G
H
J
NC
NC
DLL#
NC
VREF
Q4
K
L
NC
NC
D3
NC
Q15
NC
NC
M
N
P
R
NC
Q1
NC
D17
NC
VSS
VSS
NC
NC
A
A
C
A
A
D0
TDO
TCK
A
A
C#
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
D0 to D17
Q0 to Q17
R#
TDI
TCK
TDO
VREF
VDD
W#
: Write input
BW0#, BW1#
K, K#
: Byte Write data select
: Input clock
VDD
VSS
NC
Q
: Power Supply
C, C#
: Output clock
: Ground
CQ, CQ#
ZQ
: Echo clock
: No connection
: Output impedance matching
: PLL disable
NC/xxM : Expansion address for xxMb
DLL#
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 7A and 10A are expansion addresses : 10A for 72Mb
: 10A and 2A for 144Mb
: 10A, 2A and 7A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 5 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Pin Arrangement
165-pin PLASTIC BGA (15 x 17)
(Top View)
[μPD44325362B]
1M x 36
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ#
Q27
D27
D28
Q29
Q30
D30
DLL#
D31
Q32
Q33
D33
D34
Q35
TDO
W#
A
BW2#
BW3#
A
K#
K
BW1#
BW0#
A
R#
A
A
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
VSS/288M NC/72M
VSS/144M
Q17
Q7
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
VSS
A
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
D15
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
Q14
D13
VREF
Q4
G
H
J
K
L
D3
Q11
Q1
M
N
P
R
VSS
VSS
D9
A
A
C
A
A
D0
A
A
C#
A
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
TMS
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
D0 to D35
Q0 to Q35
R#
TDI
TCK
TDO
VREF
VDD
W#
: Write input
BW0# to BW3# : Byte Write data select
K, K#
C, C#
CQ, CQ#
ZQ
: Input clock
VDD
VSS
NC
Q
: Power Supply
: Output clock
: Ground
: Echo clock
: No connection
: Output impedance matching
: PLL disable
NC/xxM : Expansion address for xxMb
DLL#
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 3A and 10A are expansion addresses : 3A for 72Mb
: 3A and 10A for 144Mb
: 3A, 10A and 2A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 6 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Pin Description
(1/2)
Symbol
Type
Input
Description
A
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of K for READ cycles and must meet the setup and hold times
around the rising edge of K# for WRITE cycles. All transactions operate on a burst of two
words (one clock period of bus activity). These inputs are ignored when device is
deselected, i.e., NOP (R# = W# = HIGH).
D0 to Dxx
Q0 to Qxx
Synchronous Data Inputs: Input data must meet setup and hold times around the rising
edges of K and K# during WRITE operations. See Pin Arrangement for ball site location of
individual signals.
x9 device uses D0 to D8.
x18 device uses D0 to D17.
Input
x36 device uses D0 to D35.
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K
and K# rising edges if C and C# are tied HIGH. Data is output in synchronization with C and
C# (or K and K#), depending on the R# command. See Pin Arrangement for ball site
location of individual signals.
Output
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
R#
Synchronous Read: When LOW this input causes the address inputs to be registered and a
READ cycle to be initiated. This input must meet setup and hold times around the rising
edge of K.
Synchronous Write: When LOW this input causes the address inputs to be registered and a
WRITE cycle to be initiated. This input must meet setup and hold times around the rising
edge of K.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold times
around the rising edges of K and K# for each of the two rising edges comprising the WRITE
cycle. See Pin Arrangement for signal to data relationships.
x9 device uses BW0#.
Input
Input
Input
W#
BWx#
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx# and Dxx.
Input Clock: A READ address and control input signal are input in synchronization with the
rising edge of K and a WRITE address is input in synchronization with the rising edge of K#.
Input data is input in synchronization with the rising edge of K and K#. K# is ideally 180
degrees out of phase with K. All synchronous inputs must meet setup and hold times around
the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data.
The rising edge of C# is used as the output timing reference for first output data. The rising
edge of C is used as the output reference for second output data. Ideally, C# is 180 degrees
out of phase with C. When use of K and K# as the reference instead of C and C#, then fixed
C and C# to HIGH. Operation cannot be guaranteed unless C and C# are fixed to HIGH
(i.e. toggle of C and C#).
K, K#
C, C#
Input
Input
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 7 of 36
μPD44325092B, μPD44325182B, μPD44325362B
(2/2)
Symbol
Type
Description
CQ, CQ#
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to
the synchronous data outputs and can be used as a data valid indication. These signals run
freely and do not stop when Q tristates. If C and C# are stopped (if K and K# are stopped in
the single clock mode), CQ and CQ# will also stop.
Output
ZQ
Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ, where
RQ is a resistor from this bump to ground. The output impedance can be minimized by
directly connect ZQ to VDDQ. This pin cannot be connected directly to GND or left
unconnected. The output impedance is adjusted every 20 μs upon power-up to account for
drifts in supply voltage and temperature. After replacement for a resistor, the new output
impedance is reset by implementing power-on sequence.
PLL Disable: When debugging the system or board, the operation can be performed at a
clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# =
LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must
be HIGH and it can be connected to VDDQ through a 10 kΩ or less resistor.
Input
Input
DLL#
TMS
TDI
Input
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG
function is not used in the circuit.
TCK
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function
is not used in the circuit.
Input
TDO
IEEE 1149.1 Test Output: 1.8 V I/O level.
Output
When providing any external voltage to TDO signal, it is recommended to pull up to VDD.
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the
input buffers.
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC
Characteristics for range.
VREF
VDD
−
Supply
Supply
VDDQ
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See
Recommended DC Operating Conditions and DC Characteristics for range.
VSS
NC
Supply
Power Supply: Ground
−
No Connect: These signals are not connected internally.
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 8 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Block Diagram
[μPD44325092B]
21
ADDRESS
R#
ADDRESS
REGISTRY
& LOGIC
21
W#
K
K#
W#
BW0#
221 x 18
DATA
18
18
9
2
18
9
Q0 to Q8
D0 to D8
R#
REGISTRY
& LOGIC
MEMORY
ARRAY
MUX
CQ,
CQ#
K
K
K
C, C#
K#
OR
K, K#
[μPD44325182B]
20
ADDRESS
R#
ADDRESS
REGISTRY
& LOGIC
20
W#
K
K#
W#
BW0#
BW1#
220 x 36
DATA
36
36
18
2
36
18
Q0 to Q17
D0 to D17
R#
REGISTRY
& LOGIC
MEMORY
ARRAY
MUX
CQ,
CQ#
K
K
K
C, C#
OR
K#
K, K#
[μPD44325362B]
19
ADDRESS
R#
ADDRESS
REGISTRY
& LOGIC
19
W#
K
K#
W#
BW0#
BW1#
BW2#
BW3#
219 x 72
DATA
72
72
36
72
Q0 to Q35
REGISTRY
& LOGIC
MEMORY
ARRAY
MUX
36
D0 to D35
2
CQ,
CQ#
R#
K
K
K
C, C#
K#
OR
K, K#
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 9 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Power-On Sequence in QDR II SRAM
QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
The following timing charts show the recommended power-on sequence.
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and
VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during power-up.
The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD
and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5 V during
power-down.
Power-On Sequence
Apply power and tie DLL# to HIGH.
- Apply VDD before VDDQ.
- Apply VDDQ before VREF or at the same time as VREF
.
Provide stable clock for more than 20 μs to lock the PLL.
PLL Constraints
The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as
TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is
enabled, then the PLL may lock onto an undesired clock frequency.
Power-On Waveforms
V
DD/VDDQ
V
DD/VDDQ Stable (< ±0.1 V DC per 50 ns)
Fix HIGH (or tied to VDDQ)
DLL#
Clock
20 μs or more
Stable Clock
Unstable Clock
Normal Operation
Start
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Page 10 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Truth Table
Operation
CLK
R#
W#
L
D or Q
Data in
WRITE cycle
L → H
×
Load address, input write data on
consecutive K and K# rising edge
READ cycle
Input data
Input clock
Data out
DA (A+0)
DA (A+1)
K( t ) ↑
K#( t ) ↑
L → H
L
×
Load address, output data on
consecutive C and C# rising edge
NOP (No operation)
Output data
Output clock
QA (A+0)
QA (A+1)
C#(t+1) ↑
C(t+2) ↑
L → H
H
H
D = ×, Q = High-Z
Previous state
Clock stop
Stopped
×
×
Remarks 1. H : HIGH, L : LOW, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges
except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
R10DS0038EJ0200 Rev.2.00
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Page 11 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Byte Write Operation
[μPD44325092B]
Operation
Write D0 to D8
K
L → H
−
L → H
−
K#
−
L → H
−
BW0#
0
0
1
1
Write nothing
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[μPD44325182B]
Operation
K
L → H
−
L → H
−
L → H
−
L → H
−
K#
−
L → H
−
L → H
−
L → H
−
BW0#
BW1#
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD44325362B]
Operation
K
L → H
−
L → H
−
L → H
−
L → H
−
L → H
−
L → H
−
K#
−
L → H
−
L → H
−
L → H
−
L → H
−
L → H
−
BW0#
BW1#
BW2#
BW3#
Write D0 to D35
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
L → H
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0038EJ0200 Rev.2.00
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Page 12 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Bus Cycle State Diagram
LOAD NEW
WRITE ADDRESS
AT K#
LOAD NEW
READ ADDRESS
R# = LOW
Always
Always
W# = LOW
WRITE DOUBLE
AT K#
READ DOUBLE
R# = LOW
W# = LOW
W# = HIGH
W# = HIGH
R# = HIGH
R# = HIGH
Supply voltage
provided
Supply voltage
provided
READ PORT NOP
R_Init = 0
WRITE PORT NOP
Power UP
Remarks 1. The address is concatenated with 1 additional internal LSB to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1.
Bus cycle is terminated at the end of this sequence (burst count = 2).
2. Read and write state machines can be active simultaneously.
3. State machine control timing sequence is controlled by K.
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μPD44325092B, μPD44325182B, μPD44325362B
Electrical Characteristics
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
Conditions
Rating
−0.5 to +2.5
Unit
V
VDD
Output supply voltage
Input voltage
VDD
Q
−0.5 to VDD
V
VIN
VI/O
TA
−0.5 to VDD+0.5 (2.5 V MAX.)
−0.5 to VDDQ+0.5 (2.5 V MAX.)
0 to 70
V
Input / Output voltage
Operating ambient temperature
V
(E** series)
°C
(E**Y series)
−40 to 85
Storage temperature
Tstg
−55 to +125
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter
Supply voltage
Symbol Conditions
MIN.
1.7
TYP.
MAX.
1.9
Unit Note
VDD
1.8
V
Output supply voltage
Input HIGH voltage
Input LOW voltage
Clock input voltage
Reference voltage
VDD
Q
1.4
VDD
V
V
V
V
V
1
VIH (DC)
VIL (DC)
VIN
VREF +0.1
−0.3
VDDQ+0.3
VREF −0.1
VDDQ+0.3
0.95
1, 2
1, 2
1, 2
−0.3
VREF
0.68
Notes 1. During normal operation, VDDQ must not exceed VDD
.
2. Power-up: VIH ≤ VDDQ +0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter
Input HIGH voltage
Input LOW voltage
Symbol Conditions
MIN.
MAX.
Unit Note
VIH (AC)
VIL (AC)
VREF +0.2
V
V
1
1
VREF −0.2
Note 1. Overshoot: VIH (AC) ≤ VDD +0.7 V (2.5 V MAX.) for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
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μPD44325092B, μPD44325182B, μPD44325362B
DC Characteristics 1 (TA = 0 to 70°C, VDD = 1.8 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
x18 x36
+2
Unit Note
x9
Input leakage current
I/O leakage current
ILI
−2
−2
μA
μA
ILO
IDD
+2
Operating supply current
(Read cycle / Write cycle)
VIN ≤ VIL or VIN ≥ VIH, -E33
mA
570 690 770
550 660 750
510 610 690
440 530 590
310 320 340
310 320 340
300 310 330
290 300 320
II/O = 0 mA,
-E35
-E40
-E50
Cycle = MAX.
Standby supply current
(NOP)
ISB1
VIN ≤ VIL or VIN ≥ VIH, -E33
mA
II/O = 0 mA,
Cycle = MAX.
Inputs static
-E35
-E40
-E50
Output HIGH voltage
Output LOW voltage
VOH(Low) |IOH| ≤ 0.1 mA
VOH Note1
VOL(Low) IOL ≤ 0.1 mA
VOL Note2
VDDQ−0.2
VDDQ/2−0.12
VSS
V
DDQ
V
DDQ/2+0.12
0.2
VDDQ/2−0.12
VDDQ/2+0.12
Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I standards.
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μPD44325092B, μPD44325182B, μPD44325362B
DC Characteristics 2 (TA = −40 to 85°C, VDD = 1.8 0.1 V)
Parameter
Symbol
Test condition
MIN.
MAX.
x18 x36
+2
Unit Note
x9
Input leakage current
I/O leakage current
ILI
−2
−2
μA
μA
ILO
IDD
+2
Operating supply current
(Read cycle / Write cycle)
VIN ≤ VIL or VIN ≥ VIH, -E33Y
mA
700 820 910
680 790 890
640 740 830
570 670 730
430 440 470
430 440 470
420 430 460
410 420 450
II/O = 0 mA,
-E35Y
-E40Y
-E50Y
Cycle = MAX.
Standby supply current
(NOP)
ISB1
VIN ≤ VIL or VIN ≥ VIH, -E33Y
mA
II/O = 0 mA,
Cycle = MAX.
Inputs static
-E35Y
-E40Y
-E50Y
Output HIGH voltage
Output LOW voltage
VOH(Low) |IOH| ≤ 0.1 mA
VOH Note1
VOL(Low) IOL ≤ 0.1 mA
VOL Note2
VDDQ−0.2
VDDQ/2−0.12
VSS
V
DDQ
V
DDQ/2+0.12
0.2
VDDQ/2−0.12
VDDQ/2+0.12
Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) 15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I standards.
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μPD44325092B, μPD44325182B, μPD44325362B
Capacitance (TA = 25°C, f = 1 MHz)
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
MIN.
MAX.
Unit
pF
Input capacitance (Address, Control)
Input / Output capacitance
(D, Q, CQ, CQ#)
5
7
CI/O
VI/O = 0 V
pF
Clock Input capacitance
Cclk
Vclk = 0 V
6
pF
Remark These parameters are periodically sampled and not 100% tested.
Thermal Characteristics
Parameter
Thermal resistance
Symbol
Substrate
4-layer
Airflow
0 m/s
1 m/s
0 m/s
1 m/s
0 m/s
1 m/s
0 m/s
1 m/s
TYP.
Unit
θ ja
21.2
13.4
20.2
13.0
0.02
0.06
0.02
0.05
2.58
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
from junction to ambient air
8-layer
4-layer
8-layer
Thermal characterization parameter
from junction to the top center
of the package surface
Ψ jt
θ jc
Thermal resistance
from junction to case
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 17 of 36
μPD44325092B, μPD44325182B, μPD44325362B
AC Characteristics (TA = 0 to 70°C or TA = −40 to 85°C, VDD = 1.8 0.1 V)
AC Test Conditions (VDD = 1.8 0.1 V, VDDQ = 1.4 V to VDD
)
Input waveform (Rise / Fall time ≤ 0.3 ns)
1.25 V
0.75 V
0.75 V
Test Points
0.25 V
Output waveform
V
DDQ / 2
Test Points
VDDQ / 2
Output load condition
Figure 1. External load at test
V
DDQ / 2
0.75 V
50 Ω
V
REF
ZO = 50 Ω
SRAM
250 Ω
ZQ
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August 11, 2011
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μPD44325092B, μPD44325182B, μPD44325362B
Read and Write Cycle
-E33, E33Y
(300 MHz)
Parameter
Symbol
TKHKH
-E35, E35Y -E40, E40Y -E50, E50Y Unit Note
(287 MHz) (250 MHz) (200 MHz)
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock
3.3
8.4
0.2
3.5
8.4
0.2
4.0
8.4
0.2
5.0
8.4
0.2
ns
1
2
Average Clock cycle time
(K, K#, C, C#)
Clock phase jitter (K, K#, C, C#)
Clock HIGH time (K, K#, C, C#)
Clock LOW time (K, K#, C, C#)
Clock HIGH to Clock# HIGH
(K → K#, C → C#)
TKC var
TKHKL
ns
ns
ns
ns
1.32
1.32
1.49
1.5
1.5
1.7
1.6
1.6
1.8
2.0
2.0
2.2
TKLKH
TKHK#H
TK#HKH
TKHCH
1.49
0
1.7
0
1.8
0
2.2
0
ns
ns
Clock# HIGH to Clock HIGH
(K# → K, C# → C)
Clock to data clock
1.45
1.65
1.8
2.3
(K → C, K# → C#)
PLL lock time (K, C)
TKC lock
20
30
20
30
20
30
20
30
μs
ns
3
4
K static to PLL reset
TKC reset
Output Times
CQ HIGH to CQ# HIGH
(CQ → CQ#)
CQ# HIGH to CQ HIGH
(CQ# → CQ)
C, C# HIGH to output valid
C, C# HIGH to output hold
C, C# HIGH to echo clock valid
C, C# HIGH to echo clock hold
CQ, CQ# HIGH to output valid
CQ, CQ# HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
TCQHCQ#H 1.24
TCQ#HCQH 1.24
TCHQV
1.35
1.35
1.55
1.55
1.95
1.95
ns
ns
5
5
0.45
0.45
0.27
0.45
0.45
0.45
0.3
0.45
0.45
0.3
0.45
0.45
0.35
0.45
ns
ns
ns
ns
ns
ns
ns
ns
TCHQX
−0.45
−0.45
−0.45
−0.3
−0.45
−0.45
−0.3
−0.45
−0.45
−0.35
−0.45
TCHCQV
TCHCQX −0.45
TCQHQV
6
6
TCQHQX −0.27
TCHQZ
0.45
0.45
TCHQX1 −0.45
−0.45
−0.45
Setup Times
Address valid to K rising edge
TAVKH
TIVKH
0.3
0.3
0.35
0.35
0.35
0.35
0.4
0.4
ns
ns
7
7
Control inputs (R#, W#) valid to
K rising edge
Data inputs and write data
select
TDVKH
0.3
0.35
0.35
0.4
ns
7
inputs (BWx#) valid to
K, K# rising edge
Hold Times
K rising edge to address hold
K rising edge to control inputs
(R#, W#) hold
TKHAX
TKHIX
0.3
0.3
0.35
0.35
0.35
0.35
0.4
0.4
ns
ns
7
7
K, K# rising edge to data
inputs and write data select
inputs (BWx#) hold
TKHDX
0.3
0.35
0.35
0.4
ns
7
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 19 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock
cycle in this operation. The AC/DC characteristics cannot be guaranteed, however.
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
3. VDD slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention.
PLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept NOP (R# = W# = HIGH) during these cycles.
4. K input is monitored for this operation. See below for the timing.
K
TKC reset
or
K
TKC reset
5. Guaranteed by design.
6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
7. This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. VDDQ is 1.5 V DC.
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 20 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Read and Write Timing
READ
WRITE READ
WRITE READ
WRITE NOP
WRITE NOP
1
2
3
4
5
6
7
8
9
10
K
TKHKL TKLKH
TKHKH
TKHK#H TK#HKH
K#
R#
TKHIX
TIVKH
W#
A0
A1
A2
A3
A4
A5
A6
Address
TKHAX
TAVKH
TKHAX
D11
TAVKH
D30
D10
D31
D50
D51
D60
D61
Data in
TDVKH TKHDX
TDVKH TKHDX
Q01 Q20
Data out
Q00
Q21
Q40
Q41
TCHQX TCHQX
TCQHQX
TCHQX1
TCHQZ
TCHQV TCHQV
TCQHQV
CQ
TCHCQX
TCHCQV
TCQHCQ#H TCQ#HCQH
CQ#
TCHCQX
TKHCH
TCHCQV
C
TKHKL TKLKH
TKHKH
TKHK#H
TK#HKH
TKHCH
C#
Remarks 1. Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2. Outputs are disabled (high impedance) 2.5 clock cycles after the last READ (R# = LOW) is input in the
sequences of [READ/WRITE]-[NOP/WRITE], [READ/WRITE]-[NOP/NOP], [READ/NOP]-
[NOP/WRITE] and [READ/NOP] -[NOP/NOP].
3. In this example, if address A0 = A1, data Q00 = D10, Q01 = D11.
Write data is forwarded immediately as read results.
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 21 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Application Example
R =
250 Ω
R =
250 Ω
ZQ
ZQ
CQ#
CQ
Q
CQ#
SRAM#1
SRAM#4
. . .
CQ
D
A
D
A
Q
R# W# BWx# C/C# K/K#
R# W# BWx# C/C# K/K#
V
t
SRAM
Controller
R
Data In
Vt
Data Out
Address
R#
R
Vt
R
W#
BW#
SRAM#1 CQ/CQ#
Vt
R
R
SRAM#4 CQ/CQ#
Vt
Source CLK/CLK#
Return CLK/CLK#
Vt
R
R = 50 Ω
Vt = Vref
Remark AC Characteristics are defined at the condition of SRAM outputs, CQ, CQ# and DQ with termination.
R10DS0038EJ0200 Rev.2.00
August 11, 2011
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μPD44325092B, μPD44325182B, μPD44325362B
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
TCK
Pin assignments
Description
2R
Test Clock Input. All input are captured on the rising edge of TCK and all
outputs propagate from the falling edge of TCK.
TMS
TDI
10R
11R
Test Mode Select. This is the command input for the TAP controller state
machine.
Test Data Input. This is the input side of the serial registers placed between
TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP controller state machine and the instruction that is currently
loaded in the TAP instruction.
TDO
1R
Test Data Output. This is the output side of the serial registers placed between
TDI and TDO. Output changes in response to the falling edge of TCK.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 0.1 V, unless otherwise noted)
Parameter
Symbol
Conditions
MIN.
−5.0
−5.0
MAX.
+5.0
+5.0
Unit
μA
JTAG Input leakage current
JTAG I/O leakage current
ILI
0 V ≤ VIN ≤ VDD
0 V ≤ VIN ≤ VDDQ,
Outputs disabled
ILO
μA
JTAG input HIGH voltage
JTAG input LOW voltage
JTAG output HIGH voltage
VIH
VIL
1.3
−0.3
1.6
VDD+0.3
+0.5
V
V
V
V
V
V
VOH1
VOH2
VOL1
VOL2
| IOHC | = 100 μA
| IOHT | = 2 mA
IOLC = 100 μA
IOLT = 2 mA
1.4
JTAG output LOW voltage
0.2
0.4
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August 11, 2011
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μPD44325092B, μPD44325182B, μPD44325362B
JTAG AC Test Conditions
Input waveform (Rise / Fall time ≤ 1 ns)
1.8 V
0.9 V
0.9 V
Test Points
0 V
Output waveform
0.9 V
Test Points
0.9 V
Output load
Figure 2. External load at test
V
TT = 0.9 V
50 Ω
ZO = 50 Ω
TDO
20 pF
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 24 of 36
μPD44325092B, μPD44325182B, μPD44325362B
JTAG AC Characteristics (TA = 0 to 70°C)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
tTHTH
fTF
tTHTL
tTLTH
50
ns
MHz
ns
20
20
20
ns
Output time
TCK LOW to TDO unknown
TCK LOW to TDO valid
tTLOX
tTLOV
0
ns
ns
10
Setup time
TMS setup time
TDI valid to TCK HIGH
Capture setup time
tMVTH
tDVTH
tCS
5
5
5
ns
ns
ns
Hold time
TMS hold time
tTHMX
tTHDX
tCH
5
5
5
ns
ns
ns
TCK HIGH to TDI invalid
Capture hold time
JTAG Timing Diagram
t
THTH
TCK
t
MVTH
t
THTL
t
TLTH
TMS
TDI
t
THMX
t
DVTH
t
THDX
t
TLOV
t
TLOX
TDO
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 25 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller
when it is moved into the run-test/idle or the various data register state. The register can
be loaded when it is placed between the TDI and TDO pins. The instruction register is
automatically preloaded with the IDCODE instruction at power-up whenever the controller
is placed in test-logic-reset state.
Bypass register
ID register
The bypass register is a single bit register that can be placed between TDI and TDO. It
allows serial test data to be passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit
code when the controller is put in capture-DR state with the IDCODE command loaded in
the instruction register. The register is then placed between the TDI and TDO pins when
the controller is moved into shift-DR state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents
of the RAMs I/O ring when the controller is in capture-DR state and then is placed
between the TDI and TDO pins when the controller is moved to shift-DR state. Several
TAP instructions can be used to activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary
register location. The first column defines the bit’s position in the boundary register. The
second column is the name of the input or I/O at the bump and the third column is the
bump number.
Scan Register Definition (2)
Register name
Instruction register
Bypass register
ID register
Bit size
Unit
bit
3
1
bit
32
109
bit
Boundary register
bit
ID Register Definition
ID [31:28] vendor
revision no.
ID [11:1] vendor
ID no.
Part number
Organization
4M x 9
ID [27:12] part no.
ID [0] fix bit
μPD44325092B
μPD44325182B
μPD44325362B
XXXX
XXXX
XXXX
1
1
1
0000 0000 0100 1010
0000 0000 0100 1011
0000 0000 0100 1100
00000010000
00000010000
00000010000
2M x 18
1M x 36
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 26 of 36
μPD44325092B, μPD44325182B, μPD44325362B
SCAN Exit Order
Bit
Signal name
Bump
ID
Bit
Signal name
x18 x36
Bump
ID
Bit
Signal name
x18 x36
Bump
ID
no.
x9
x18
x36
no.
x9
no.
x9
NC
Q5 Q11 Q20 3E
1
C#
C
6R
6P
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NC
NC
NC
NC
NC
NC
Q4
D4
NC D15 10D
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
NC Q28 2C
2
NC Q15
9E
10C
11D
9C
3
A
6N
Q7
D7
Q7
D7
D5
NC
NC
D11 D20
NC D29
2D
2E
4
A
7P
5
A
7N
NC D16
NC Q16
NC Q29 1E
6
A
7R
9D
NC Q12 Q21
NC D12 D21
2F
3F
7
A
8R
Q8
D8
Q8
D8
11B
11C
9B
8
A
8P
NC
NC
NC D30 1G
NC Q30 1F
9
A
9R
NC
NC
NC D17
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Q0
D0
NC
NC
Q1
D1
NC
NC
Q2
D2
NC
NC
Q3
D3
NC
NC
Q4
D4
ZQ
NC
NC
Q5
D5
NC
NC
Q6
D6
11P
10P
10N
9P
NC Q17 10B
CQ 11A
VSS VSS 10A
Q6 Q13 Q22 3G
D6
D13 D22 2G
NC
NC
NC
NC
NC
NC
Q1
D1
D9
Q9
A
DLL#
1H
1J
2J
A
A
9A
8B
7C
6C
8A
NC
NC
NC D31
NC Q31
Q1
10M
11N
9M
9N
D1
A
NC Q14 Q23 3K
D10
Q10
Q2
A
NC D14 D23
3J
R#
NC
NC
NC D32
2K
11L
11M
9L
NC
NC
NC BW1# 7A
NC Q32 1K
D2
BW0#
K
7B
6B
6A
Q7 Q15 Q24
2L
3L
NC
NC
NC
NC
NC
NC
Q2
D2
D11
D7
NC
NC
D15 D24
Q11 10L
K#
NC D33 1M
NC Q33 1L
Q3
D3
11K
10K
9J
NC BW3# 5B
NC BW1# BW2# 5A
NC Q16 Q25 3N
NC D16 D25 3M
D12
Q12
Q4
W#
A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
9K
NC
NC
NC D34
1N
10J
11J
11H
A
NC Q34 2M
D4
A
A
NC
Q8 Q17 Q26 3P
VSS
CQ#
Q9
D9
D8
D17 D26
NC D35
2N
2P
NC
NC
NC
NC
NC
NC
Q3
D3
D13 10G
101 NC
102 NC
103
Q13
Q5
9G
11F
11G
9F
NC
NC
NC
NC
Q18
D18
NC Q35 1P
A
A
A
A
A
A
−
3R
4R
D5
NC D27
NC Q27
104
D14
105
4P
Q14 10F
NC Q10 Q19
NC D10 D19
106
5P
Q6
D6
11E
10E
107
5N
NC
NC D28
108
5R
109
Internal
Remarks
Bump ID 10A of bit no. 48 can also be used as NC if the product is x18 or x36.
Bump ID 2A of bit no. 64 can also be used as NC.
The register always indicates LOW, however.
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 27 of 36
μPD44325092B, μPD44325182B, μPD44325362B
JTAG Instructions
Instructions
Description
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested.
Boundary-scan register cells at output pins are used to apply test vectors, while those at
input pins capture test results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register using the PRELOAD
instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and
the PRELOAD data is driven onto the output pins.
IDCODE
BYPASS
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the
controller is in capture-DR mode and places the ID register between the TDI and TDO pins
in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up
and any time the controller is placed in the test-logic-reset state.
When the BYPASS instruction is loaded in the instruction register, the bypass register is
placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-
DR state. This allows the board level scan path to be shortened to facilitate testing of other
devices in the scan path.
SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the
SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP
controller into the capture-DR state loads the data in the RAMs input and DQ pins into the
boundary scan register. Because the RAM clock(s) are independent from the TAP clock
(TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample
metastable input will not harm the device, repeatable results cannot be expected. RAM
input signals must be stabilized for long enough to meet the TAPs input data capture setup
plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other
TAP operation except capturing the I/O ring contents into the boundary scan register.
Moving the controller to shift-DR state then places the boundary scan register between the
TDI and TDO pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM DQ pins are
forced to an inactive drive state (high impedance) and the boundary register is connected
between TDI and TDO when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2
0
IR1
0
IR0
0
Instruction
EXTEST
Note
0
0
1
IDCODE
0
1
0
SAMPLE-Z
1
2
0
1
1
RESERVED
SAMPLE / PRELOAD
RESERVED
RESERVED
BYPASS
1
0
0
1
0
1
2
2
1
1
0
1
1
1
Notes 1. TRISTATE all DQ pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
2. Do not use this instruction code because the vendor uses it to evaluate this product.
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 28 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Output Pin States of CQ, CQ# and Q
Instructions
Control-Register Status
Output Pin Status
CQ,CQ#
Update
Update
SRAM
SRAM
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
Q
EXTEST
0
1
0
1
0
1
0
1
0
1
High-Z
Update
SRAM
SRAM
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 109).
Boundary Scan
Register
CAPTURE
Register
There are three statuses:
Update : Contents of the “Update Register” are output to
the output pin (QDR Pad).
SRAM
Output
Update
Register
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (QDR Pad).
High-Z : The output pin (QDR Pad) becomes high
impedance by controlling of the “High-Z JTAG
ctrl”.
Update
QDR
Pad
SRAM
SRAM
Output
Driver
High-Z
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
High-Z
JTAG ctrl
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 29 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Boundary Scan Register Status of Output Pins CQ, CQ# and Q
Instructions
SRAM Status
Boundary Scan Register Status
Note
CQ,CQ#
Pad
Pad
–
Q
Pad
Pad
–
EXTEST
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
READ (Low-Z)
NOP (High-Z)
IDCODE
SAMPLE-Z
SAMPLE
BYPASS
No definition
–
–
Pad
Pad
Internal
Internal
–
Pad
Pad
Internal
Pad
–
No definition
–
–
Remark The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mode.
Boundary Scan
Register
CAPTURE
Register
There are two statuses:
Internal
Pad
: Contents of the output pin (QDR Pad) are captured
in the “CAPTURE Register” in the Boundary Scan
Register.
SRAM
Output
Update
Register
Pad
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
QDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 30 of 36
μPD44325092B, μPD44325182B, μPD44325362B
TAP Controller State Diagram
1
0
Test-Logic-Reset
0
1
1
1
Run-Test / Idle
Select-DR-Scan
0
Select-IR-Scan
0
1
1
Capture-DR
0
Capture-IR
0
0
0
Shift-DR
1
Shift-IR
1
1
1
Exit1-DR
0
Exit1-IR
0
0
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS may be left open
but fix them to VDD via a resistor of about 1 kΩ when the TAP controller is not used. TDO should be left unconnected
also when the TAP controller is not used.
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 31 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Run-Test/Idle
Update-IR
Exit1-IR
Shift-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-Logic-Reset
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 32 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Test-Logic-Reset
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Update-DR
Exit1-DR
Shift-DR
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
Select-DR-Scan
Run-Test/Idle
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 33 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Package Dimensions
165-PIN PLASTIC BGA(15x17)
w S
B
ZD
B
E
ZE
11
10
9
8
7
A
6
5
D
4
3
2
1
R P N M L K J H G F E D C B A
INDEX MARK
w
S A
A
(UNIT:mm)
ITEM DIMENSIONS
A2
y1
S
D
E
15.00 0.10
17.00 0.10
0.30
S
w
A
1.35 0.11
0.37 0.05
0.98
A1
A2
e
y
e
x
A1
A B
S
1.00
M
b
S
+0.10
b
0.50
0.05
x
0.10
y
0.15
y1
ZD
ZE
0.25
2.50
1.50
P165F5-100-FQ1-1
Renesas Electronics Corporation 2010
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 34 of 36
μPD44325092B, μPD44325182B, μPD44325362B
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
μPD44325092BF5-FQ1 : 165-pin PLASTIC BGA (15 x 17)
μPD44325182BF5-FQ1 : 165-pin PLASTIC BGA (15 x 17)
μPD44325362BF5-FQ1 : 165-pin PLASTIC BGA (15 x 17)
Quality Grade
• A quality grade of the products is “Standard”.
• Anti-radioactive design is not implemented in the products.
• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to
the ground and so forth.
R10DS0038EJ0200 Rev.2.00
August 11, 2011
Page 35 of 36
Revision History
μPD44325092B, μPD44325182B , μPD44325362B
Description
Summary
Rev.
1st edition
Date
Page
-
’08.03.01
New Preliminary Data Sheet
2nd edition ’10.03.01
P14
P15
DC Characteristics (Modification, Spec of IDD and ISB1
Thermal Characteristics (Modification, Spec)
)
Rev.1.00
Rev.2.00
’10.09.10
’11.08.11
Throughout Preliminary Data Sheet → Data Sheet
Throughout Add Lead and the extended temperature operation product
All trademarks and registered trademarks are the property of their respective owners.
C - 36
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