UPD44325362F5-E50-EQ2-A [NEC]
QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165;型号: | UPD44325362F5-E50-EQ2-A |
厂家: | NEC |
描述: | QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165 存储 内存集成电路 静态存储器 |
文件: | 总32页 (文件大小:348K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD44325082, 44325092, 44325182, 44325362
36M-BIT QDRTMII SRAM
2-WORD BURST OPERATION
Description
The µPD44325082 is a 4,194,304-word by 8-bit, the µPD44325092 is a 4,194,304-word by 9-bit, the µPD44325182 is a
2,097,152-word by 18-bit and the µPD44325362 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The µPD44325082, µPD44325092, µPD44325182 and µPD44325362 integrate unique synchronous peripheral
circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive
edge of K and /K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC FBGA.
Features
• 1.8 ± 0.1 V power supply and HSTL I/O
• DLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR READ and WRITE operation
• Two-tick burst for low DDR transaction size
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output clocks (C and /C) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability with µs restart
• User programmable impedance output
• Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz)
• Simple control logic for easy depth expansion
• JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M16783EJ1V0DS00 (1st edition)
Date Published October 2004 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2003
µPD44325082, 44325092, 44325182, 44325362
Ordering Information
Part number
Cycle
Clock
Organization Core Supply
I/O
Package
Time Frequency (word x bit)
Voltage
V
Interface
ns
MHz
250
200
250
200
250
200
250
200
µPD44325082F5-E40-EQ2
µPD44325082F5-E50-EQ2
µPD44325092F5-E40-EQ2
µPD44325092F5-E50-EQ2
µPD44325182F5-E40-EQ2
µPD44325182F5-E50-EQ2
µPD44325362F5-E40-EQ2
µPD44325362F5-E50-EQ2
4.0
5.0
4.0
5.0
4.0
5.0
4.0
5.0
4 M x 8-bit
4 M x 9-bit
2 M x 18-bit
1M x 36-bit
1.8 ± 0.1
HSTL
165-pin PLASTIC
FBGA (13 x 15)
Preliminary Data Sheet M16783EJ1V0DS
2
µPD44325082, 44325092, 44325182, 44325362
Pin Configurations
/××× indicates active low signal.
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[µPD44325082F5-EQ2]
1
2
3
A
4
5
/NW1
NC
A
6
7
NC
/NW0
A
8
9
A
10
A
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
A
B
C
D
E
F
/CQ
NC
NC
NC
NC
NC
NC
/DLL
NC
NC
NC
NC
NC
NC
TDO
VSS
NC
NC
D4
/W
/K
/R
NC
NC
NC
Q4
NC
Q5
VDDQ
NC
NC
D6
NC
NC
Q7
A
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
NC
NC
D2
VSS
A
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
D5
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
VREF
Q1
G
H
J
VREF
NC
NC
Q6
K
L
NC
NC
NC
NC
NC
TMS
M
N
P
R
NC
D7
VSS
VSS
NC
TCK
A
A
C
A
A
A
A
/C
A
A
A
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Nibble Write data select
: Input clock
TMS
TDI
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
D0 to D7
Q0 to Q7
/R
TCK
TDO
VREF
VDD
VDDQ
VSS
/W
/NW0, /NW1
K, /K
C, /C
: Output clock
CQ, /CQ
ZQ
/DLL
: Echo clock
: Output impedance matching
: DLL disable
NC
: No connection
Remarks 1. Refer to Package Drawing for the index mark.
2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.
Preliminary Data Sheet M16783EJ1V0DS
3
µPD44325082, 44325092, 44325182, 44325362
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[µPD44325092F5-EQ2]
1
2
3
A
4
5
6
7
NC
/BW0
A
8
9
A
10
A
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
A
B
C
D
E
F
/CQ
NC
NC
NC
NC
NC
NC
/DLL
NC
NC
NC
NC
NC
NC
TDO
VSS
NC
NC
D5
/W
NC
NC
A
/K
/R
NC
NC
NC
Q5
NC
Q6
VDDQ
NC
NC
D7
NC
NC
Q8
A
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
NC
NC
D3
VSS
A
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
NC
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
G
H
J
VREF
NC
NC
Q7
K
L
M
N
P
R
NC
D8
VSS
VSS
NC
TCK
A
A
C
A
A
A
A
/C
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL disable
TMS
TDI
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
D0 to D8
Q0 to Q8
/R
/W
/BW0
K, /K
C, /C
CQ, /CQ
ZQ
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
: No connection
/DLL
Remarks 1. Refer to Package Drawing for the index mark.
2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.
Preliminary Data Sheet M16783EJ1V0DS
4
µPD44325082, 44325092, 44325182, 44325362
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[µPD44325182F5-EQ2]
1
2
3
4
5
/BW1
NC
A
6
7
NC
/BW0
A
8
9
A
10
VSS
NC
Q7
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
/CQ
NC
NC
NC
NC
NC
NC
/DLL
NC
NC
NC
NC
NC
NC
TDO
VSS
Q9
A
/W
/K
/R
D9
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
VSS
A
VSS
D11
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
NC
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
Q12
D13
VREF
NC
NC
NC
VREF
Q4
G
H
J
K
L
NC
D3
Q15
NC
NC
Q1
M
N
P
R
D17
NC
VSS
VSS
NC
D0
A
A
C
A
A
TCK
A
A
/C
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
TMS
TDI
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
D0 to D17
Q0 to Q17
/R
TCK
TDO
VREF
VDD
VDDQ
VSS
/W
/BW0, /BW1
K, /K
C, /C
: Output clock
CQ, /CQ
ZQ
/DLL
: Echo clock
: Output impedance matching
: DLL disable
NC
: No connection
Remarks 1. Refer to Package Drawing for the index mark.
2. 2A and 10A are expansion addresses: 10A for 72Mb and 2A for 144Mb.
Preliminary Data Sheet M16783EJ1V0DS
5
µPD44325082, 44325092, 44325182, 44325362
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[µPD44325362F5-EQ2]
1
2
3
4
5
/BW2
/BW3
A
6
7
/BW1
/BW0
A
8
9
10
VSS
Q17
Q7
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
B
C
D
E
F
/CQ
Q27
D27
D28
Q29
Q30
D30
/DLL
D31
Q32
Q33
D33
D34
Q35
TDO
VSS
NC
/W
/K
/R
A
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
A
K
A
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
VSS
A
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
D15
D6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
Q14
D13
VREF
Q4
G
H
J
K
L
D3
Q11
Q1
M
N
P
R
VSS
VSS
D9
A
A
C
A
A
D0
A
A
/C
A
A
A
TMS
A
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
TMS
TDI
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
D0 to D35
Q0 to Q35
/R
TCK
TDO
VREF
VDD
VDDQ
VSS
/W
/BW0 to /BW3
K, /K
C, /C
: Output clock
CQ, /CQ
ZQ
/DLL
: Echo clock
: Output impedance matching
: DLL disable
NC
: No connection
Remarks 1. Refer to Package Drawing for the index mark.
2. 3A and 10A are expansion addresses: 3A for 72Mb and 10A for 144Mb.
Preliminary Data Sheet M16783EJ1V0DS
6
µPD44325082, 44325092, 44325182, 44325362
Pin Identification
Symbol
Description
A
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the
rising edge of K for READ cycles and must meet the setup and hold times around the rising edge of /K for
WRITE cycles. All transactions operate on a burst of two words (one clock period of bus activity). These inputs
are ignored when device is deselected.
D0 to Dxx
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and /K
during WRITE operations. See Pin Configurations for ball site location of individual signals.
x8 device uses D0 to D7.
x9 device uses D0 to D8.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Q0 to Qxx
Synchronous Data Outputs: Output data is synchronized to the respective C and /C or to K and /K rising edges
if C and /C are tied HIGH. This bus operates in response to /R commands. See Pin Configurations for ball site
location of individual signals.
x8 device uses Q0 to Q7.
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
/R
Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be
initiated. This input must meet setup and hold times around the rising edge of K.
Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be
initiated. This input must meet setup and hold times around the rising edge of K.
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations
for signal to data relationships.
/W
/BWx
/NWx
K, /K
C, /C
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data
on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous
inputs must meet setup and hold times around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of
/C is used as the output timing reference for first output data. The rising edge of C is used as the output
reference for second output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied HIGH to
force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied
HIGH, C and /C must remain HIGH and not be toggled during device operation.
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q
tristates.
CQ, /CQ
ZQ
Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus
impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to
ground. This pin cannot be connected directly to GND or left unconnected.
/DLL
DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation.
TMS
TDI
IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not
used in the circuit.
TCK
IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the
circuit.
TDO
VREF
VDD
IEEE 1149.1 Test Output: 1.8V I/O level.
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range.
VDDQ
Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics
and Operating Conditions for range.
VSS
NC
Power Supply: Ground
No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level
applied to the ball sites. These signals may be connected to ground to improve package heat dissipation.
Preliminary Data Sheet M16783EJ1V0DS
7
µPD44325082, 44325092, 44325182, 44325362
Block Diagram
[µPD44325082]
21
ADDRESS
/R
ADDRESS
REGISTRY
& LOGIC
21
21
20
/W
K
/K
/W
/NW0
/NW1
221 x 16
DATA
16
16
8
2
16
8
D0 to D7
/R
Q0 to Q7
REGISTRY
& LOGIC
MEMORY
ARRAY
MUX
CQ,
/CQ
K
K
K
C, /C
/K
OR
K, /K
[µPD44325092]
21
ADDRESS
/R
ADDRESS
REGISTRY
& LOGIC
/W
K
/K
/W
/BW0
221 x 18
DATA
18
18
9
2
18
9
Q0 to Q8
REGISTRY
& LOGIC
D0 to D8
/R
MEMORY
ARRAY
MUX
CQ,
/CQ
K
K
K
C, /C
OR
K, /K
/K
[µPD44325182]
20
ADDRESS
/R
ADDRESS
REGISTRY
& LOGIC
/W
K
/K
/W
/BW0
/BW1
220 x 36
DATA
36
36
18
2
36
18
Q0 to Q17
REGISTRY
& LOGIC
D0 to D17
/R
MEMORY
ARRAY
MUX
CQ,
/CQ
K
K
K
C, /C
OR
/K
K, /K
Preliminary Data Sheet M16783EJ1V0DS
8
µPD44325082, 44325092, 44325182, 44325362
[µPD44325362]
19
ADDRESS
/R
ADDRESS
REGISTRY
& LOGIC
19
/W
K
/K
/W
/BW0
/BW1
/BW2
/BW3
219 x 72
DATA
72
72
36
2
72
Q0 to Q35
REGISTRY
& LOGIC
MEMORY
ARRAY
MUX
36
D0 to D35
CQ,
/CQ
/R
K
K
K
C, /C
/K
OR
K, /K
Power-on Sequence
The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after
VDD/VDDQ stable and when starting the clock before VDD/VDDQ stable.
1. Clock starts after VDD/VDDQ stable
V
DD/VDDQ
V
DD/VDDQ Stable (< 0.1 V DC per 50 ns)
Clock
Clock Start
1,024 cycles or more
Stable Clock
Start
Normal Operation
2. Clock starts before VDD/VDDQ stable
V
DD/VDDQ
VDD/VDDQ Stable (< 0.1 V DC per 50 ns)
Clock
Clock Start
30 ns (MIN.)
1,024 cycles or more Start
DLL Reset or DLL Off
Stable Clock
Normal Operation
Preliminary Data Sheet M16783EJ1V0DS
9
µPD44325082, 44325092, 44325182, 44325362
Truth Table
Operation
CLK
/R
X
/W
L
D or Q
Data in
WRITE cycle
L → H
Load address, input write data on
consecutive K and /K rising edge
READ cycle
Input data
Input clock
Data out
DA (A+0)
DA (A+1)
K( t ) ↑
/K( t ) ↑
L → H
L
X
Load address, output data on
consecutive C and /C rising edge
NOP (No operation)
Output data
Output clock
QA (A+0)
QA (A+1)
/C(t+1) ↑
C(t+2) ↑
L → H
H
X
H
X
D=X or Q=High-Z
Previous state
STANDBY(Clock stopped)
Stopped
Remarks 1. H : High level, L : Low level, × : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges
except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of
K. All control inputs are registered during the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = /(/K) = C = /(/C) when clock is stopped. This is not essential but permits most
rapid restart by overcoming transmission line charging symmetrically.
Preliminary Data Sheet M16783EJ1V0DS
10
µPD44325082, 44325092, 44325182, 44325362
Byte Write Operation
[µPD44325082]
Operation
K
/K
–
/NW0
/NW1
Write D0 to D7
L → H
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
–
L → H
–
L → H
–
Write D0 to D3
Write D4 to D7
Write nothing
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remarks 1. H : High level, L : Low level, → : rising edge.
2. Assumes a WRITE cycle was initiated. /NW0 and /NW1 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[µPD44325092]
Operation
K
L → H
–
/K
–
/BW0
Write D0 to D8
Write nothing
0
0
1
1
L → H
–
L → H
–
L → H
Remarks 1. H : High level, L : Low level, → : rising edge.
2. Assumes a WRITE cycle was initiated. /BW0 can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[µPD44325182]
Operation
K
L → H
–
/K
–
/BW0
/BW1
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remarks 1. H : High level, L : Low level, → : rising edge.
2. Assumes a WRITE cycle was initiated. /BW0 and /BW1 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Preliminary Data Sheet M16783EJ1V0DS
11
µPD44325082, 44325092, 44325182, 44325362
[µPD44325362]
Operation
K
/K
–
/BW0
/BW1
/BW2
/BW3
Write D0 to D35
L → H
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
–
L → H
–
L → H
–
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
–
L → H
Remarks 1. H : High level, L : Low level, → : rising edge.
2. Assumes a WRITE cycle was initiated. /BW0 to /BW3 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Bus Cycle State Diagram
LOAD NEW
WRITE ADDRESS
AT /K
LOAD NEW
READ ADDRESS
/R = L
Always
Always
/W = L
WRITE DOUBLE
AT /K
READ DOUBLE
/R = L
/W = L
/W = H
/R = H
/W = H
/R = H
Supply voltage
provided
Supply voltage
provided
READ PORT NOP
R_Init = 0
WRITE PORT NOP
Power UP
Remarks 1. The address is concatenated with 1 additional internal LSB to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1.
Bus cycle is terminated at the end of this sequence (burst count = 2).
2. Read and write state machines can be active simultaneously.
3. State machine control timing sequence is controlled by K.
Preliminary Data Sheet M16783EJ1V0DS
12
µPD44325082, 44325092, 44325182, 44325362
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol Conditions
MIN.
–0.5
–0.5
–0.5
–0.5
0
TYP.
MAX.
Unit
V
Supply voltage
VDD
VDDQ
VIN
+2.5
Output supply voltage
Input voltage
VDD
VDD + 0.5 (2.5 V MAX.)
VDDQ + 0.5 (2.5 V MAX.)
70
V
V
Input / Output voltage
Operating ambient temperature
Storage temperature
VI/O
TA
V
°C
°C
Tstg
–55
+125
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70 °C)
Parameter
Supply voltage
Symbol
Conditions
MIN.
1.7
TYP.
MAX.
1.9
Unit
V
Note
VDD
Output supply voltage
High level input voltage
Low level input voltage
Clock input voltage
VDDQ
VIH (DC)
VIL (DC)
VIN
1.4
VDD
V
1
VREF + 0.1
–0.3
VDDQ + 0.3
VREF – 0.1
VDDQ + 0.3
0.95
V
1, 2
1, 2
1, 2
V
–0.3
V
Reference voltage
VREF
0.68
V
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions (TA = 0 to 70 °C)
Parameter
High level input voltage
Low level input voltage
Symbol
VIH (AC)
VIL (AC)
Conditions
MIN.
VREF + 0.2
–
TYP.
MAX.
–
Unit
V
Note
1
1
VREF – 0.2
V
Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ – 0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
Preliminary Data Sheet M16783EJ1V0DS
13
µPD44325082, 44325092, 44325182, 44325362
DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Note
x8, x9 x18 x36
Input leakage current
I/O leakage current
Operating supply current
(Read Write cycle)
ILI
–2
–2
–
–
+2
+2
µA
µA
ILO
IDD
VIN ≤ VIL or VIN ≥ VIH, –E40
750 1,050 1,250 mA
650 900 1,050
II/O = 0 mA
–E50
Cycle = MAX.
Standby supply current
(NOP)
ISB1
VIN ≤ VIL or VIN ≥ VIH, –E40
400
350
mA
II/O = 0 mA
–E50
Cycle = MAX.
High level output voltage
Low level output voltage
VOH(Low) |IOH| ≤ 0.1 mA
VOH Note1
VOL(Low) IOL ≤ 0.1 mA
VOL Note2
VDDQ – 0.2
VDDQ/2–0.12
VSS
–
–
–
–
VDDQ
VDDQ/2+0.12
0.2
V
V
3,4
3,4
3,4
3,4
VDDQ/2–0.12
VDDQ/2+0.12
Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
Capacitance (TA = 25 °C, f = 1MHz)
Parameter
Symbol
CIN
Test conditions
VIN = 0 V
MIN.
TYP.
MAX.
Unit
pF
Input capacitance(Address, Control)
Input / Output capacitance(D, Q)
Clock Input capacitance
4
6
5
5
7
6
CI/O
VI/O = 0 V
Vclk = 0 V
pF
Cclk
pF
Remark These parameters are periodically sampled and not 100% tested.
Preliminary Data Sheet M16783EJ1V0DS
14
µPD44325082, 44325092, 44325182, 44325362
AC Characteristics (TA = 0 to 70 °C, VDD = 1.8 ± 0.1 V)
AC Test Conditions
Input waveform (Rise / Fall time ≤ 0.3 ns)
1.25 V
0.75 V
0.25 V
0.75 V
Test Points
Output waveform
V
DDQ / 2
Test Points
VDDQ / 2
Output load condition
Figure 1. External load at test
VDDQ / 2
0.75 V
50 Ω
V
REF
ZO = 50 Ω
SRAM
250 Ω
ZQ
Preliminary Data Sheet M16783EJ1V0DS
15
µPD44325082, 44325092, 44325182, 44325362
Read and Write Cycle
-E40
-E50
Parameter
Symbol
Unit
Note
(250 MHz)
(200 MHz)
MIN.
MAX.
MIN.
MAX.
Clock
Average Clock cycle time (K, /K, C, /C) TKHKH
4.0
–
8.4
0.2
–
–
–
5.0
–
8.4
0.2
–
–
–
–
–
2.3
2.8
3.55
–
ns
ns
ns
ns
ns
ns
ns
1
2
Clock phase jitter (K, /K, C, /C)
Clock HIGH time (K, /K, C, /C)
Clock LOW time (K, /K, C, /C)
Clock to /clock (K→/K., C→/C.)
Clock to /clock (/K→K., /C→C.)
TKC var
TKHKL
TKLKH
TKH /KH
T /KHKH
1.6
1.6
1.8
1.8
0
0
0
0
2.0
2.0
2.2
2.2
–
0
0
0
–
Clock to data clock 200 to 250 MHz TKHCH
1.8
2.3
2.8
3.55
–
(K→C., /K→/C.)
167 to 200 MHz
133 to 167 MHz
< 133 MHz
DLL lock time (K, C)
K static to DLL reset
TKC lock
TKC reset
1,024
30
1,024
30
Cycle
ns
3
–
–
Output Times
C, /C HIGH to output valid
C, /C HIGH to output hold
C, /C HIGH to echo clock valid
C, /C HIGH to echo clock hold
CQ, /CQ HIGH to output valid
CQ, /CQ HIGH to output hold
C HIGH to output High-Z
TCHQV
TCHQX
–
– 0.45
–
– 0.45
–
– 0.3
–
– 0.45
0.45
–
0.45
–
0.3
–
0.45
–
–
– 0.45
–
– 0.45
–
– 0.35
–
– 0.45
0.45
–
0.45
–
0.35
–
0.45
–
ns
ns
ns
ns
ns
ns
ns
ns
TCHCQV
TCHCQX
TCQHQV
TCQHQX
TCHQZ
4
4
C HIGH to output Low-Z
TCHQX1
Setup Times
Address valid to K rising edge
Control inputs (/R, /W) valid to K rising
edge
TAVKH
TIVKH
0.35
0.35
–
–
0.4
0.4
–
–
ns
ns
5
5
Data inputs and write data select
inputs (/BWx, /NWx) valid to K, /K
rising edge
TDVKH
0.35
–
0.4
–
ns
5
Hold Times
K rising edge to address hold
K rising edge to control inputs (/R, /W)
hold
TKHAX
TKHIX
0.35
0.35
–
–
0.4
0.4
–
–
ns
ns
5
5
K, /K rising edge to data inputs and
write data select inputs (/BWx, /NWx)
hold
TKHDX
0.35
–
0.4
–
ns
5
Preliminary Data Sheet M16783EJ1V0DS
16
µPD44325082, 44325092, 44325182, 44325362
Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.).
2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
3. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.
DLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
5. This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions
unless otherwise noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters.
5. VDDQ is 1.5 V DC.
Preliminary Data Sheet M16783EJ1V0DS
17
µPD44325082, 44325092, 44325182, 44325362
Read and Write Timing
READ
WRITE READ
WRITE READ
WRITE NOP
WRITE NOP
1
2
3
4
5
6
7
8
9
10
K
TKHKL TKLKH
TKHKH
TKH/KH T/KHKH
/K
/R
TKHIX
TIVKH
/W
A0
A1
A2
A3
A4
A5
A6
Address
TKHAX
TAVKH
TKHAX
D11
TAVKH
D30
D10
D31
D50
D51
D60
D61
Data in
TDVKH TKHDX
TDVKH TKHDX
Q01 Q20
Data out
Q00
Q21
Q40
Q41
TCHQX TCHQX
TCQHQV
TCHQX1
TCHQZ
TCHQV TCHQV
CQ
TCHCQX
TCHCQV
/CQ
TCHCQX
TKHCH
TCHCQV
C
TKHKL TKLKH
TKHKH
TKH/KH
T/KHKH
TKHCH
/C
Remarks 1. Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2. Outputs are disable (high impedance) one clock cycle after a NOP.
3. In this example, if address A0=A1, data Q00=D10, Q01=D11.
Write data is forwarded immediately as read results.
Preliminary Data Sheet M16783EJ1V0DS
18
µPD44325082, 44325092, 44325182, 44325362
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
TCK
Pin assignments
2R
Description
Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.
Test Mode Select. This is the command input for the TAP controller state machine.
TMS
TDI
10R
11R
Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.
TDO
1R
Test Data Output. Output changes in response to the falling edge of TCK. This is the
output side of the serial registers placed between TDI and TDO.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)
Parameter
Symbol
ILI
Conditions
MIN.
–5.0
–5.0
TYP.
MAX.
+5.0
+5.0
Unit
µA
Note
JTAG Input leakage current
JTAG I/O leakage current
0 V ≤ VIN ≤ VDD
–
–
ILO
0 V ≤ VIN ≤ VDDQ ,
µA
Outputs disabled
JTAG input high voltage
JTAG input low voltage
JTAG output high voltage
VIH
VIL
1.3
–0.3
1.6
1.4
–
–
–
–
–
–
–
VDD+0.3
V
V
V
V
V
V
+0.5
–
VOH1
VOH2
VOL1
VOL2
| IOHC | = 100 µA
| IOHT | = 2 mA
IOLC = 100 µA
IOLT = 2 mA
–
JTAG output low voltage
0.2
0.4
–
Preliminary Data Sheet M16783EJ1V0DS
19
µPD44325082, 44325092, 44325182, 44325362
JTAG AC Test Conditions
Input waveform (Rise / Fall time ≤ 1 ns)
1.8 V
0.9 V
0 V
0.9 V
Test Points
Output waveform
0.9 V
Test Points
0.9 V
Output load
Figure 2. External load at test
V
TT = 0.9 V
50 Ω
ZO = 50 Ω
TDO
20 pF
Preliminary Data Sheet M16783EJ1V0DS
20
µPD44325082, 44325092, 44325182, 44325362
JTAG AC Characteristics (TA = 0 to 70 °C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Note
Clock
Clock cycle time
Clock frequency
Clock high time
Clock low time
tTHTH
fTF
100
–
–
–
–
–
–
10
–
ns
MHz
ns
tTHTL
tTLTH
40
40
–
ns
Output time
TCK low to TDO unknown
TCK low to TDO valid
TDI valid to TCK high
TCK high to TDI invalid
tTLOX
tTLOV
tDVTH
tTHDX
0
–
–
–
–
–
–
20
–
ns
ns
ns
ns
10
10
–
Setup time
TMS setup time
Capture setup time
tMVTH
tCS
10
10
–
–
–
–
ns
ns
Hold time
TMS hold time
Capture hold time
tTHMX
tCH
10
10
–
–
–
–
ns
ns
JTAG Timing Diagram
tTHTH
TCK
tMVTH
tTHTL
t
TLTH
TMS
TDI
tTHMX
tDVTH
tTHDX
tTLOV
tTLOX
TDO
Preliminary Data Sheet M16783EJ1V0DS
21
µPD44325082, 44325092, 44325182, 44325362
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register
ID register
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The second column is
the name of the input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name
Instruction register
Bypass register
ID register
Bit size
Unit
bit
3
1
bit
32
109
bit
Boundary register
bit
ID Register Definition
Part number Organization ID [31:28] vendor revision no.
ID [27:12] part no.
0000 0000 0100 1001
0000 0000 0100 1010
0000 0000 0100 1011
0000 0000 0100 1100
ID [11:1] vendor ID no.
00000010000
ID [0] fix bit
µPD44325082
µPD44325092
µPD44325182
µPD44325362
4M x 8
4M x 9
XXXX
XXXX
XXXX
XXXX
1
1
1
1
00000010000
2M x 18
1M x 36
00000010000
00000010000
Preliminary Data Sheet M16783EJ1V0DS
22
µPD44325082, 44325092, 44325182, 44325362
SCAN Exit Order
Bit
Signal name
Bump
ID
Bit
Signal name
Bump
ID
Bit
Signal name
Bump
ID
no.
x8
x9
x18 x36
no.
x8
x9
x18 x36
no.
x8
X9
x18
x36
1
/C
C
A
A
A
A
A
A
A
6R
6P
6N
7P
7N
7R
8R
8P
9R
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
NC
NC
NC
NC
NC
NC
Q3
D3
NC
NC
NC
NC
NC
NC
Q4
D4
NC D15 10D
NC Q15 9E
73
74
NC
Q4
D4
NC
NC
NC
NC
NC
NC
Q5
D5
NC
Q5
D5
NC
NC
NC Q28
Q11 Q20
D11 D20
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1H
1J
2
3
Q7
D7
Q7 10C
D7 11D
75
4
76
NC
D29
5
NC D16 9C
NC Q16 9D
77
NC Q29
6
78
NC Q12 Q21
7
Q8
D8
Q8 11B
D8 11C
79
NC
NC
NC
Q6
D6
D12 D21
NC D30
8
80
9
NC
NC
NC
NC
NC D17 9B
NC Q17 10B
11A
81
NC Q30
Q13 Q22
D13 D22
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
NC
Q0
D0
Q0
D0
Q0 11P
D0 10P
D9 10N
82
CQ
83
NC NC NC
NC NC NC
A
A
VSS
VSS 10A
84
/DLL
Q9
9P
A
A
9A
8B
7C
6C
8A
85
NC
NC
NC
NC
NC
NC
Q6
D6
NC
NC
NC
D31
NC NC
NC NC
Q1
D1
Q1 10M
D1 11N
86
NC Q31
2J
A
87
NC Q14 Q23
3K
3J
NC NC NC D10 9M
NC NC NC Q10 9N
A
88
NC
NC
NC
Q7
D7
NC
NC
D14 D23
NC D32
/R
89
2K
1K
2L
3L
1M
1L
3N
3M
1N
Q0
D0
Q1
D1
Q2
D2
Q2 11L
D2 11M
NC
NC
NC /BW1 7A
90
NC Q32
Q15 Q24
D15 D24
55 /NW0 /BW0 /BW0 /BW0 7B
91
NC NC NC D11 9L
NC NC NC Q11 10L
56
57
58
K
6B
6A
92
/K
93
NC
NC
NC
NC
NC
NC
Q7
D7
NC
D33
NC NC
NC NC
Q3
D3
Q3 11K
D3 10K
NC
NC
NC /BW3 5B
94
NC Q33
59 /NW1 NC /BW1 /BW2 5A
95
NC Q16 Q25
NC NC NC D12 9J
NC NC NC Q12 9K
60
61
62
63
64
65
66
67
68
69
70
71
72
/W
A
4A
5C
4B
3A
2A
1A
96
NC
NC
NC
Q8
D8
NC
NC
D16 D25
NC D34
97
Q1
D1
Q2
D2
Q4
D4
Q4 10J
D4 11J
11H
A
98
NC Q34 2M
A
A
A
NC
99
Q17 Q26
D17 D26
3P
2N
ZQ
VSS
100
101
102
103
104
105
106
107
108
109
NC NC NC D13 10G
NC NC NC Q13 9G
/CQ
NC
NC
NC
D35
2P
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q9 Q18 2B
D9 D18 3B
NC D27 1C
NC Q27 1B
NC Q35
1P
NC NC
NC NC
Q5
D5
Q5 11F
D5 11G
A
A
A
A
A
A
–
3R
4R
NC NC NC D14 9F
NC NC NC Q14 10F
4P
NC Q10 Q19 3D
NC D10 D19 3C
5P
Q2
D2
Q3
D3
Q6
D6
Q6 11E
D6 10E
5N
NC
NC D28 1D
5R
Internal
Preliminary Data Sheet M16783EJ1V0DS
23
µPD44325082, 44325092, 44325182, 44325362
JTAG Instructions
Instructions
EXTEST
Description
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-
scan register cells at output pins are used to apply test vectors, while those at input pins capture test
results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,
the output drive is turned on and the PRELOAD data is driven onto the output pins.
IDCODE
BYPASS
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is
placed in the test-logic-reset state.
The BYPASS instruction is loaded in the instruction register when the bypass register is placed
between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This
allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /
PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-
DR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to
capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).
Although allowing the TAP to sample metastable input will not harm the device, repeatable results
cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input
data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any
other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving
the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an
inactive drive state (high impedance) and the boundary register is connected between TDI and TDO
when the TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2
0
IR1
0
IR0
0
Instruction
EXTEST
Note
1
0
0
1
IDCODE
0
1
0
SAMPLE-Z
0
1
1
RESERVED
SAMPLE / PRELOAD
RESERVED
RESERVED
BYPASS
1
0
0
1
0
1
1
1
0
1
1
1
Note 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
Preliminary Data Sheet M16783EJ1V0DS
24
µPD44325082, 44325092, 44325182, 44325362
TAP Controller State Diagram
1
0
Test-Logic-Reset
0
1
1
1
Run-Test / Idle
Select-DR-Scan
0
Select-IR-Scan
0
1
1
Capture-DR
0
Capture-IR
0
0
0
Shift-DR
1
Shift-IR
1
1
1
Exit1-DR
0
Exit1-IR
0
0
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and
may be left unconnected. But they may also be tied to VDD through a 1 kΩ resistor.
TDO should be left unconnected.
Preliminary Data Sheet M16783EJ1V0DS
25
Test Logic Operation (Instruction Scan)
TCK
TMS
Contoroller
state
TDI
Instruction
Register state
IDCODE
New Instruction
Output Inactive
TDO
Test Logic (Data Scan)
TCK
TMS
Controller
state
TDI
Instructin
Register state
Instruction
IDCODE
Output Inactive
TDO
µPD44325082, 44325092, 44325182, 44325362
Package Drawing
165-PIN PLASTIC FBGA (13x15)
E
w S B
ZD
ZE
B
11
10
9
8
7
A
6
5
D
4
3
2
1
R P N M L K J H G F E D C B A
w S A
INDEX MARK
y1 S
A2
h
A
S
ITEM MILLIMETERS
A1
e
y
D
E
13.00
15.00
1.50
0.50
1.00
0.60
1.40
0.40
1.00
0.50
0.08
0.08
0.15
0.20
S
ZD
ZE
e
φ M
x
φ
b
S A B
h
A
A1
A2
b
y
x
w
y1
This package drawing is a preliminary version. It may be changed in the future.
Preliminary Data Sheet M16783EJ1V0DS
28
µPD44325082, 44325092, 44325182, 44325362
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of these products.
Types of Surface Mount Devices
µPD44325082F5-EQ2: 165-pin PLASTIC FBGA (13 x 15)
µPD44325092F5-EQ2: 165-pin PLASTIC FBGA (13 x 15)
µPD44325182F5-EQ2: 165-pin PLASTIC FBGA (13 x 15)
µPD44325362F5-EQ2: 165-pin PLASTIC FBGA (13 x 15)
Preliminary Data Sheet M16783EJ1V0DS
29
µPD44325082, 44325092, 44325182, 44325362
Revision History
Edition/
Page
Previous
edition
Type of
revision
Location
Description
Date
This
edition
(Previous edition → This edition)
1st edition/ Throughout Throughout Modification
Oct. 2004
Preliminary Product Information
→ Preliminary Data sheet
Package Code
F5-EQ1 → F5-EQ2
Deletion
−E60 (167MHz) and −E75 (133MHz)
Remark 2 has been added
Power-on sequence has been added
pp.3-6
p.9
pp.3-6
Addition
Pin Configurations
Power-on Sequence
p.14
p.14
Modification DC Characteristics IDD (MAX.)
MAX.
Unit
MAX.
Unit
x8, x9 x18 x36
x8, x9 x18 x36
−E40 850 900 1,030 mA
−E50 720 760 870
−E40 750 1,050 1,250 mA
−E50 650 900 1,050
DC Characteristics ISB1 (MAX.)
MAX.
x8, x9 x18 x36
230
Unit
mA
MAX.
x8, x9 x18 x36
400
Unit
mA
−E40
−E50
−E40
−E50
210
350
Preliminary Data Sheet M16783EJ1V0DS
30
µPD44325082, 44325092, 44325182, 44325362
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Preliminary Data Sheet M16783EJ1V0DS
31
µPD44325082, 44325092, 44325182, 44325362
QDR RAMs and Quad Data Rate RAMs comprise a new series of products developed by Cypress Semiconductor,
Renesas, IDT, Micron Technology, Inc., NEC Electronics, and Samsung.
•
The information in this document is current as of October, 2004. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
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determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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