UPD120N15TA-E1-AT [RENESAS]
3 Terminal Regulators, MM, /;
| 型号： | UPD120N15TA-E1-AT |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 3 Terminal Regulators, MM, / 光电二极管 输出元件 调节器 |
| 文件： | 总15页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Data Sheet
R03DS0030EJ0400
Rev.4.00
μPD120Nxx Series
Apr 15, 2011
THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A)
Description
The μPD120Nxx series provides low-voltage output regulators with the output current capacitance of 0.3 A. The output
voltage varies according to the product (1.5 V, 1.8 V, 2.5 V, or 3.3 V). The circuit current is low due to the CMOS
structure, so the power consumption in the ICs can be reduced. Moreover, since ICs are mounted in the small package
of the μPD120Nxx series, this contributes to the miniaturization of the application set.
Features
• Output current: 0.3 A
• On-chip overcurrent protection circuit
• On-chip thermal protection circuit
• Small circuit operation current: 60 μA TYP.
Applications
Digital TV, Audio, HDD, DVD, etc.
Pin Configurations (Marking Side)
SC-74A
GND
N.C.
GND
5
4
1
2
1
2
3
OUTP
OUTPUT
INPUT
GND
Block Diagram
INPUT
Overcurrent
Protection Circuit
Reference
Voltage
Circuit
Error
Amp.
OUTPUT
Thermal
Protection Circuit
GND
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
R03DS0030EJ0400 Rev.4.00
Apr 15, 2011
Page 1 of 13
μPD120Nxx Series
Chapter Title
Ordering Information
Part Number
Package
SC-74A
SC-62
Output Voltage
1.5 V
Marking
K71
7D
μ PD120N15TA
μ PD120N15T1B
μ PD120N18TA
μ PD120N18T1B
μ PD120N25TA
μ PD120N25T1B
μ PD120N33TA
μ PD120N33T1B
1.5 V
SC-74A
SC-62
1.8 V
K72
7E
1.8 V
SC-74A
SC-62
2.5 V
K73
7F
2.5 V
SC-74A
SC-62
.3.3 V
3.3 V
K74
7G
Remark -E1 or -E2 is suffixed to the end of the part number of taping products, and -A, -AT, -AY or -AZ to that of Pb-
free products. See the table below for details.
Note1
Part Number
Package
SC-74A
SC-74A
SC-74A
Package Type
<R>
Note2
μ PD120NxxTA-A
• Unit
• Unit
Note2
μ PD120NxxTA-AT
Note2
μ PD120NxxTA-E1-A
• 8 mm wide embossed t
• Pin 1 on take-up si
• 3000 pcs/reel (
Note2
μ PD120NxxTA-E1-AT
SC-74A
SC-74A
• 8 mm wid
• Pin 1
• 30
Note2
μ PD120NxxTA-E2-A
Note2
μ PD120NxxTA-E2-AT
ossed taping
w-out side
s/reel (MAX.)
Note3
μ PD120NxxT1B-AY
μ PD120NxxT1B-AZ
it
• Unit
Note3
Note3
Note3
Note3
Note3
μ PD120NxxT1B-E1-AY
μ PD120NxxT1B-E1-AZ
μ PD120NxxT1B-E2-AY
μ PD120NxxT1B-E2-AZ
• 12 mm wide embossed taping
• Pin 1 on take-up side
• 1000 pcs/reel (MAX.)
SC-62
SC-62
SC-62
• 12 mm wide embossed taping
• Pin 1 on take-up side
• 1000 pcs/reel (MAX.)
• 12 mm wide embossed taping
• Pin 1 on draw-out side
• 1000 pcs/reel (MAX.)
• 12 mm wide embossed taping
• Pin 1 on draw-out side
• 1000 pcs/reel (MAX.)
Notes 1. xx stands for symbols that indicate the output voltage.
2. Pb-free (This product does not contain Pb in external electrode and other parts.)
3. Pb-free (This product does not contain Pb in external electrode.)
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Apr 15, 2011
Page 2 of 13
μPD120Nxx Series
Chapter Title
Absolute Maximum Ratings (TA = 25°C, unless otherwise specified.)
Parameter
Symbol
Rating
Unit
μ PD120NxxTA
μ PD120NxxT1B
Input Voltage
VIN
−0.3 to +6
V
mW
°C
Note1
Note2
Note3
Power Dissipation
180/510
400/2000
PT
Operating Ambient Temperature
Operating Junction Temperature
Storage Temperature
TA
–40 to +85
–40 to +150
–55 to +150
TJ
°C
Tstg
Rth(J-A)
°C
Note2
Note3
695/245
315/62.5
Thermal Resistance (junction to ambient)
°C/W
Note 1. Internally limited. When the operating junction temperature rises over 150°C, the internal circuit shuts down the
output voltage.
2. Mounted on ceramic substrate of 75 mm2 x 0.7 mm
3. Mounted on ceramic substrate of 16 cm2 x 0.7 mm
Caution Product quality may suffer if the absolute maximum rating is eded even momentarily for any
parameter. That is, the absolute maximum ratings are ratewhich the product is on the
verge of suffering physical damage, and therefore the ped under conditions that
ensure that the absolute maximum ratings are not exce
Typical Connection
OUTPUT
INPUT
D2
CIN
COUT
CIN: 0.1 μF or higher. Slength of the line between the regulator and INPUT pin. Be sure to
connect CIN to prevent f using a laminated ceramic capacitor, it is necessary to ensure that CIN
is 0.1 μF or higher for the mperature range to be used.
COUT: 10 μF or higher. Be sure to t COUT to prevent oscillation and improve excessive load regulation. Place CIN
and COUT as close as possible to the IC pins (within 2 cm). Be sure to use the capacitor of 10 μF or higher of
capacity values and 1 to 8 Ω of equivalent series resistance under an operating condition.
D1: If the OUTPUT pin has a higher voltage than the INPUT pin, connect a diode.
D2: If the OUTPUT pin has a lower voltage than the GND pin, connect a schottky barrier diode.
Caution Make sure that no voltage is applied to the OUTPUT pin from external.
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Apr 15, 2011
Page 3 of 13
μPD120Nxx Series
Chapter Title
Recommended Operating Conditions
Parameter
Symbol
Type Number
MIN.
3.0
3.2
4.5
4.5
0
TYP.
MAX.
5.5
Unit
V
Input Voltage
VIN
μ PD120N15
μ PD120N18
μ PD120N25
μ PD120N33
All
5.5
V
5.5
V
5.5
V
Output Current
IO
0.3
A
Operating Ambient Temperature TA
Operating Junction Temperature TJ
All
− 40
− 40
+ 85
+ 125
°C
°C
All
Caution Use of conditions other than the above-listed recommended operating conditions is not a problem as
long as the absolute maximum ratings are not exceeded. However, since the use of such conditions
diminishes the margin of safety, careful evaluation is required before such conditions are used.
Moreover, using the MAX. value for all the recommended operating conditions is not guaranteed to be
safe.
Electrical Characteristics
μPD120N15 (TJ = 25°C, VIN = 5.0 V, IO = 0.15 A, CIN = 0.1 μF, COUT = 10 μF, unlotherwise specified.)
Parameter
Output Voltage
Symbol
Conditions
TYP.
1.5
MAX.
1.53
1.545
30
30
120
25
−
Unit
V
VO1
VO2
3.0 V ≤ VIN ≤ 5.5 V, 0 A ≤ IO ≤ 0.3
3.0 V ≤ VIN ≤ 5.5 V
0 A ≤ IO ≤ 0.3 A
V
Line Regulation
REGIN
REGL
IBIAS
mV
mV
μA
μA
μ Vr.m.s.
dB
Load Regulation
2
Quiescent Current
Quiescent Current Change
Output Noise Voltage
Ripple Rejection
IO = 0 A
60
ΔIBIAS
Vn
3.0 V ≤ VIN ≤ 5.5
10 Hz ≤ f ≤ 10
f = 1 kHz,
IO = 0.
−
−
100
63
<R>
R•R
VDIF
−
−
Dropout Voltage
−
0.6
1.0
0.2
−
0.9
−
V
IO
−
V
Short Circuit Current
Peak Output Current
Temperature Coefficient of
Output Voltage
IOshort
−
−
A
IOpeak
0.3
−
−
A
ΔV
°C
−
mV/°C
− 0.03
μPD120N18 (TJ = 25°C, = 0.1 μF, COUT = 10 μF, unless otherwise specified.)
Parameter
Conditions
MIN.
TYP.
1.8
−
MAX.
1.836
1.854
30
Unit
V
Output Voltage
1.764
VO2
3.2 V ≤ VIN ≤ 5.5 V, 0 A ≤ IO ≤ 0.3 A
3.2 V ≤ VIN ≤ 5.5 V
0 A ≤ IO ≤ 0.3 A
1.746
V
Line Regulation
REGIN
REGL
IBIAS
−
−
1
mV
mV
μA
Load Regulation
2
30
Quiescent Current
Quiescent Current Change
Output Noise Voltage
Ripple Rejection
IO = 0 A
−
60
−
120
25
ΔIBIAS
Vn
3.2 V ≤ VIN ≤ 5.5 V
10 Hz ≤ f ≤ 100 kHz
f = 1 kHz, 3.2 V ≤ VIN ≤ 5.5 V
IO = 0.15 A
−
μA
−
120
63
0.4
0.2
−
−
μ Vr.m.s.
dB
<R>
R•R
−
−
Dropout Voltage
VDIF
−
0.65
−
V
Short Circuit Current
Peak Output Current
Temperature Coefficient of
Output Voltage
IOshort
IOpeak
ΔVO/ΔT
VIN = 5 V
−
A
VIN = 5 V
0.3
−
−
A
IO = 0 A, 0°C ≤ TJ ≤ 125°C
−
mV/°C
− 0.06
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Apr 15, 2011
Page 4 of 13
μPD120Nxx Series
Chapter Title
μPD120N25 (TJ = 25°C, VIN = 5.0 V, IO = 0.15 A, CIN = 0.1 μF, COUT = 10 μF, unless otherwise specified.)
Parameter
Output Voltage
Symbol
Conditions
MIN.
TYP.
2.5
−
MAX.
2.55
2.575
30
Unit
V
VO1
2.45
VO2
4.5 V ≤ VIN ≤ 5.5 V, 0 A ≤ IO ≤ 0.3 A
4.5 V ≤ VIN ≤ 5.5 V
0 A ≤ IO ≤ 0.3 A
2.425
V
Line Regulation
REGIN
REGL
IBIAS
−
−
1
mV
mV
μA
Load Regulation
2
30
Quiescent Current
Quiescent Current Change
Output Noise Voltage
Ripple Rejection
IO = 0 A
−
60
−
120
25
ΔIBIAS
Vn
4.5 V ≤ VIN ≤ 5.5 V
10 Hz ≤ f ≤ 100 kHz
f = 1 kHz, 4.5 V ≤ VIN ≤ 5.5 V
IO = 0.15 A
−
μA
<R>
−
170
60
0.3
0.2
−
μ Vr.m.s.
dB
R•R
−
−
Dropout Voltage
VDIF
−
0.7
−
V
Short Circuit Current
Peak Output Current
Temperature Coefficient of
Output Voltage
IOshort
IOpeak
ΔVO/ΔT
VIN = 5 V
−
A
VIN = 5 V
0.3
−
−
−
A
− 0.07
IO = 0 A, 0°C ≤ TJ ≤ 125°C
−
mV/°C
μPD120N33 (TJ = 25°C, VIN = 5.0 V, IO = 0.15 A, CIN = 0.1 μF, COUT = 10 se specified.)
Parameter
Output Voltage
Symbol
Conditions
.3
−
MAX.
3.366
3.399
30
Unit
V
VO1
VO2
4.5 V ≤ VIN ≤ 5.5 V, 0
4.5 V ≤ VIN ≤ 5.5
0 A ≤ IO ≤ 0.
V
Line Regulation
REGIN
REGL
IBIAS
−
1
mV
mV
μA
Load Regulation
2
30
Quiescent Current
Quiescent Current Change
Output Noise Voltage
Ripple Rejection
IO = 0 A
−
60
−
120
25
ΔIBIAS
Vn
4.5
V
−
μA
<R>
−
220
60
0.2
0.2
−
μ Vr.m.s.
dB
R•R
−
−
Dropout Voltage
V
−
0.6
−
V
Short Circuit Current
Peak Output Current
Temperature Coefficient of
Output Voltage
−
A
0.3
−
−
−
A
− 0.06
0°C ≤ TJ ≤ 125°C
−
mV/°C
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Apr 15, 2011
Page 5 of 13
μPD120Nxx Series
Chapter Title
Typical Characteristics
Pd vs. TA (μ PD120NxxTA)
Pd vs. TA (μ PD120NxxT1B)
0.6
0.5
0.4
0.3
0.2
0.1
0
2.5
2
(Mounted on ceramic substrate of 75 mm2 x 0.7
(Mounted on ceramic substrate of 16 cm2 x 0.7
62.5°C/W
245°C/W
1.5
1
(Without heatsink)
695°C/W
(Without heatsink)
315°C/W
0.5
0
0
20
40
60
80
100
0
20
40
60
80
100
TA - Operating Ambient Temperature - °C
ΔVO vs. TJ
TA - Oping Ambient Temperature - °C
. TJ
10
5
O
I = 0.15 A
O
I = 0.15 A
0
μPD120N15
μPD120N33
-5
-5
μPD120N25
Δ
Δ
-10
-10
-50
0
-50
0
50
100
150
TJ - Operating Junction Temperature - °C
TJ - Operating
VO vs. VIN (μ
VO vs. VIN (μPD120N18)
2
2
TJ = 25˚C
TJ = 25˚C
I
I
I
O
O
O
= 5 mA
= 150 mA
= 300 mA
I
I
I
O
O
O
= 5 mA
= 150 mA
= 300 mA
1
0
1
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
VIN - Input Voltage - V
VIN - Input Voltage - V
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Apr 15, 2011
Page 6 of 13
μPD120Nxx Series
Chapter Title
VO vs. VIN (μPD120N25)
VO vs. VIN (μPD120N33)
5
4
3
4
T
J
= 25˚C
T = 25˚C
J
3
2
1
0
I
I
I
O
O
O
= 5 mA
2
1
0
I
I
I
O
O
O
= 5 mA
= 150 mA
= 300 mA
= 150 mA
= 300 mA
0
1
2
3
4
5
6
0
1
2
3
4
5
6
VIN - Input Voltage - V
VIN - Input Voltage - V
IBIAS (IBIAS(S)) vs. VIN (μPD120N15)
) vs. VIN (μPD120N18)
1000
800
600
400
T = 25˚C
J
T = 25˚C
J
μ
μ
200
0
I
O
= 300 mA
= 150 mA
I
O
= 300 mA
= 150 mA
IO
IO
200
0
I
O
= 5 mA
I
O
=
0
1
2
0
1
2
3
4
5
6
VI
VIN - Input Voltage - V
IBIAS (IBIAS(S)) vs25)
IBIAS (IBIAS(S)) vs. VIN (μPD120N33)
1000
800
600
400
200
1000
T = 25˚C
J
T = 25˚C
J
μ
μ
800
600
I
O
= 300 mA
= 150 mA
I
O
= 300 mA
= 150 mA
400
200
IO
I
O
I
O
= 5 mA
5
IO
= 5 mA
5
0
0
0
1
2
3
4
6
0
1
2
3
4
6
VIN - Input Voltage - V
VIN - Input Voltage - V
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Apr 15, 2011
Page 7 of 13
μPD120Nxx Series
Chapter Title
VDIF vs. TJ
IOpeak vs. VDIF (μPD120N15)
1
0.8
0.6
0.4
0.2
0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
I = 0.15 A
O
T
J
= 0°C
T
J
J
= 25°C
μPD120N15
T
= 125°C
μPD120N18
μPD120N25
μPD120N33
0
1
2
3
4
5
-25
0
25
50
75 100 125 150
VDIF - Dropout Voltage - V
TJ - Operating Junction Temperature - °C
IOpeak vs. VDIF (μPD120N18)
s. VDIF (μPD120N25)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.7
0
0
0°C
T
T
T
J
J
J
= 0°C
T
J
25°C
= 25°C
= 125°C
= 125°C
0
1
2
3
0
1
2
3
4
VDIF - Dropout
VDIF - Dropout Voltage - V
R•R vs. f
IOpeak
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
80
70
60
50
40
30
20
10
0
T
I
J
= 25°C
= 0.15 A
T
T
J
μPD120N15
μPD120N25
O
= 25°C
= 125°C
J
0
1
2
3
10
100
1000
10000
100000
VDIF - Dropout Voltage - V
f - Frequency - Hz
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Apr 15, 2011
Page 8 of 13
μPD120Nxx Series
Chapter Title
R•R vs. f
VDIF vs. IO
80
T
I
J
= 25°C
= 0.15 A
1
0.8
0.6
0.4
0.2
0
μPD120N18
70
O
60
μ
μ
μ
μ
PD120N15
μPD120N33
50
PD120N18
PD120N25
PD120N33
40
30
20
10
0
10
100
1000
10000
100000
0
0.05
0.1
0.15
0.2
0.25
0.3
f - Frequency - Hz
IO - Output Current - A
VO vs. IO (μPD120N15)
(μPD120N18)
3
2
1
0
0
200
400
0
200
400
600
800
0
IO - O
IO - Output Current - A
VO vs. IO (μP
VO vs. IO (μPD120N33)
4
5
4
3
2
3
2
1
0
1
0
200
400
600
800
200
400
600
800
0
0
IO - Output Current - A
IO - Output Current - A
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Apr 15, 2011
Page 9 of 13
μPD120Nxx Series
Chapter Title
Package Drawings (Unit: mm)
SC-74A
5 PIN PLASTIC MINI MOLD
detail of lead end
F
G
L
A
I
J
B
N
S
ITEM MILLIMETERS
K
A
B
C
2.9 0.2
0.3
0.95 (T.P.)
+0.05
0.32
D
−0.02
0.05 0.05
1.4 MAX.
E
F
+0.2
1.1
G
−0.1
H
I
2.8 0.2
+0.2
1.5
−0.1
+0.1
0.65
J
−0.15
+0.1
0.16
K
−0.06
L
M
N
R
0.4 0.2
0.19
0.1
5° 5°
S5TA-95-15A
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Page 10 of 13
μPD120Nxx Series
Chapter Title
SC-62
4.5 0.1
1.6 0.2
1.5 0.1
0.42
0.06
0.42
0.06
0.47
0.06
+0.03
–0.05
0.41
1.5 TYP.
3.0 TYP.
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Apr 15, 2011
Page 11 of 13
μPD120Nxx Series
Chapter Title
<R>
Recommended Soldering Conditions
The μ PD120Nxx series should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact a Renesas Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.renesas.com/prod/package/manual/)
Surface Mount Device
μPD120N15TA-A, μPD120N18TA-A, μPD120N25TA-A, μPD120N33TA-A: SC-74ANote1
μPD120N15TA-AT, μPD120N18TA-AT, μPD120N25TA-AT, μPD120N33TA-AT: SC-74ANote1
μPD120N15T1B-AY, μPD120N18T1B-AY, μPD120N25T1B-AY, μPD120N33T1B-AY: SC-62Note2
μPD120N15T1B-AZ, μPD120N18T1B-AZ, μPD120N25T1B-AZ, μPD120N33T1B-AZ: SC-62Note2
Process
Conditions
Symbol
Infrared Ray Reflow
Peak temperature: 260°C or below (Package surface te
Reflow time: 60 seconds or less (at 220°C or highe
IR60-00-3
Maximum number of reflows processes: 3 time
Partial Heating Method
Pin temperature: 350°C or below,
P350
Heat time: 3 seconds or less (Per eac
Notes 1. Pb-free (This product does not contain Pb in extts.)
2. Pb-free (This product does not contain Pb i
Caution Do not use different soldering mr partial heating).
Remark Flux: Rosin-based flux with e 0.2 Wt% or below) is recommended.
Reference Documents
USER’S MANUAL USAGL REGULATORS
INFORMATION VOLTAGE RSMD
SEMICONDUCTOR PACKAGE MANUAL
Document No.G12702E Note
Document No.G11872E Note
http://www.renesas.com/prod/package/index.html
Note Published by the former NEC Electronics Corporation.
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Apr 15, 2011
Page 12 of 13
μPD120Nxx Series
Chapter Title
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected
wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH
(MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the
device when the input level is fixed, and also in the transition period when the input level passes through the
area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must baken to stop generation of
static electricity as much as possible, and quickly dissipate it when it has Environmental control
must be adequate. When it is dry, a humidifier should be used. It is ravoid using insulators
that easily build up static electricity. Semiconductor devices must brted in an anti-static
container, static shielding bag or conductive material. All test aning work benches
and floors should be grounded. The operator should be groumiconductor
devices must not be touched with bare hands. Similar prer PW boards with
mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on doinitial status of a MOS device.
Immediately after the power source is turned Os have not yet been initialized.
Hence, power-on does not guarantee output ntents of registers. A device is not
initialized until the reset signal is receivedexecuted immediately after power-on
for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: Ies different power supplies for the internal
operation and external interfacternal power supply after switching on the internal
power supply. When switcha rule, switch off the external power supply and then
the internal power supplyon/off sequences may result in the application of an
overvoltage to the intcausing malfunction and degradation of internal elements
due to the passage e correct power on/off sequence must be judged separately for
each device and accocations governing the device.
(6) INPUT OF SIGNAL DURINFF STATE : Do not input signals or an I/O pull-up power supply while
the device is not powered. Tnt injection that results from input of such a signal or I/O pull-up power
supply may cause malfunction ad the abnormal current that passes in the device at this time may cause
degradation of internal elements. Input of signals during the power off state must be judged separately for
each device and according to related specifications governing the device.
R03DS0030EJ0400 Rev.4.00
Apr 15, 2011
Page 13 of 13
Revision History
μPD120Nxx Series Data Sheet
Description
Summary
Rev.
Date
Page
−
Jun 2007
−
Previous No. : S17145EJ3V0DS00
4.00
Apr 15, 2011 Throughout Addition of Pb-free products (-AT, -AY)
pp.4, 5 Modification of Absolute Maximum Ratings Output Noise Voltage
10 kHz ≤ f ≤ 100 kHz -> 10 Hz ≤ f ≤ 100 kHz
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