M62393FP#DF0Q [RENESAS]
IC,D/A CONVERTER,OCTAL,8-BIT,CMOS,SOP,20PIN;
| 型号： | M62393FP#DF0Q |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,D/A CONVERTER,OCTAL,8-BIT,CMOS,SOP,20PIN 光电二极管 转换器 |
| 文件： | 总7页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Datasheet
M62393P/FP
R03DS0046EJ0400
Rev.4.00
8-bit 8ch I2C BUS D/A Converter with Buffer Amplifiers
Jun 03, 2011
Description
The M62393P/FP is an integrated circuit semiconductor of CMOS structure with 8 channels of built-in D/A converters
with output buffer operational amplifiers. The input is 2-wires serial method is used for the transfer format of digital
data to allow connection with a microcomputer with minimum wiring.
The output buffer operational amplifier employs AB class output circuit with sink and source drive capacity of 1.0 mA
or more, and it operates in the whole voltage range from VrefU to ground. And because of connects maximum 8 pieces
to 64 channels control.
Features
Digital data transfer format: I2C BUS serial data method
Output buffer operational amplifier
It operates in the whole voltage range from VrefU (0 to 5 V) to ground.
High output current drive capacity: 1.0 mA over
Preparation two high level reference voltage terminal because there are two high level reference voltage terminal, it
can set up two kinds differ voltage range.
Application
Conversion from digital control data to analog control data for home-use and industrial equipment.
Signal gain control or automatic adjustment of display-monitor or CTV.
Block Diagram
VDD
17
AO4
15
AO3
14
AO2
13
AO1
12
VCC
16
CS0 CS1 CS2
20 19 18
VrefU 2
11
Chip select
+
−
+
−
+
−
+
−
8-bit upper
segment R-2R
8-bit upper
segment R-2R
8-bit upper
segment R-2R
8-bit upper
segment R-2R
8-bit
latch
8-bit
latch
8-bit
latch
8-bit
latch
8
8-bit
latch
8-bit
latch
8-bit
latch
8-bit
latch
8-bit upper
segment R-2R
8-bit upper
segment R-2R
8-bit upper
segment R-2R
8-bit upper
segment R-2R
+
−
+
−
+
−
+
−
1
2
3
8
4
5
6
7
10
GND
9
AO5
AO6
AO7
AO8
SCL SDA
VrefL
VrefU1
R
R03DS0046EJ0400 Rev.4.00
Jun 03, 2011
Page 1 of 6
M62393P/FP
Preliminary
Pin Arrangement
M62393P/FP
R
SCL
1
2
3
4
5
6
7
8
9
20 CS0
19
18
CS1
CS2
SDA
AO5
17 VDD
16 VCC
15 AO4
14 AO3
13 AO2
12 AO1
11 VrefU2
AO6
AO7
AO8
VrefL
VrefU1
GND 10
(Top view)
Outline: 20P4 [P] (not recommend for new design)
PRSP0020DA-A (20P2N-A) [FP]
Pin Description
Pin No.
3
Pin Name
SDA
Function
Serial data input terminal
1
R
Reset signal input terminal
2
SCL
Ao1
Ao2
Ao3
Ao4
Ao5
Ao6
Ao7
Ao8
VCC
Serial clock input terminal
12
13
14
15
4
8-bit D/A converter output terminal
5
6
7
16
17
10
8
Analog power supply terminal
VDD
Digital power supply terminal
GND
VrefL
VrefU1
VrefU2
CS2
CS1
CS0
Analog and digital common GND
D/A converter low level reference voltage input terminal
D/A converter high level reference voltage input terminal 1
D/A converter high level reference voltage input terminal 2
Chip select data input terminal 2
9
11
18
19
20
Chip select data input terminal 1
Chip select data input terminal 0
R03DS0046EJ0400 Rev.4.00
Jun 03, 2011
Page 2 of 6
M62393P/FP
Preliminary
Absolute Maximum Ratings
Item
Supply voltage
Symbol
Ratings
–0.3 to +7.0
Unit
V
VCC
VDD
Supply voltage
–0.3 to +7.0
V
D/A converter high level reference voltage
Input voltage
VrefU1, 2
VIN
–0.3 to +7.0
V
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
990 (P) / 590 (FP)
–20 to +85
V
Output voltage
VO
V
Power dissipation
Pd
mW
C
C
Operating temperature
Storage temperature
Topr
Tstg
–40 to +125
Electrical Characteristics
<Digital Part>
(VCC, VDD, VrefU1, 2 = +5 V 10%, VCC VrefU1, 2, GND = VrefL = 0 V, Ta = –20 to +85C, unless otherwise noted.)
Limits
Item
Supply voltage
Supply current
Symbol
VDD
Unit
V
Conditions
Min
4.5
—
Typ
5.0
—
Max
5.5
IDD
1.0
mA
CLK = 1 MHz operation,
IAO = 0 A
Output low voltage (SDA)
VOL
—
—
0.4
V
Isink = 3 mA
Input leak current
Input low voltage
Input high voltage
IILK
VIL
VIH
–10
—
—
—
—
10
0.2 VCC
—
A
V
VIN = 0 to VCC
0.8 VCC
V
<Analog Part>
(VCC, VDD, VrefU1, 2 = +5 V 10%, VCC VrefU1, 2, GND = VrefL = 0 V, Ta = –20 to +85C, unless otherwise noted.)
Limits
Item
Supply voltage
Supply current
Symbol
VCC
Unit
Conditions
Min
4.5
—
Typ
5.0
1.6
1.0
Max
5.5
V
ICC
3.2
mA CLK = 1 MHz operation, IAO = 0 A
mA VrefU = 5 V, VrefL = 0 V
D/A converter high level
reference voltage input
current
IrefU
—
2.0
Data condition: at maximum current
D/A converter high level
reference voltage range
VrefU
VrefL
VAO
3.5
—
—
VCC
V
V
The output dose not necessarily be
the values within the reference
voltage setting range.
D/A converter low level
reference voltage range
GND
VCC – 3.5
Buffer amplifier output
voltage range
0.1
0.2
—
—
—
VCC – 0.1
VCC – 0.2
1.0
V
V
IAO = 100 A
IAO = 500 A
Buffer amplifier output
current range
IAO
–1.0
mA Upper side saturation voltage = 0.3 V
Lower side saturation voltage = 0.2 V
LSB VrefU = 4.79 V
Differential nonlinearity
Nonlinearity
SDL
SL
–1.0
–1.5
–2.0
–2.0
—
—
—
—
—
—
5.0
1.0
1.5
2.0
2.0
0.1
—
VrefL = 0.95 V
LSB
LSB
LSB
F
VCC = 5.5 V (15 mV/LSB)
Without load (IAO = 0)
Zero code error
SZERO
SFULL
CO
Full scale error
Output capacitive load
Buffer amplifier output
impedance
RO
—
R03DS0046EJ0400 Rev.4.00
Jun 03, 2011
Page 3 of 6
M62393P/FP
Preliminary
I2C BUS Line Characteristics
Normal Mode
High Speed Mode
Item
Symbol
fSCL
Unit
kHz
s
Min
0
Max
100
—
Min
0
Max
400
—
SCL clock frequency
Time the bus must be free before a new
transmission can start
tBUF
4.7
1.3
Hold time start condition. After this period.
The first clock pulse is generated.
tHD : STA
4.0
—
0.6
—
s
Low period of the clock
High period of the clock
tLOW
tHIGH
4.7
4.0
4.7
—
—
—
1.3
0.6
4.7
—
—
—
s
s
s
Setup time for start condition (only relevant for a tSU : STA
repeated start condition)
Hold time data
tHD : DAT
tSU : DAT
tR
0
—
—
0
0.9
—
s
ns
ns
ns
s
Setup time data
250
—
100
20
Rise time of both SDA and SCL lines
Fall time of both SDA and SCL lines
Setup time for stop condition
1000
300
—
300
300
—
tF
—
20
tSU : STO
4.0
0.6
Note: Transmitter must internally at reset a hold time to bridge the undefined region (300 ns Max) of the falling edge of
SCL.
Timing Chart
tr, tf
tBUF
VIH
SDA
VIL
tHD:STA
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
V
IH
SCL
VIL
tLOW
tHIGH
Start
Start
Stop
Start
R03DS0046EJ0400 Rev.4.00
Jun 03, 2011
Page 4 of 6
M62393P/FP
Preliminary
I2C BUS Format
STA
Slave address
W
A
Sub address
A
DAC data
A
STP
Digital Data Format
Slave Address
First
First
Sub Address
Last
A0
Last
1
0
0
1
A2
A1
X
X
X
X
S3
S2
S1
S0
(Slave address)
Chip select data
Don't care
Channel select data
First
DAC Data
Last
LSB
MSB
D7
D6
D5
D4
D3
D2
D1
D0
(1) Chip Select Data
(2) Channel Select Data
MSB
LSB
MSB
LSB
A2
0
A1
0
A0
0
CS2
CS1
CS0
S3
0
0
0
:
S2
0
0
0
:
S1
0
0
1
:
S0
0
1
0
:
Channel Selection
0
0
0
:
0
0
1
:
0
1
0
:
Don’t care
ch1 selection
ch2 selection
:
0
0
1
0
1
0
:
:
:
1
1
1
1
1
1
0
1
1
:
1
0
0
:
1
0
0
:
1
0
1
:
ch7 selection
ch8 selection
Don’t care
:
1
1
1
1
Don’t care
(3) DAC Data
First
MSB
Last
LSB
D7
D6
D5
D4
D3
D2
D1
D0
DAC Output
(VrefU
(VrefU
(VrefU
(VrefU
−
−
−
−
VrefL ) / 256 × 1 + VrefL
VrefL ) / 256 × 2 + VrefL
VrefL ) / 256 × 3 + VrefL
VrefL ) / 256 × 4 + VrefL
:
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
0
0
:
0
0
1
1
:
0
1
0
1
:
(VrefU
VrefU
−
VrefL ) / 256 × 255 + VrefL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
R03DS0046EJ0400 Rev.4.00
Jun 03, 2011
Page 5 of 6
M62393P/FP
Preliminary
Package Dimensions
20P4
Plastic 20pin 300mil DIP
EIAJ Package Code
DIP20-P-300-2.54
JEDEC Code
—
Weight(g)
1.3
Lead Material
Alloy 42/Cu Alloy
20
11
1
10
Dimension in Millimeters
Symbol
A
D
Min
—
Nom
—
—
Max
4.5
—
A
A
1
2
0.51
—
3.3
0.5
1.5
1.0
0.27
24.0
6.3
2.54
7.62
—
—
b
0.4
1.4
0.9
0.22
23.8
6.15
—
0.6
1.8
1.3
0.34
24.2
6.45
—
b
1
2
SEATING PLANE
b
c
D
E
e
e
b1
b
b2
e1
—
—
—
3.0
0°
L
—
15°
JEITA Package Code
RENESAS Code
PRSP0020DA-A
Previous Code
20P2N-A
MASS[Typ.]
0.3g
P-SOP20-5.3x12.6-1.27
20
11
F
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
10
c
Index mark
*2
A2
A1
D
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
12.5 12.6 12.7
5.2 5.3 5.4
1.8
A2
A1
A
*3
bp
0
0.1 0.2
2.1
e
y
Detail F
bp
c
0.35 0.4 0.5
0.18 0.2 0.25
0°
8°
HE
e
7.5 7.8 8.1
1.12 1.27 1.42
0.1
y
L
0.4 0.6 0.8
R03DS0046EJ0400 Rev.4.00
Jun 03, 2011
Page 6 of 6
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