M62399FP [MITSUBISHI]
8-BIT 8CH I2C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS; 8位8通道I2C -BUS DA与缓冲放大器，转换器
| 型号： | M62399FP |
| 厂家： | 
Mitsubishi Group |
| 描述： | 8-BIT 8CH I2C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS |
| 文件： | 总5页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI<Dig.Ana.INTERFACE>
M62399P,FP
8-BIT 8CH I2C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M62399P,FP is an integrated circuit semiconductor of
high voltage type CMOS structure with 8 channels of built-in D-
A converters with output buffer operational amplifiers.
The input is 2-wires serial method is used for the transfer
formal of digital data to allow connection with a microcomputer
with minimum wiring.
The output buffer operational amplifier employs AB class
output circuit with sync and source drive capacity of 2.5mA or
more,and it operates in the whole voltage range from VrefU to
ground.
And because of connects maximum 8 pieces,it is possible to
64 channels control.
1
2
20
19
18
17
16
15
14
13
12
11
CS0
CS1
CS2
R
SCL
3
SDA
Ao5
Ao6
4
VDD
Vcc
Ao4
5
6
Ao7
Ao8
Ao3
7
FEATURES
VrefL
Ao2
Ao1
8
•Digital data transfer format
2
9
I C-bus serial data method
VrefU1
GND
•Output buffer operational amplifier
it operates in the whole voltage range from VrefU(0~12V)to
ground.
10
VrefU2
•High output current drive capacity
±2.5mA over
•Preparation two high level reference voltage terminal
because there are two high level reference voltage
terminal,it can set up two kinds differ voltage range.
Outline 20P4(P)
20P2N-A(FP)
APPLICATION
Conversion from digital control data to analog control data
for home-use and industrial equipment.
Signal gain control or automatic adjustment of DISPLAY-
MONITOR or CTV.
BLOCK DIAGRAM
CS0 CS1 CS2 VDD
Ao4
Ao3
Ao2
Ao1
Vcc VrefU2
20
19
17
18
16
11
15
14
13
12
R2
R1
R2
R2
R2
R1
CHIP SELECT
R1
R1
8bit upper
segment R-2R
8bit upper
segment R-2R
8bit upper
segment R-2R
8bit upper
segment R-2R
8bit Latch
8bit Latch
8bit Latch
8bit Latch
R2
R1
8
=2.4
8bit Latch
8bit Latch
8bit Latch
8bit Latch
8bit upper
segment R-2R
8bit upper
segment R-2R
8bit upper
segment R-2R
8bit upper
segment R-2R
R1
R2
R1
R2
R1
R2
R1
R2
8
10
4
5
6
7
2
3
1
9
SDA
SCL
VrefL
R
Ao5
Ao6
Ao7
Ao8
VrefU1
GND
MITSUBISHI
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MITSUBISHI<Dig.Ana.INTERFACE>
M62399P,FP
8-BIT 8CH I2C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS
EXPLANATION OF TERMINALS
Function
Symbol
SDA
R
Pin No.
3
Serial data input terminal
Reset signal input terminal
Serial clock input terminal
1
2
12
SCL
Ao1
13
14
Ao2
Ao3
Ao4
Ao5
Ao6
8-bit D-A converter output terminal
15
4
5
6
7
16
Ao7
Ao8
VCC
Analog power supply terminal
Digital power supply terminal
Analog and digital common GND
17
10
8
VDD
GND
VrefL
D-A converter low level reference voltage input terminal
D-A converter high level reference voltage input terminal 1
D-A converter high level reference voltage input terminal 2
Chip select data input terminal 2
VrefU1
VrefU2
9
11
18
CS2
CS1
CS0
19
20
Chip select data input terminal 1
Chip select data input terminal 0
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ELECTRIC
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MITSUBISHI<Dig.Ana.INTERFACE>
M62399P,FP
8-BIT 8CH I2C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Conditions
Symbol
VCC
Ratings
Parameter
Supply voltage
Supply voltage
Unit
V
-0.3~+13.5
VDD
-0.3~+7.0
VDD
V
V
VrefU1,2 D-A converter upper reference voltage
VIND
-0.3~VDD+0.3
V
Digital input voltage
Topr
Tstg
-20~+85
Operating temperature
Storage temperature
°C
°C
-40~+125
ELECTRICAL CHARACTERISTICS
Digital part(Vcc=13V,VDD=VrefU1,2=+5V±10%,GND=VrefL=0V,Ta=-20 ~ +85°C,unless otherwise noted)
Limits
Typ.
Symbol
Test conditions
Parameter
Supply voltage
Unit
Min.
4.5
Max.
VDD
IDD
5.0
5.5
1
V
Supply current
CLK=1MHz operation IAO=0µA
VIN=0~VDD
mA
Input leak current
-10
10
µA
V
IILK
VIL
VIH
0.2VCC
Input low voltage
Input high voltage
V
0.8VCC
Analog part(Vcc=13V,VDD=VrefU1,2=+5V±10%,GND=VrefL=0V,Ta=-20 ~ +85°C,unless otherwise noted)
Limits
Typ.
Symbol
Test conditions
Parameter
Supply voltage
Unit
Min.
VDD
Max.
Vcc
Icc
13
V
Circuit current
2.0
1.2
4.0
mA
CLK=1MHz operation IAO=0µA
D-A converter upper reference
voltage input current
VrefU=5V VrefL=0V
Data condition:at maximum current
2.5
IrefU
mA
V
D-A converter upper reference
voltage range
VrefU
VrefL
3.5
VDD
1.5
The output does not necessarily be the
values within the reference voltage setting
range.
D-A converter lower reference
voltage range
GND
V
V
IAO=±500µA
IAO=±1.0mA
0.1
0.2
Vcc-0.1
Vcc-0.2
Buffer amplifier output voltage range
Buffer amplifier output drive range
VAO
IAO
Upper side saturation voltage=0.3V
Lower side saturation voltage=0.2V
-2.5
mA
2.5
-1.0
-1.5
-2.0
-2.0
-3.0
Differential nonlinearity error
Nonlinearity error
Zero code error
SDL
SL
SZERO
LSB
LSB
LSB
LSB
1.0
1.5
2.0
2.0
3.0
VrefU=4.79V
VrefL=0.95V
Vcc=5.5V(15mV/LSB)
without load(IAO=0)
SFULL
Eo
Full scale error
Gain error
%
Output slew rate
V/µs
SR
0.2
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MITSUBISHI<Dig.Ana.INTERFACE>
M62399P,FP
8-BIT 8CH I2C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS
I2C-BUS LINE CHARACTERISTICS
Normal mode High speed mode
Parameter
Symbol
Unit
Min
0
Max
100
Max
400
Min
0
SCL clock frequency
fSCL
KHz
µs
tBUF
4.7
4.0
Time the bus must be free before a new transmission can start
Hold time start condition.After this period.The first clock pulse is generated
The low period of the clock
1.3
0.6
1.3
0.6
4.7
µs
µs
tHD:STA
tLOW
4.7
4.0
4.7
The high period of the clock
µs
tHIGH
tSU:STA
tHD:DAT
Set up time for start condition(only relevant for a repeated start condition)
Hold time data
µs
µs
0
0.9
0
tSU:DAT
Set up time data
ns
ns
ns
250
100
20
Rise time of both SDA and SCL lines
Fall time of both SDA and SCL lines
tR
tF
300
300
1000
300
20
tSU:STO
µs
Set up time for stop condition
0.6
4.0
*Note that transmitter must internally at reset a hold time to bridge the undefined region(max.300ns)of the falling edge of SCL.
TIMING CHART
tR, tF
tBUF
VIL
SDA
VIH
tSU:DAT
tHD:DAT
tSU:STA
tHD:STA
tSU:STO
VIL
VIH
SCL
tLOW
tHIGH
P
S
S
S
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MITSUBISHI<Dig.Ana.INTERFACE>
M62399P,FP
8-BIT 8CH I2C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS
I2C BUS FORMAT
STA
SLAVE ADDRESS
W
A
SUB ADDRESS
A
DAC DATA
A
STP
DIGITAL DATA FORMAT
•SLAVE ADDRESS
FIRST
•SUB ADDRESS
FIRST
LAST
S0
LAST
A0
0
0
1
X
X
X
X
S3
S2
S1
1
A2
A1
CHANNEL
(SLAVE ADDRESS)
Don't care
CHIP SELECT DATA
SELECT DATA
•DAC DATA
FIRST
MSB
LAST
LSB
D7
D6
D5
D4
D3
D2
D1
D0
(2)CHANNEL SELECT DATA
(1)CHIP SELECT DATA
MSB
S3
LSB
S0
MSB
LSB
S2
S1
Channel selection
A2
A1
A0
CS2 CS1 CS0
0
0
0
0
0
0
0
0
1
0
1
0
Don't care.
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
0
ch1 selection
ch2 selection
0
1
1
0
0
1
0
1
ch7 selection
ch8 selection
Don't care.
1
1
1
1
1
1
1
1
0
0
1
1
1
1
Don't care.
(3)DAC DATA
LAST
LSB
FIRST
MSB
D7
D6
D5
D4
D3
D2
D1
D0
DAC output
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
(VrefU-VrefL)/256 x 1 x 2.4 + VrefL
(VrefU-VrefL)/256 x 2 x 2.4 +VrefL
(VrefU-VrefL)/256 x 3 x 2.4 +VrefL
(VrefU-VrefL)/256 x 4 x 2.4 +VrefL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
(VrefU-VrefL)/256 x 255 x 2.4 +VrefL
VrefU x 2.4 + VrefL
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