M52347SP [RENESAS]
Sync Signal Processor; SYNC信号处理器
| 型号： | M52347SP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Sync Signal Processor |
| 文件： | 总17页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M52347SP/FP
Sync Signal Processor
REJ03F0190-0200
Rev.2.00
Sep 14, 2006
Description
The M52347 automatically selects three types of synchronous signals containing separate sync (positive and negative
polarities of 0.5 to 2.5 VP-P), composite sync (positive and negative polarities of 0.5 to 2.5 VP-P) and sync-on-video
(sync negative polarity), and performs waveform shaping. The IC is optimum to synchronous signal processing for
multi-scan type display monitor.
Features
•
•
•
•
•
Low power consumption with supply voltage of 5 V
Capable of obtaining output information on whether to input synchronous signal, and on polarity
Output of clamp pulse
Equipped with V TIME GATE SW that enables selecting whether or not VD portion pulse is output from pin 14/15.
Equipped with CLAMP SW that enables switching the clamp pulse output position.
Application
Display monitor
Recommended Operating Condition
Supply voltage range:
Rated supply voltage:
VCC = 4.5 to 5.5 V
CC = 5 V
V
Block Diagram
+
−
+
+
VD
CLAMP
TIMING V.POL. H.POL.
CLAMP
OUT
17
HD
OUT
15
HD
OUT
14
V S/S
OUT
12
V S/S
IN
VCC
16
OUT
13
20
19
18
11
EDGE
SW
CLAMP
GEN
V.TIME
GATE
V.SYNC
SEP
LOGIC
LOGIC
SYNC
SEP
H
SHAPE
H
DET
V
SHAPE
V
DET
1
2
3
4
5
6
7
8
9
10
H.STATE V.STATE CLAMP GREEN
IN
GND COMP/H COMP/H V IN
IN DET
V DET V TIME GATE
SW
SW
Rev.2.00 Sep 14, 2006 page 1 of 16
M52347SP/FP
Pin Arrangement
M52347SP/FP
H.STATE
CLAMP TIMING
V.POL.
1
2
20
19
18
17
16
15
14
13
12
11
V.STATE
CLAMP SW
GREEN IN
3
H.POL.
+
CLAMP OUT
4
VCC
5
GND
−
HD OUT
COMP/H IN
6
+
HD OUT
7
COMP/H DET
V IN
+
VD OUT
8
V DET
V S/S OUT
V S/S IN
9
10
V TIME GATE SW
(Top view)
Outline: PRDP0020BA-A (20P4B) [SP]
PRSP0020DA-A (20P2N-A) [FP]
Rev.2.00 Sep 14, 2006 page 2 of 16
M52347SP/FP
Absolute Maximum Ratings
(Ta = 25°C, unless otherwise noted)
Item
Supply voltage
Power dissipation
Electrostatic discharge
Operating temperature
Storage temperature
Symbol
Ratings
Unit
V
mW
V
°C
°C
VCC
Pd
6.0
1237.6 (SP), 827.8 (FP)
±200
Surge
Topr
Tstg
−20 to +85
−40 to +150
Electrical Characteristics
(Ta = 25°C, VCC = 12 V, unless otherwise noted)
TP
Relay Condition Condition
In
put
Pin
Limits
Output
pin
4
2
6
2
8
2
16
2
3
10
Min. Typ. Max.
Item
Symbol
ICC
Unit
Input Condition
Output waveform
Note
5 V
Circuit current
40 53 66 mA
5 V 16
A
50 kHz
1 VP-P
0 V
2.5 V
5 V
Pin 1 output
Hi level
1 OH
4.0 5.0 5.0
V
V
2
1
1
1
5 V
5 V
1
1
DC
DC
*1
6
8
1 µs
50 kHz
1 VP-P
1 µs
50 kHz
0.2 VP-P
0 V
2.5 V
5 V
Pin 1 output
Low level
1 OL
0
0.04 0.5
2
1
1
1
*1, *2
6
8
1 µs
50 kHz
1.0 VP-P
1 µs
50 kHz
1 VP-P
0 V
2.5 V
5 V
6
8
Pin 2 output
Hi level
2 OH
2 OL
4.0 5.0 5.0
V
2
1
1
1
5 V
2
DC
*1
1 µs
50 kHz
1 VP-P
1 µs
50 kHz
1.0 VP-P
0 V
2.5 V
5 V
6
8
Pin 2 output
Low level
0
0.04 0.5
V
V
V
2
2
2
1
1
1
1
1
1
1
1
1
5 V
5 V
5 V
2
DC
DC
DC
*1, *2
1 µs
50 kHz
0.2 VP-P
1 µs
50 kHz
1 VP-P
0 V
2.5 V
5 V
6
8
Pin 18 output
Hi level
18 OH 4.0 5.0 5.0
18
18
*1
1 µs
50 kHz
1 VP-P
1 µs
18 OL
50 kHz
1 VP-P
0 V
2.5 V
5 V
Pin 18 output
Low level
0
0.04 0.5
6
8
*1
1 µs
50 kHz
1 VP-P
1 µs
50 kHz
1 VP-P
6
8
0 V
2.5 V
5 V
Pin 19 output
Hi level
19 OH 4.0 5.0 5.0
V
V
V
2
2
1
1
1
1
1
1
2
1
1
1
5 V
5 V
5 V
19
19
14
DC
*1
*1
1 µs
50 kHz
1 VP-P
1 µs
50 kHz
1 VP-P
0 V
2.5 V
5 V
Pin 19 output
Low level
19 OL
0
0.04 0.5
6
8
DC
1 µs
50 kHz
1 VP-P
1 µs
50 kHz
0.6 VP-P
0 V
2.5 V
5 V
4
6
Pin 14 output
Hi level
14 OH 4.0 5.0 5.0
V Meas
1 µs
50 kHz
2 VP-P
1 µs
50 kHz
0.6 VP-P
0 V
2.5 V
5 V
Pin 14 output
Low level
14 OL
0
0.25 0.5
V
1
1
2
1
5 V
14
4
6
1 µs
50 kHz
2 VP-P
V Meas
1 µs
Notes: 1. The true value table depends on Table 1
2. 0.2 VP-P of input signal is equivalent to NON SYNC.
Rev.2.00 Sep 14, 2006 page 3 of 16
M52347SP/FP
Electrical Characteristics (cont.)
TP
Relay Condition Condition
In
put
Pin
Limits
Output
pin
Item
Symbol
15 OH
4
6
8
16
3
10
Input Condition
50 kHz
1 µs
0.6 VP-P
Output waveform
V Meas
Note
Unit
V
Min. Typ. Max.
0 V
2.5 V
5 V
Pin 15 output
Hi level
4.0 5.0 5.0
1
1
2
1
5 V
4
6
15
15
17
17
13
13
12
12
50 kHz
2 VP-P
1 µs
50 kHz
0.6 VP-P
0 V
2.5 V
5 V
0
0.25 0.5
V
V
V
V
V
V
V
1
1
1
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
1
1
1
1
1
1
5 V
5 V
5 V
5 V
5 V
5 V
Pin 15 output
Low level
15 OL
17 OH
17 OL
13 OH
13 OL
12 OH
4
6
1 µs
50 kHz
2 VP-P
V Meas
V Meas
1 µs
50 kHz
0.6 VP-P
0 V
2.5 V
5 V
Pin 17 output
Hi level
4.0 5.0 5.0
4
6
1 µs
50 kHz
2 VP-P
1 µs
50 kHz
0.6 VP-P
0 V
2.5 V
5 V
Pin 17 output
Low level
0
0.25 0.5
4
6
1 µs
50 kHz
2 VP-P
V Meas
V Meas
1 µs
0 V
2.5 V
5 V
50 kHz
2 VP-P
Pin 13 output
Hi level
4.0 5.0 5.0
8
1 µs
0 V
2.5 V
5 V
50 kHz
2 VP-P
0
0.25 0.5
Pin 13 output
Low level
8
1 µs
V Meas
V Meas
50 kHz
0.6 VP-P
0 V
2.5 V
5 V
Pin 12 output
Hi level
4.0 5.0 5.0
4
6
4
1 µs
50 kHz
2 VP-P
1 µs
50 kHz
0.6 VP-P
0 V
2.5 V
5 V
Pin 12 output
Low level
0
0.25 0.5
1
1
1
2
2
2
1
1
5 V
5 V
12 OL
1 µs
50 kHz
2 VP-P
V Meas
6
4
1 µs
0 V
2.5 V
5 V
Sync-Sep Sync
input signal Max.
noise amplitude
voltage
SS-NV
0.05 VP-P
No pulse must be output.
50 kHz
0.05 VP-P
14
15
17
*3
1 µs
50 kHz
0.2 VP-P
0 V
2.5 V
5 V
50 kHz
14
17
*4
*5
*6
Sync-Sep Sync
input signal Min.
amplitude voltage
0.2
VP-P
1
2
2
2
1
1
2
2
2
1
1
1
5 V
5 V
5 V
4
SS-LV
V3H
V3L
1 µs
No pulse must be output
in this portion.
DC voltage must be
applied.
50 kHz
CLAMP SW
threshold voltage
H
14, 17
15
Vari-
able
3
6
2.8 3.1 3.4
1.0 1.3 1.6
V
1 µs
2 VP-P
DC voltage must be
14, 17
15
Vari-
able
CLAMP SW
threshold voltage
H variable
3
6
V
applied.
50 kHz
1 µs
2 VP-P
50 kHz
2 VP-P
Vari-
able
6
8
1 µs
0 V
5 V
*7
V10
V TIME GATE
SW threshold
voltage variable
2.0 2.5 3.0
V
2
1
1
1
14
15
50 kHz
2 VP-P
1 µs
DC voltage must be
applied.
10
Notes: 3. Must not operate when input amplitude is 0.05 VP-P or less. (Pseudo noise signal)
4. Must operate when the input amplitude is 0.2 VP-P or more.
5. Checking output pulse for output with a voltage of 5 VDC applied, decrease the DC voltage and then
measure the voltage when the output pulse is not output.
6. Checking output pulse for output with a voltage of 0 VDC applied, increase the DC voltage and then measure
the voltage when the output pulse is not output.
7. Checking output pulse for output with a voltage of 5 VDC applied, decrease the DC voltage and then
measure the voltage when the output pulse becomes narrow.
Rev.2.00 Sep 14, 2006 page 4 of 16
M52347SP/FP
Electrical Characteristics (cont.)
TP
Condition
In
put
Pin
Limits
Relay Condition
Output
pin
4
6
8
16
3
10
Input Condition
50 kHz
1 µs
0.6 VP-P
Output waveform
Input 6 (50%)
Note
Item
Symbol Min. Typ. Max. Unit
+
+
120 350 ns
80 350 ns
140 350 ns
120 350 ns
70 350 ns
120 350 ns
100 350 ns
150 350 ns
90 350 ns
130 350 ns
90 350 ns
1
1
2
1
14
14
14
14
15
15
15
15
17
17
17
17
13
HD -delay time HD -DA
(A)
5 V
4
6
Time
Meas
50 kHz
2 VP-P
1 µs
Output 14 (50%)
Input 6 (50%)
Time
Meas
Output 14 (50%)
50 kHz
0.6 VP-P
+
+
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
HD -delay time
(B)
HD -DB
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
5 V
0 V
0 V
0 V
5 V
4
6
1 µs
50 kHz
2 VP-P
1 µs
50 kHz
0.6 VP-P
Input 4 (50%)
+
+
2.5 V
HD -delay time
(C)
HD -DC
4
6
1 µs
Time
Meas
50 kHz
2 VP-P
1 µs
Output 14 (50%)
Input 4 (50%)
Time
Meas
Output 14 (50%)
+
50 kHz
0.6 VP-P
HD -delay time
(D)
+
2.5 V
4
6
HD -DD
1 µs
50 kHz
2 VP-P
1 µs
−
50 kHz
0.6 VP-P
Input 6 (50%)
−
HD -delay time
(A)
0 V
5 V
HD -DA
4
6
1 µs
Time
Meas
50 kHz
2 VP-P
1 µs
Output 15 (50%)
Input 6 (50%)
Time
Meas
Output 15 (50%)
−
50 kHz
0.6 VP-P
−
HD -delay time
(B)
HD -DB
0 V
5 V
4
6
1 µs
50 kHz
2 VP-P
1 µs
−
50 kHz
0.6 VP-P
Input 4 (50%)
−
HD -delay time
(C)
2.5 V
2.5 V
0 V
HD -DC
4
6
1 µs
Time
Meas
50 kHz
2 VP-P
1 µs
Output 15 (50%)
Input 4 (50%)
Time
Meas
Output 15 (50%)
−
50 kHz
0.6 VP-P
−
HD -delay time
(D)
HD -DD
4
6
1 µs
50 kHz
2 VP-P
1 µs
50 kHz
0.6 VP-P
Input 6 (50%)
+
Time
Meas
+
CP -delay time
(A)
CP -DA
4
6
1 µs
50 kHz
2 VP-P
1 µs
Output 17 (50%)
Input 4 (50%)
50 kHz
0.6 VP-P
+
Time
Meas
+
CP -delay time
(B)
2.5 V
5 V
CP -DB
4
6
1 µs
50 kHz
2 VP-P
1 µs
Output 17 (50%)
Input 6 (50%)
50 kHz
0.6 VP-P
+
+
CP -delay time
(C)
CP -DC
4
6
1 µs
Time
Meas
50 kHz
2 VP-P
1 µs
Output 17 (50%)
+
Time
Meas
50 kHz
0.6 VP-P
+
CP -PULSE-
WIDTH
0 V
2.5 V
5 V
250 400 550 ns
CP -PW
4
6
1 µs
50 kHz
2 VP-P
Output 17 (50%)
Input 8 (50%)
1 µs
+
+
50 kHz
2 VP-P
VD -delay time
(A)
0 V
2.5 V
5 V
100 350 ns
70 350 ns
8
VD -DA
Time
Meas
1 µs
Output 13 (50%)
Input 8 (50%)
Time
Meas
Output 13 (50%)
+
50 kHz
2 VP-P
+
VD -delay time
(B)
0 V
2.5 V
5 V
13
14
VD -DB
8
1 µs
50 kHz
2 VP-P
6
1 µs
V Sync-Sep
threshold voltage
H
*8
*9
3.0 3.5 4.0
1.3 1.8 2.3
V
V
0 V
5 V
V11H
V11L
DC voltage must be
applied.
11
15
14
50 kHz
2 VP-P
1 µs
V Sync-Sep
threshold voltage
L
0 V
5 V
6
DC voltage must be
applied.
11
15
Notes: 8. Checking output pulse for output with a voltage of 0 VDC applied, increase the DC voltage and then measure
the voltage when the output pulse is not output.
9. Checking output pulse for output with a voltage of 5 VDC applied, decrease the DC voltage and then
measure the voltage when the output pulse is output.
Rev.2.00 Sep 14, 2006 page 5 of 16
M52347SP/FP
Test Circuit
V11
V10
V TIME
GATA SW
100 p
43 k
V S/S IN
11
10
10 µ
V DET
V IN
12
13
14
9
8
7
V S/S OUT
2
1
R8
4.7 µ
+
VD OUT
TP13
TP14
0.0068 µ
+
HD OUT
COMP/H DET
2
1
4.7 µ
R6
−
HD OUT
COMP/H IN
GND
15
16
6
5
TP15
2
1
VCC
5 V
R16
0.01 µ
47 µ
TP17
2
1
75 k
R4
+
CLAMP OUT
17
18
19
4
3
2
GREEN IN
CLAMP SW
V.STATE
3.3 µ
H.POL.
V.POL.
TP18
TP19
V3
TP2
TP1
4.3 k
CLAMP
TIMING
20
1
H.STATE
220 p
: 5 V
Units Resistance: Ω
Capacitance: F
Rev.2.00 Sep 14, 2006 page 6 of 16
M52347SP/FP
Pin Description
DC Voltage
(V)
Pin No.
Name
Peripheral Circuit
Function
1
H.STATE
0 VDC or
5 VDC
Logic output pin for horizontal
synchronous signal
When pin 6 input signal is POSI,
outputs "H"; when NON, outputs "L";
and when NEG, outputs "H".
20 kΩ
1
2
3
V.STATE
0 VDC or
5 VDC
Same as pin 1
Logic output pin for vertical
synchronous signal
When pin 8 input signal is POSI,
outputs "H"; when NON, outputs "L";
and when NEG, outputs "H".
This SW is available to change the
generating position of clamp pulse for
input signal. (See Table 2.)
CLAMP
SW
2.2 V when
open
0.1 mA
28 kΩ
V
TH L = 0 to 1 V
VTH M = 1.6 to 2.8 V
TH H = 3.4 to 5 V
3.1 V
1.3 V
3
V
22 kΩ
20 kΩ 20 kΩ
4
GREEN
IN
2.8 V
when open
GREEN (SYNC ON VIDEO) input pin
Input with negative sync.
Comparison of pin 4 input signal and
reference voltage within the IC
performs synchronous separation.
1 kΩ
1 kΩ
3.5 V
4
5
6
GND
COMP/H
IN
Grounding
2.5 V
when open
Composite sync/H sync input pin.
Bias is approx. 2.5 V and impedance
is 10 kΩ.
1.5 kΩ
1.5 kΩ
20 kΩ
The internal double threshold
comparator is used for shaping
waveform and detecting polarity.
Optimum input amplitude is 0.6 VP-P
at pin 6. Up to approx. 50% of duty,
waveform shaping and polarity
detection can be done.
20 kΩ
6
10 kΩ
2.8 V
10 kΩ
2.5 V
10 kΩ
2.2 V
0.3 mA
0.3 mA
7
COMP/H
DET
2.5 V
when open
(no signal)
External capacitance is required as a
filter pin for detecting polarity and
detecting non-input. As the value is
larger, the ripple is smaller and less
malfunction occurs. However, this
lowers the response speed of
detection.
12 kΩ
12 kΩ
75 kΩ
7
2.5 V
2.2 V
2.8 V
20 kΩ
20 kΩ
8
9
V IN
2.5 V
Same as pin 6
Same as pin 7
V sync input pin
Same as pin 6
Same as pin 7
when open
V DET
2.5 V
when open
(no signal)
Rev.2.00 Sep 14, 2006 page 7 of 16
M52347SP/FP
Pin Description (cont.)
Pin
No.
DC Voltage
(V)
Name
Peripheral Circuit
Function
10
V.TIME
GATE SW
3.2 V
when open
V TIME GATE SW pin
Can select whether to output the pulse
of VD portion from pin 14, 15 output
pulse.
0.1 mA
2.5 V
10
The threshold voltage is approx. 2.5 V.
30 kΩ
VTH L = 0 to 2 V
20 kΩ
VTH H = 3 to 5 V
11
V S/S IN
V S/S IN pin
4 kΩ
Inputs a signal of having externally
integrated composite sync for V sync
separation.
0.1 mA
7.5 kΩ
11
1 kΩ
1 kΩ
5.5 kΩ
20 kΩ
1.75 kΩ
0.2 mA
0.2 mA
12
V S/S OUT
V S/S pulse output pin
1 kΩ
No problem occurs when current of
approx. 6 mA flows to internal part of
the IC. To improve the rising speed,
connect a resistance between power
supplies.
12
13
14
15
VD+OUT
HD+OUT
Same as pin 12
Same as pin 12
Same as pin 12
VD+ pulse output pin
Same as pin 12
HD+ pulse output pin
Same as pin 12
−
−
HD OUT
HD pulse output pin
Same as pin 12
16
17
VCC
5 V
Power supply
CLAMP+
OUT
Same as pin 12
CLAMP+ pulse output pin
Same as pin 12
18
19
20
H.POL.
0 VDC or
5 VDC
Same as pin 1
Logic output pin for horizontal
synchronous signal
When pin 6 input signal is POSI,
outputs "L"; when NON, outputs "L";
and when NEG, outputs "H".
Logic output pin for vertical
synchronous signal
When pin 8 input signal is POSI,
outputs "L"; when NON, outputs "L";
and when NEG, outputs "H".
V.POL.
0 VDC or
5 VDC
Same as pin 1
CLAMP
TIMING
CLAMP TIMING pin
3.0 V
1.9 V
The clamp pulse width is determined
depending on the external resistance
and capacitance. As the resistance
value and capacitance value are
larger, the clamp pulse width is wider.
4 kΩ
4 kΩ
3 V
1.9 V
20
0.2 mA
0.4 mA
Rev.2.00 Sep 14, 2006 page 8 of 16
M52347SP/FP
Table 1
Decorder Logic Output
Pin 6 Input
COMP/H
Pin 8 Input
V
Output Pin
1
2
18
19
POSI.
NEG.
NON.
NON
POSI.
NEG.
NON
POSI.
NEG.
NON
POSI.
NEG.
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
L
H
H
L
L
L
H
H
H
L
L
L
L
L
H
L
L
H
L
L
H
Table 2
Clamp Pulse Position
Input Signal
Pin 17 Output Signal
Pin 3 "M"
Pin 4
Pin 6
Pin 3 "H"
Pin 3 "L"
Ο
Ο
Χ
Χ
Ο
Ο
4 trailing edge
6 leading edge
6 leading edge
4 trailing edge
4 trailing edge
Χ
4 trailing edge
6 trailing edge
6 trailing edge
Table 3
Pin 4
Output Priority Order
Output Signal
Input Signal
Pin 6
Pin 3 "H" "L"
Pin 3 "M"
Pins 12, 14, 15, 17
Pin 8
Pins 12, 14, 15, 17
Pin 13
Pin 13
Ο
Ο
Ο
Ο
Χ
Χ
Χ
Χ
Χ
Ο
Χ
Ο
Χ
Ο
Χ
Ο
Χ
Χ
Ο
Ο
Χ
Χ
Ο
Ο
4
6
4
6
Χ
6
Χ
6
11
11
8
4
4
11
11
8
4
8
4
8
Χ
Χ
Χ
Χ
Χ
Χ
Χ
8
11
8
8
8
Table 4
Allowable Input Amplitude Voltage
Pin 4 input amplitude
VV 0 to 2.1 (VP-P
)
fH = 10 Hz to 200 kHz
)
fV = 10 Hz to 200 Hz
V
S 0.2 to 0.6 (VP-P
Pin 6 input amplitude
Pin 8 input amplitude
VS 0.5 to 2.5 (VP-P
)
fH = 10 Hz to 200 kHz
V
0.5 to 2.5 (VP-P)
S
fV = 10 Hz to 200 Hz
Rev.2.00 Sep 14, 2006 page 9 of 16
M52347SP/FP
Application Method
1. Input Block
1) GREEN (SYNC ON VIDEO) IN (Pin 4)
Input with sync negative polarity.
Comparison of pin 4 input signal and the reference voltage of the inside of the IC performs the synchronous
separation. When the input at pin 4 is less than or equal to the reference voltage (2.8 V) and the flowing current is
more than or equal to the input sensitivity current (200 µA or more), the signal is separated.
When only a synchronous signal is input into pin 4, the operatable amplitude and the duty are as shown in Figure 1.
If the IC does not operate normally with the video signal input, change the value of external resistance R to make
the current optimum.
But, when capacity value is too big, output response becomes bad.
2) COMP/H IN, VIN (pins 6 and 8)
The composite sync input is connected to pin 6. H and V of the separate sync input are connected to pins 6 and 8,
respectively. For each of pins 6 and 8, the bias is 2.5 V and the impedance is 10 k. The internal double threshold
converter is used for shaping waveform and for detecting polarity.
Average DC voltage of input signal is 2.5 V. Each threshold voltage is set at a voltage 0.3 V away from this voltage.
If the duty ratio at pin 6 is small as shown in Figure 2, the optimum value is approx. 0.3 VP-P. If the duty ratio is
large, the optimum value is approx. 0.6 VP-P. Figure 3 shows the allowable input amplitude and the reference value
of duty test.
Only 5 V TTL input, decrease the amplitude by resistor splitting.
In addition, Figure 4 shows an example for improving the capability of the allowable duty when the input amplitude
is 0.7 VP-P or more.
To use the IC out of the standard value, remove the filter from pins 7 and 9, observe the waveform and check for a
match with the waveform shown in Figure 5.
30
R = 56 kΩ
R = 75 kΩ
25
20
15
10
3.3 µ
4
f = 100 kHz
R
5
0
0
0.2
0.4
0.6
0.8
1.0
Input Amplitude (VP-P
)
Figure 1
≈ 2.8 V
≈ 2.5 V
≈ 2.2 V
Small POSI Duty
Large NEG Duty
Figure 2
Rev.2.00 Sep 14, 2006 page 10 of 16
M52347SP/FP
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
Input Amplitude (VP-P
)
Figure 3
18 kΩ
pin 6
or pin 8
Input signal
100 Ω
3 kΩ
This additional circuit (limiter) limits
the amplitude to 0.6 V
: 5 V
.
P-P
Figure 4
≈ 4.5 V
NEG input
≈ 2.5 V
≈ 2.5 V
POSI input
≈ 0.5 V
Figure 5
Rev.2.00 Sep 14, 2006 page 11 of 16
M52347SP/FP
3) Polarity detection and non-input detection (pins 7 and 8)
External capacitance is required as a filter pin to detect polarity and non-input. As the value is larger, the ripple is
smaller and less malfunction occurs. However, the response speed for detection is lower. A sufficient external
capacitance is 0.05 µF with input of 15 kHz and 10 µF with input of 60 kHz. However, check the frequency of the
input signal in use and the filter pin waveform with the duty ratio conditions, and then check that the value is 3.1 V
or more (2.8 V in capability) with positive polarity input and 1.9 V or less (2.2 V in capability) with negative
polarity input.
4) V S/S IN (pin 11)
Input a signal of having externally integrated composite sync for V sync separation.
Composite sync input into pin 6 is output to pin 12. Output at 12 is externally integrated and is input into pin 11 for
V sync separation. With the waveform at pin 11, check that the H element has been fully dropped.
The threshold levels of sync separation, given hysteresis, are 3.5 V and 1.8 V.
Input waveform at
pin 6
Waveform at
pin 11
VTH = 3.5 V
VTH = 1.8 V
Output waveform at
pin 13
2. Clamp Pulse
1) Clamp pulse width
CLAMP TIMING (Pin 20)
The clamp pulse width is determined by the external resistance and the capacitance. As the resistance value and
capacitance value are larger, the clamp pulse width is wider.
The time constant is determined by the current flowing out of pin 20 and the capacitance value of the timing pin.
The flow current at pin 20 is determined by the pin voltage and external resistance value. When the external
resistance is 4.3 (that is 700 µA) and the external capacitance is 220 pF, the pulse width is 0.4 µs.
2) Clamp pulse position
CLAMP SW (pin 3)
When pin 3 is "M" or "L", fixing a higher-priority signal to the trailing edge results in occurrence of a clamp pulse.
When pin 3 is "H", and only GREEN is input, clamp pulse occurs at the trailing edge. A clamp pulse also occurs at
the leading edge when COMP/H only is input or when both COMP/H and GREEN are input.
8
7
6
5
4
R = 10 kΩ
3
2
R = 4.3 kΩ
1
0
10
100
1000
10000
Clamp Timing Capacitance at Pin 20 (pF)
Rev.2.00 Sep 14, 2006 page 12 of 16
M52347SP/FP
3. Sampling Pulse from VD Portion
V TIME GATE SW (Pin 10)
Whether to output the pulse of VD portion from pins 14 and 15 can be selected. When pin 10 is "H" or OPEN, pulse of
the VD portion is output. When pin 10 is "L", the pulse of the VD portion is not output.
Output at pin 14 when pin 10 is "H" or OPEN
VD portion
Output at pin 14 when pin 10 is "L"
Output at pin 15 when pin 10 is "H" or OPEN
VD portion
Output at pin 15 when pin 10 is "L"
4. Output Stage
1) Logic output (pins 1, 2, 18 and 19)
The output format is as shown in the diagram below.
When the internal load resistance of the IC is 20 kΩ, a current of approx. 3 mA flows to the inside of the IC, no
problem will occur.
20 kΩ
2) Pulse output (pins 12, 13, 14, 15 and 17)
The output format is as shown in the diagram below.
When the internal load resistance of the IC is 1 kΩ, a current of approx. 6 mA flows to the inside of the IC, no
problem will occur.
To improve the rising speed, connect a resistance between power supplies. Note that the low level of the output
pulse goes up.
1 kΩ
Rev.2.00 Sep 14, 2006 page 13 of 16
M52347SP/FP
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
∞
External Resistance (kΩ)
Typical Characteristics
Thermal Derating (Maximum Rating)
1400
1237.6
1200
1000
SP
827.8
800
643.6
FP
600
400
200
0
430.5
−25
0
25 50 7585 100 125 150
Ambient Temperature Ta (°C)
Rev.2.00 Sep 14, 2006 page 14 of 16
M52347SP/FP
Application Example (fH = 50 kHz, fV = 80 Hz)
(POSI NON NEG)
(POSI NON NEG)
VCC 5 V
0.01 µ
43 k
100 p
220 p
+
4.3 k
47 µ
−
+
+
HD HD
OUT OUT
VD
OUT
CLAMP
TIMING
V S/S
OUT
V S/S
IN
+
CLAMP
OUT
H.POL.
18
V.POL.
20
19
17
16
15 14
13
12
11
V.TIME
GATE
EDGE
SW
CLAMP
GEN
V.SYNC
SEP
LOGIC
LOGIC
SYNC
SEP
H
SHAPE
H
DET
V
SHAPE
V
DET
1
2
3
4
5
6
7
8
9
10
+
COMP/H
DET
4.7 µ
CLAMP
SW
H.STATE V.STATE
V DET
V TIME GATE
SW
4.7 µ
+
0.068 µ
(POSI NON NEG)
(POSI NON NEG)
GND
1.0 µ
56 k
10
µ
H
M
H
L
4.7 µ
18 k
18 k
4.7 µ
L
0.01 µ
0.01 µ
100
100
3 k
3 k
: 5 V
Units Resistance: Ω
Capacitance: F
GREEN
IN
COMP/H
IN
V IN
Note: External circuit for input of pins 6 and 8
When amplitude of up to 5 VP-P is entered into this circuit, can be kept constant at approx. 0.6 VP-P
When the duty of input signal at pins 6 and 8 changes, the most broad support range is obtained
with amplitude of 0.6 VP-P
.
.
Rev.2.00 Sep 14, 2006 page 15 of 16
M52347SP/FP
Package Dimensions
JEITA Package Code
P-SDIP20-6.3x19-1.78
RENESAS Code
PRDP0020BA-A
Previous Code
20P4B
MASS[Typ.]
1.0g
20
11
1
10
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
*2
D
Dimension in Millimeters
Reference
Symbol
Min Nom Max
e1
D
7.32 7.62 7.92
18.8 19.0 19.2
6.15 6.3 6.45
4.5
E
A
A1
A2
bp
b3
c
0.51
*3
b3
bp
e
3.3
SEATING PLANE
0.38 0.48 0.58
0.9 1.0 1.3
0.22 0.27 0.34
0°
15°
e
L
1.528 1.778 2.028
3.0
JEITA Package Code
RENESAS Code
PRSP0020DA-A
Previous Code
20P2N-A
MASS[Typ.]
0.3g
P-SOP20-5.3x12.6-1.27
20
11
F
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
10
Index mark
*2
A2
A1
D
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
E
12.5 12.6 12.7
5.2 5.3 5.4
1.8
A2
A1
A
*3
bp
0
0.1 0.2
2.1
e
y
Detail F
bp
c
0.35 0.4 0.5
0.18 0.2 0.25
0°
8°
HE
e
7.5 7.8 8.1
1.12 1.27 1.42
0.1
y
L
0.4 0.6 0.8
Rev.2.00 Sep 14, 2006 page 16 of 16
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