ISL83483IB-T [RENESAS]
LINE TRANSCEIVER, PDSO8, PLASTIC, MS-012AA, SOIC-8;
| 型号： | ISL83483IB-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | LINE TRANSCEIVER, PDSO8, PLASTIC, MS-012AA, SOIC-8 驱动 信息通信管理 光电二极管 接口集成电路 驱动器 |
| 文件： | 总19页 (文件大小：965K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
3.3V, Low Power, High Speed or Slew Rate Limited, RS-485/RS-422 Transceivers
FN6052
Rev.5.00
Nov 21, 2018
These Renesas RS-485/RS-422 devices are BiCMOS 3.3V
powered, single transceivers that meet both the RS-485 and
Features
• Operate from a single +3.3V supply (10% tolerance)
• Interoperable with 5V logic
RS-422 standards for balanced communication. Unlike
competitive devices, this Renesas family is specified for 10%
tolerance supplies (3V to 3.6V).
• High data rates. . . . . . . . . . . . . . . . . . . . . . up to 10Mbps
• Single unit load allows up to 32 devices on the bus
The ISL83483 and ISL83488 use slew rate limited drivers
which reduce EMI, and minimize reflections from improperly
terminated transmission lines, or unterminated stubs in
multidrop and multipoint applications.
• Slew rate limited versions for error free data transmission
(ISL83483, ISL83488) . . . . . . . . . . . . . . . . .up to 250kbps
• Low current Shutdown mode (ISL83483, ISL83485,
ISL83491). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15nA
Data rates up to 10Mbps are achievable by using the
ISL83485, ISL83490, or ISL83491, which feature higher
slew rates.
• -7V to +12V common-mode input voltage range
• Three-state Rx and Tx outputs (except ISL83488,
ISL83490)
Logic inputs (for example, DI and DE) accept signals in
excess of 5.5V, making them compatible with 5V logic
families.
• 10ns propagation delay, 1ns skew (ISL83485, ISL83490,
ISL83491)
Receiver (Rx) inputs feature a “fail-safe if open” design,
which ensures a logic high output if Rx inputs are floating. All
devices present a “single unit load” to the RS-485 bus, which
allows up to 32 transceivers on the network.
• Full duplex and half duplex pinouts
• Current limiting and thermal shutdown for driver overload
protection
Driver (Tx) outputs are short-circuit protected, even for
voltages exceeding the power supply voltage. Additionally,
on-chip thermal shutdown circuitry disables the Tx outputs to
prevent damage if power dissipation becomes excessive.
• Pb-free (RoHS compliant)
Applications
• Factory automation
The ISL83488, ISL83490, and ISL83491 are configured for
full duplex (separate Rx input and Tx output pins)
applications. The ISL83488 and ISL83490 are offered in
space saving 8 Ld packages for applications not requiring Rx
and Tx output disable functions (for example, point-to-point
and RS-422). Half duplex configurations (ISL83483,
ISL83485) multiplex the Rx inputs and Tx outputs to provide
transceivers with Rx and Tx disable functions in 8 Ld
packages.
• Security networks
• Building environmental control systems
• Industrial/process control networks
• Level translators (for example, RS-232 to RS-422)
• RS-232 “Extension Cords”
Related Literature
For a full list of related documents, visit our website:
• ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
device pages
TABLE 1. SUMMARY OF FEATURES
SLEW-RATE RECEIVER/DRIVER QUIESCENT I
PART
NUMBER
HALF/FULL
DUPLEX
DATA RATE
(Mbps)
LOW POWER
SHUTDOWN?
CC
LIMITED?
ENABLE?
(mA)
0.65
0.65
0.65
0.65
0.65
PIN COUNT
ISL83483
ISL83485
ISL83488
ISL83490
ISL83491
Half
Half
Full
Full
Full
0.25
10
Yes
No
Yes
Yes
Yes
No
8
8
Yes
0.25
10
Yes
No
No
8
No
No
8
10
No
Yes
Yes
14
FN6052 Rev.5.00
Nov 21, 2018
Page 1 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
TAPE AND REEL
PKG.
DWG. #
MARKING TEMP. RANGE (°C) (UNITS) (Note 1)
PACKAGE
ISL83483IBZ
83483 IBZ
83483 IBZ
83483 IBZ
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-
2.5k
250
-
8 Ld SOIC (RoHS compliant) M8.15
8 Ld SOIC (RoHS compliant) M8.15
8 Ld SOIC (RoHS compliant) M8.15
ISL83483IBZ-T
ISL83483IBZ-T7A
ISL83483IP (No longer available or supported) ISL 83483IP
8 Ld PDIP
E8.3
ISL83485IBZ
83485 IBZ
83485 IBZ
83485 IBZ
83488 IBZ
83488 IBZ
83490 IBZ
83490 IBZ
83491IBZ
83491IBZ
83491IBZ
-
8 Ld SOIC (RoHS compliant) M8.15
8 Ld SOIC (RoHS compliant) M8.15
8 Ld SOIC (RoHS compliant) M8.15
8 Ld SOIC (RoHS compliant) M8.15
8 Ld SOIC (RoHS compliant) M8.15
8 Ld SOIC (RoHS compliant) M8.15
8 Ld SOIC (RoHS compliant) M8.15
14 Ld SOIC (RoHS compliant) M14.15
14 Ld SOIC (RoHS compliant) M14.15
14 Ld SOIC (RoHS compliant) M14.15
ISL83485IBZ-T
ISL83485IBZ-T7A
ISL83488IBZ
2.5k
250
-
ISL83488IBZ-T
ISL83490IBZ
2.5k
-
ISL83490IBZ-T
ISL83491IBZ
2.5k
-
ISL83491IBZ-T
ISL83491IBZ-T7A
2.5k
250
-
ISL83491IP (No longer available, recommended ISL83491IP
replacement: ISL83491IBZ)
14 Ld PDIP
E14.3
NOTES:
1. Refer to TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), refer to the ISL83483, ISL83485, ISL83488, ISL83490, and ISL83491 device pages. For more information
about MSL, refer to TB363.
FN6052 Rev.5.00
Nov 21, 2018
Page 2 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
Pinouts
ISL83483, ISL83485 (PDIP, SOIC)
ISL83488, ISL83490 (SOIC)
ISL83491 (PDIP, SOIC)
TOP VIEW
TOP VIEW
TOP VIEW
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
CC
V
1
2
3
4
8
7
6
5
A
B
Z
NC
RO
1
2
3
4
5
6
7
14 V
13 V
CC
CC
R
D
R
B/Z
RO
DI
CC
R
D
A/Y
RE
12 A
11 B
10 Z
D
GND
GND
Y
DE
DI
GND
GND
9
8
Y
NC
NOTE: PDIP packages are no longer supported
Truth Tables
TRANSMITTING
RECEIVING
INPUTS
INPUTS
OUTPUTS
OUTPUT
RE
X
DE
1
DI
1
Z
0
1
Y
RE
DE
DE
A-B
RO
Half Duplex Full Duplex
1
0
0
0
1
1
0
0
0
0
1
X
X
X
0
≥ +0.2V
≤ -0.2V
1
0
X
1
0
0
0
0
X
X
High-Z
High-Z
High-Z *
Inputs Open
1
1
0
High-Z *
X
X
High-Z *
High-Z
NOTE: *Shutdown Mode for ISL83483, ISL83485, ISL83491
1
NOTE: *Shutdown Mode for ISL83483, ISL83485, ISL83491
Pin Descriptions
PIN
FUNCTION
RO
RE
DE
DI
Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating).
Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high.
Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low.
Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low.
GND
A/Y
B/Z
A
Ground connection.
Noninverting receiver input and noninverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1.
Inverting receiver input and inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1.
Noninverting receiver input.
Inverting receiver input.
B
Y
Noninverting driver output.
Inverting driver output.
Z
V
System power supply input (3V to 3.6V).
No Connection.
CC
NC
FN6052 Rev.5.00
Nov 21, 2018
Page 3 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
Typical Operating Circuits
For calculating the resistor values refer to TB509, “Detecting Bus Signals Correctly with Failsafe Biased RS-485 Receivers”
3.3V
3.3V
100nF
100nF
8
8
R
PU
R
PU
V
CC
V
CC
R
R
R
B
1
2
3
4
RO
RE
DE
DI
RO
RE
DE
DI
1
2
3
4
A/Y
B/Z
6
7
6
7
A/Y
B/Z
V
FS
R
T1
T2
B
GND
5
GND
5
FIGURE 1. ISL83483, ISL83485
3.3V
1
3.3V
1
100nF
100nF
V
V
CC
CC
A
8
5
Y
2
RO
DI
DI
3
R
T
B
Z
7
6
6
7
Z
B
3
RO 2
R
T
Y
5
8
A
GND
4
GND
4
FIGURE 2. ISL83488, ISL83490
3.3V
3.3V
100nF
100nF
13, 14
13,14
R
R
R
B
B
T
R
PU
R
PU
V
V
CC
CC
A
12
9
Y
2
RO
RE
DI
5
3
4
5
B
Z
11
10
10
11
Z
DE
4
DE
DI
B
RE
RO
3
2
R
T
Y
9
12
A
GND
6, 7
GND
6, 7
R
R
B
B
FIGURE 3. ISL83491
FN6052 Rev.5.00
Nov 21, 2018
Page 4 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
Absolute Maximum Ratings
Thermal Information
V
to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Thermal Resistance (Typical, Note 4)
θJA (°C/W)
CC
Input Voltages
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
8 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . .
14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
14 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile (SOIC only). . . . . . . . . . . . . . . . . see TB493
170
140
130
105
DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input/Output Voltages
A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V
RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (V
Short-Circuit Duration
+0.5V)
CC
Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range
ISL834xxIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
4. θ is measured with the component mounted on a low-effective thermal conductivity test board in free air. See TB379.
JA
Electrical Specifications Test conditions: V = 3V to 3.6V; unless otherwise specified. Typicals are at V
= 3.3V, T = +25°C,
A
CC
CC
Note 5.
TEMP
PARAMETER
SYMBOL
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNIT
DC CHARACTERISTICS
Driver Differential V
Driver Differential V
(no load)
V
V
Full
Full
Full
Full
Full
-
2
-
V
V
V
V
V
V
V
OUT
OD1
OD2
CC
-
(with load)
R
R
R
R
= 100Ω (RS-422) (Figure 4A)
= 54Ω (RS-485) (Figure 4A)
2.7
2.3
2.6
0.01
OUT
L
L
L
L
1.5
1.5
-
CC
-
= 60Ω, -7V ≤ V
CM
≤ 12V (Figure 4B)
Change in Magnitude of Driver
Differential V for
ΔV
= 54Ω or 100Ω (Figure 4A)
0.2
OD
OUT
Complementary Output States
Driver Common-Mode V
V
R
R
= 54Ω or 100Ω (Figure 4A)
= 54Ω or 100Ω (Figure 4A)
Full
Full
-
-
1.8
3
V
V
OUT
Change in Magnitude of Driver
Common-Mode V for
OC
L
ΔV
0.01
0.2
OC
L
OUT
Complementary Output States
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
V
DE, DI, RE
DE, DI, RE
DE, DI
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
2
-
-
-
-
0.8
2
V
V
IH
V
IL
I
-2
-25
-
-
µA
µA
mA
mA
µA
µA
µA
µA
V
IN1
IN2
IN3
IN3
RE
-
25
1
Input Current (A, B)
I
I
I
DE = 0V, V
= 0V or 3.6V
V
V
V
V
= 12V
= -7V
= 12V
= -7V
0.6
-0.3
14
-11
0.03
-0.01
-
CC
IN
IN
IN
IN
-
-0.8
20
-
Output Leakage Current (Y, Z)
(ISL83491)
RE = 0V, DE = 0V, V
= 0V or 3.6V
-
CC
-20
-
Output Leakage Current (Y, Z)
in Shutdown Mode (ISL83491)
RE = V , DE = 0V, V
CC
= 0V or 3.6V V = 12V
IN
1
CC
V
= -7V
-1
-0.2
-
IN
Receiver Differential Threshold
Voltage
V
-7V ≤ V
≤ 12V
0.2
TH
CM
Receiver Input Hysteresis
ΔV
V
= 0V
+25
Full
-
50
-
-
-
mV
V
TH
CM
Receiver Output High Voltage
V
I
= -4mA, V = 200mV
ID
V
-
OH
O
CC
0.4
Receiver Output Low Voltage
V
I
= -4mA, V = 200mV
ID
Full
-
-
0.4
V
OL
O
FN6052 Rev.5.00
Nov 21, 2018
Page 5 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
Electrical Specifications Test conditions: V = 3V to 3.6V; unless otherwise specified. Typicals are at V
= 3.3V, T = +25°C,
A
CC
CC
Note 5. (Continued)
TEMP
PARAMETER
SYMBOL
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNIT
Three-State (high impedance)
Receiver Output Current
I
0.4V ≤ V ≤ 2.4V
Full
-1
-
1
µA
OZR
O
Receiver Input Resistance
R
-7V ≤ V
≤ 12V
Full
Full
12
-
19
-
kΩ
IN
CM
No-Load Supply Current (Note 6)
I
DI = 0V or V
DE = V
,
0.75
1.2
mA
CC
CC
CC
RE = 0V
or V
CC
DE = 0V,
RE = 0V
Full
Full
Full
Full
-
-
0.65
1
mA
nA
Shutdown Supply Current
I
DE = 0V, RE = V , DI = 0V or V
CC
15
-
100
250
60
SHDN
CC
(Except ISL83488 and ISL83490)
Driver Short-Circuit Current,
I
DE = V , -7V ≤ V or V ≤ 12V (Note 7)
CC
-
mA
mA
OSD1
Y
Z
V
= High or Low
O
Receiver Short-Circuit Current
I
0V ≤ V ≤ V
8
-
OSR
O
CC
DRIVER SWITCHING CHARACTERISTICS (ISL83485, ISL83490, ISL83491)
Maximum Data Rate
f
Full
Full
Full
Full
Full
Full
12
1
3
6
-
15
10
5
-
Mbps
ns
MAX
Driver Differential Output Delay
Driver Differential Rise or Fall Time
Driver Input to Output Delay
Driver Output Skew
t
R
R
R
R
R
= 60Ω, C = 15pF (Figure 5A)
35
20
35
8
DD
DIFF
L
t , t
= 60Ω, C = 15pF (Figure 5A)
ns
R
F
DIFF
L
t
, t
PLH PHL
= 27Ω, C = 15pF (Figure 5C)
10
1
ns
L
L
L
L
t
= 27Ω, C = 15pF (Figure 5C)
ns
SKEW
L
Driver Enable to Output High
(Except ISL83490)
t
t
= 110Ω, C = 50pF, SW = GND (Figure 6),
-
45
90
ns
ZH
L
(Note 8)
= 110Ω, C = 50pF, SW = V (Figure 6),
CC
Driver Enable to Output Low
(Except ISL83490)
t
R
Full
-
45
90
ns
ZL
L
L
(Note 8)
Driver Disable from Output High
(Except ISL83490)
R
R
R
= 110Ω, C = 50pF, SW = GND (Figure 6)
+25
Full
+25
Full
Full
-
-
-
-
-
65
-
80
110
80
ns
ns
ns
ns
ns
HZ
L
L
L
L
Driver Disable from Output Low
(Except ISL83490)
t
= 110Ω, C = 50pF, SW = V (Figure 6)
CC
65
-
LZ
L
110
150
Driver Enable from Shutdown to
Output High (Except ISL83490)
t
= 110Ω, C = 50pF, SW = GND (Figure 6),
115
ZH(SHDN)
L
(Notes 10, 11)
= 110Ω, C = 50pF, SW = V (Figure 6),
CC
Driver Enable from Shutdown to
Output Low (Except ISL83490)
t
R
Full
-
115
150
ns
ZL(SHDN)
L
L
(Notes 10, 11)
DRIVER SWITCHING CHARACTERISTICS (ISL83483, ISL83488)
Maximum Data Rate
f
Full
Full
Full
+25
Full
Full
Full
250
600
400
600
400
-
-
-
kbps
ns
MAX
Driver Differential Output Delay
Driver Differential Rise or Fall Time
Driver Input to Output Delay
t
R
R
R
= 60Ω, C = 15pF (Figure 5A)
930
900
930
-
1400
1200
1500
1500
-
DD
DIFF
L
t , t
= 60Ω, C = 15pF (Figure 5A)
ns
R
F
DIFF
L
t
, t
PLH PHL
= 27Ω, C = 15pF (Figure 5C)
ns
L
L
ns
Driver Output Skew
t
R
R
= 27Ω, C = 15pF (Figure 5C)
140
385
ns
SKEW
L
L
Driver Enable to Output High
(Except ISL83488)
t
t
= 110Ω, C = 50pF, SW = GND (Figure 6),
-
800
ns
ZH
L
L
(Note 8)
= 110Ω, C = 50pF, SW = V (Figure 6),
CC
Driver Enable to Output Low
(Except ISL83488)
t
R
Full
-
55
800
ns
ZL
L
L
(Note 8)
Driver Disable from Output High
(Except ISL83488)
R
= 110Ω, C = 50pF, SW = GND (Figure 6)
+25
Full
-
-
63
-
80
ns
ns
HZ
L
L
110
FN6052 Rev.5.00
Nov 21, 2018
Page 6 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
Electrical Specifications Test conditions: V = 3V to 3.6V; unless otherwise specified. Typicals are at V
= 3.3V, T = +25°C,
A
CC
CC
Note 5. (Continued)
TEMP
PARAMETER
SYMBOL
TEST CONDITIONS
= 110Ω, C = 50pF, SW = V (Figure 6)
(°C)
+25
Full
MIN
TYP
70
MAX
80
UNIT
ns
Driver Disable from Output Low
(Except ISL83488)
t
R
-
-
-
LZ
L
L
CC
-
110
2000
ns
Driver Enable from Shutdown to
Output High (Except ISL83488)
t
R
R
= 110Ω, C = 50pF, SW = GND (Notes 10, 11) Full
450
ns
ZH(SHDN)
L
L
Driver Enable from Shutdown to
Output Low (Except ISL83488)
t
= 110Ω, C = 50pF, SW = V (Figure 6),
CC
Full
-
126
2000
ns
ZL(SHDN)
L
L
(Notes 10, 11)
RECEIVER SWITCHING CHARACTERISTICS (All Versions)
Receiver Input to Output Delay
Receiver Skew | t - t
t
, t
PLH PHL
(Figure 7)
(Figure 7)
Full
+25
Full
Full
25
-
45
2
90
10
12
50
ns
ns
ns
ns
|
t
SKD
PLH PHL
-
2
Receiver Enable to Output High
(Except ISL83488 and ISL83490)
t
t
R
= 1kΩ, C = 15pF, SW = GND (Figure 8),
-
11
ZH
L
L
(Note 9)
= 1kΩ, C = 15pF, SW = V (Figure 8),
CC
Receiver Enable to Output Low
(Except ISL83488 and ISL83490)
t
R
Full
Full
Full
Full
Full
-
-
11
7
50
45
ns
ns
ns
ns
ns
ZL
L
L
(Note 9)
Receiver Disable from Output High
(Except ISL83488 and ISL83490)
R
= 1kΩ, C = 15pF, SW = GND (Figure 8)
L
HZ
L
L
Receiver Disable from Output Low
(Except ISL83488 and ISL83490)
t
R
= 1kΩ, C = 15pF, SW = V (Figure 8)
CC
-
7
45
LZ
L
Time to Shutdown
(Except ISL83488 and ISL83490)
t
(Note 10)
80
-
190
240
300
600
SHDN
Receiver Enable from Shutdown to
Output High
t
R = 1kΩ, C = 15pF, SW = GND (Figure 8),
L L
(Notes 10, 11)
ZH(SHDN)
(Except ISL83488 and ISL83490)
Receiver Enable from Shutdown to
Output Low
t
R
= 1kΩ, C = 15pF, SW = V (Figure 8),
CC
Full
-
240
600
ns
ZL(SHDN)
L
L
(Notes 10, 11)
(Except ISL83488 and ISL83490)
NOTES:
5. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
6. Supply current specification is valid for loaded drivers when DE = 0V.
7. Applies to peak current. See “Typical Performance Curves” on page 11 for more information.
8. When testing the ISL83483, ISL83485, and ISL83491, keep RE = 0 to prevent the device from entering SHDN.
9. When testing the ISL83483, ISL83485, and ISL83491, the RE signal high time must be short enough (typically <100ns) to prevent the device
from entering SHDN.
10. The ISL83483, ISL83485, and ISL83491 are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 80ns,
the parts are ensured not to enter shutdown. If the inputs are in this state for at least 300ns, the parts are ensured to have entered shutdown.
See “Low Power Shutdown Mode (ISL83483, ISL83485, ISL83491 Only)” on page 11.
11. Keep RE = VCC, and set the DE signal low time >300ns to ensure that the device enters SHDN.
12. Set the RE signal high time >300ns to ensure that the device enters SHDN.
FN6052 Rev.5.00
Nov 21, 2018
Page 7 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
Test Circuits and Waveforms
R /2
L
375Ω
DE
DI
DE
DI
V
V
CC
CC
Z
Y
Z
Y
V
CM
R
= 60Ω
V
V
OD
L
D
D
OD
-7V to +12V
V
R /2
L
375Ω
OC
FIGURE 4B. V
WITH COMMON MODE LOAD
FIGURE 4A. V
AND V
OC
OD
OD
FIGURE 4. DC DRIVER TEST CIRCUITS
3V
DI
1.5V
PLH
1.5V
C
= 15pF
= 15pF
L
DE
0V
3V
Z
t
t
t
DI
PHL
R
= 60Ω
DIFF
D
Y
V
OH
C
L
50%
50%
50%
OUT (Y)
SIGNAL
GENERATOR
V
OL
t
PHL
PLH
V
OH
FIGURE 5A. DIFFERENTIAL TEST CIRCUIT
OUT
OUT (Z)
50%
50%
V
OL
t
t
DD
DD
DE
3V
+V
-V
OD
90%
90%
DIFF OUT (Y - Z)
Z
50%
10%
R
= 27Ω
L
DI
10%
V
D
OM
OD
Y
t
t
R
F
C
= 15pF
L
SKEW = |t
PLH
(Y or Z) - t
(Z or Y)|
PHL
SIGNAL
GENERATOR
V
+ V
2
OH
OL
V
=
≈1.5V
OM
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
FIGURE 5C. SINGLE ENDED TEST CIRCUIT
FN6052 Rev.5.00
Nov 21, 2018
Page 8 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
Test Circuits and Waveforms (Continued)
DE
Z
Y
110Ω
V
DI
CC
3V
0V
D
GND
DE
1.5V
1.5V
HZ
SW
= 50pF
SIGNAL
GENERATOR
Note 10
C
L
t
, t
ZH ZH(SHDN)
t
OUTPUT HIGH
50%
Note 10
V
OH
V
- 0.25V
OH
PARAMETER
OUTPUT
Y/Z
RE
X
DI
SW
OUT (Y, Z)
t
t
t
t
t
t
1/0
0/1
1/0
0/1
1/0
0/1
GND
0V
HZ
Y/Z
X
V
LZ
CC
t
, t
ZL ZL(SHDN)
t
LZ
Note 10
Y/Z
0 (Note 8)
0 (Note 8)
1 (Note 11)
1 (Note 11)
GND
ZH
V
CC
OUT (Y, Z)
50%
Y/Z
V
ZL
CC
V
+ 0.25V
V
OL
OL
Y/Z
GND
ZH(SHDN)
ZL(SHDN)
OUTPUT LOW
Y/Z
V
CC
FIGURE 6B. MEASUREMENT POINTS
FIGURE 6A. TEST CIRCUIT
FIGURE 6. DRIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490)
RE
3V
0V
GND
+1.5V
15pF
A
B
A
1.5V
PLH
1.5V
PHL
RO
R
t
t
V
SIGNAL
GENERATOR
CC
50%
50%
RO
0V
FIGURE 7A. TEST CIRCUIT
FIGURE 7B. MEASUREMENT POINTS
FIGURE 7. RECEIVER PROPAGATION DELAY
RE
B
1kΩ
V
Note 10
GND
CC
RO
R
3V
0V
A
GND
SW
SIGNAL
RE
1.5V
1.5V
HZ
GENERATOR
15pF
t
, t
ZH ZH(SHDN)
Note 10
t
OUTPUT HIGH
1.5V
V
OH
V
- 0.25V
PARAMETER
DE
A
SW
GND
OH
RO
t
t
t
t
t
t
0
+1.5V
-1.5V
+1.5V
-1.5V
+1.5V
-1.5V
HZ
LZ
ZH
ZL
0V
0
0
0
0
0
V
CC
t
, t
ZL ZL(SHDN)
t
LZ
(Note 9)
(Note 9)
GND
Note 10
V
CC
OL
V
CC
RO
1.5V
(Note 12)
(Note 12)
GND
V
+ 0.25V
V
ZH(SHDN)
ZL(SHDN)
OL
OUTPUT LOW
V
CC
FIGURE 8A. TEST CIRCUIT
FIGURE 8B. MEASUREMENT POINTS
FIGURE 8. RECEIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490)
FN6052 Rev.5.00
Nov 21, 2018
Page 9 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
faster output transition times allow data rates of at least
10Mbps.
Application Information
RS-485 and RS-422 are differential (balanced) data
transmission standards for use in long haul or noisy
Data Rate, Cables, and Terminations
environments. RS-422 is a subset of RS-485, so RS-485
transceivers are also RS-422 compliant. RS-422 is a
point-to-multipoint (multidrop) standard, which allows only one
driver and up to 10 (assuming one unit load devices) receivers
on each bus. RS-485 is a true multipoint standard, which
allows up to 32 one unit load devices (any combination of
drivers and receivers) on each bus. To allow for multipoint
operation, the RS-485 specification requires that drivers must
handle bus contention without sustaining any damage.
RS-485 and RS-422 are intended for network lengths up to
4000’, but the maximum system data rate decreases as the
transmission length increases. Devices operating at 10Mbps
are limited to lengths of a few hundred feet, while the 250kbps
versions can operate at full data rates with lengths in excess of
1000’.
Twisted pair is the cable of choice for RS-485 and RS-422
networks. Twisted pair cables tend to pick up noise and other
electromagnetically induced voltages as common-mode
signals, which are effectively rejected by the differential
receivers in these ICs.
Another important advantage of RS-485 is the extended
Common-Mode Range (CMR), which specifies that the driver
outputs and receiver inputs withstand signals that range from
+12V to -7V. RS-422 and RS-485 are intended for runs as long
as 4000’, so the wide CMR is necessary to handle ground
potential differences, as well as voltages induced in the cable
by external fields.
Proper termination is imperative, when using the 10Mbps
devices, to minimize reflections. Short networks using the
250kbps versions need not be terminated, but, terminations
are recommended unless power dissipation is an overriding
concern.
Receiver Features
In point-to-point, or point-to-multipoint (single driver on bus)
networks, the main cable should be terminated in its
characteristic impedance (typically 120Ω) at the end farthest
from the driver. In multi-receiver applications, stubs connecting
receivers to the main cable should be kept as short as
possible. Multipoint (multi-driver) systems require that the main
cable be terminated in its characteristic impedance at both
ends. Stubs connecting a transceiver to the main cable should
be kept as short as possible.
These devices use a differential input receiver for maximum
noise immunity and common-mode rejection. Input sensitivity is
±200mV, as required by the RS422 and RS-485 specifications.
Receiver input impedance surpasses the RS-422 spec of 4kΩ,
and meets the RS-485 “Unit Load” requirement of 12kΩ
minimum.
Receiver inputs function with common-mode voltages as great
as +9V/-7V outside the power supplies (that is, +12V and -7V),
making them ideal for long networks where induced voltages
are a realistic concern.
Built-In Driver Overload Protection
As stated previously, the RS-485 specification requires that
drivers survive worst case bus contentions undamaged. The
ISL834xx devices meet this requirement through driver output
short-circuit current limits, and on-chip thermal shutdown
circuitry.
All the receivers include a “fail-safe if open” function that
ensures a high level receiver output if the receiver inputs are
unconnected (floating).
Receivers easily meet the data rates supported by the
corresponding driver.
The driver output stages incorporate short-circuit current
limiting circuitry, which ensures that the output current never
exceeds the RS-485 specification, even at the common-mode
voltage range extremes. Additionally, these devices use a
foldback circuit which reduces the short-circuit current, and
thus the power dissipation, whenever the contending voltage
exceeds either supply.
ISL83483, ISL83485, ISL83491 receiver outputs are tri-statable
using the active low RE input.
Driver Features
The RS-485, RS-422 driver is a differential output device that
delivers at least 1.5V across a 54Ω load (RS-485), and at least
2V across a 100Ω load (RS-422) even with V
drivers feature low propagation delay skew to maximize bit
width, and to minimize EMI.
= 3V. The
In the event of a major short-circuit condition, the ISL834xx
devices also include a thermal shutdown feature that disables
the drivers whenever the die temperature becomes excessive.
This eliminates the power dissipation, allowing the die to cool.
The drivers automatically re-enable after the die temperature
drops about 15°. If the contention persists, the thermal
shutdown/re-enable cycle repeats until the fault is cleared.
Receivers stay operational during thermal shutdown.
CC
Drivers of the ISL83483, ISL83485, and ISL83491 are
tri-statable using the active high DE input.
ISL83483 and ISL83488 driver outputs are slew rate limited to
minimize EMI, and to minimize reflections in unterminated or
improperly terminated networks. Data rate on these slew rate
limited versions is a maximum of 250kbps. Outputs of
ISL83485, ISL83490, and ISL83491 drivers are not limited, so
FN6052 Rev.5.00
Nov 21, 2018
Page 10 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
period of at least 300ns. Disabling both the driver and the
receiver for less than 80ns ensures that shutdown is not
entered.
Low Power Shutdown Mode (ISL83483, ISL83485,
ISL83491 Only)
These CMOS transceivers all use a fraction of the power
required by their bipolar counterparts, but the ISL83483,
ISL83485, and ISL83491 include a shutdown feature that
Note that receiver and driver enable times increase when
these devices enable from shutdown. For more information
refer to Notes 8 through 12 on page 7 at the end of the
Electrical Specification table.
reduces the already low quiescent I
to a 15nA trickle. They
CC
enter shutdown whenever the receiver and driver are
simultaneously disabled (RE = V and DE = GND) for a
CC
Typical Performance Curves
V
= 3.3V, T = +25°C, ISL83483 thru ISL83491; Unless otherwise specified
A
CC
110
100
90
80
70
60
50
40
30
20
10
0
2.9
2.8
R
= 100Ω
DIFF
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
R
= 54Ω
DIFF
-40
0
50
85
0
0.5
1
1.5
2
2.5
3
3.5
-25
25
75
DIFFERENTIAL OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 9. DRIVER OUTPUT CURRENT vs DIFFERENTIAL
OUTPUT VOLTAGE
FIGURE 10. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs
TEMPERATURE
160
140
120
800
ISL83483/85, DE = V , RE = X
CC
Y OR Z = LOW
100
750
700
650
600
80
60
40
20
0
ISL83483/85, DE = RE = GND; ISL83491, DE = X, RE = GND;
ISL83488/90
-20
Y OR Z = HIGH
-40
-60
-80
-100
-120
-40
0
50
85
-25
25
75
-7 -6
-4
-2
0
2
4
6
8
10
12
OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 11. DRIVER OUTPUT CURRENT vs SHORT-CIRCUIT
VOLTAGE
FIGURE 12. SUPPLY CURRENT vs TEMPERATURE
FN6052 Rev.5.00
Nov 21, 2018
Page 11 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
Typical Performance Curves
V
= 3.3V, T = +25°C, ISL83483 thru ISL83491; Unless otherwise specified (Continued)
CC
A
1200
300
R
= 54Ω
DIFF
R
= 54Ω
DIFF
Figure 5A
|t
- t
|
PHLY PLHZ
250
200
150
100
50
1100
1000
900
t
PLHZ
|t
- t
|
t
PLHY PHLZ
PLHY
t
PHLY
t
PHLZ
800
|CROSS PT. OF Y↑ & Z↓ - CROSS PT. OF Y↓ & Z↑|
0
-40
700
-40
0
50
85
0
50
85
-25
25
75
-25
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 13. DRIVER PROPAGATION DELAY vs
FIGURE 14. DRIVER SKEW vs TEMPERATURE
(ISL83483, ISL83488)
TEMPERATURE (ISL83483, ISL83488)
16
15
14
13
12
11
10
9
4
R
= 54Ω
R
= 54Ω
DIFF
DIFF
Figure 5A
3.5
3
|t |
- t
PHLY PLHZ
t
PLHZ
2.5
2
t
PLHY
t
PHLY
1.5
1
|CROSSING PT. OF Y↑ & Z↓ -
CROSSING PT. OF Y↓ & Z↑|
t
PHLY
-25
t
PHLZ
25
|t
- t |
PLHY PHLZ
8
0.5
-40
-40
0
50
85
75
0
50
85
-25
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 15. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL83485, ISL83490, ISL83491)
FIGURE 16. DRIVER SKEW vs TEMPERATURE
(ISL83485, ISL84390, ISL83491)
R
= 54Ω, C = 15pF
L
R
= 54Ω, C = 15pF
L
DIFF
DIFF
5
0
5
0
DI
DI
5
0
5
0
RO
RO
3
3
2.5
2
2.5
2
B/Z
A/Y
1.5
1
1.5
1
A/Y
B/Z
0.5
0
0.5
0
TIME (400ns/DIV)
TIME (400ns/DIV)
FIGURE 17. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL83483, ISL83488)
FIGURE 18. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL83483, ISL83488)
FN6052 Rev.5.00
Nov 21, 2018
Page 12 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
Typical Performance Curves
V
= 3.3V, T = +25°C, ISL83483 thru ISL83491; Unless otherwise specified (Continued)
CC A
R
= 54Ω, C = 15pF
L
R
= 54Ω, C = 15pF
L
DIFF
DIFF
5
0
5
0
DI
DI
5
0
5
0
RO
RO
3
3
2.5
2
2.5
2
A/Y
B/Z
B/Z
A/Y
1.5
1
1.5
1
0.5
0
0.5
0
TIME (10ns/DIV)
TIME (10ns/DIV)
FIGURE 19. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL83485, ISL83490, ISL83491)
FIGURE 20. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL83485, ISL83490, ISL83491)
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
528
PROCESS:
Si Gate CMOS
FN6052 Rev.5.00
Nov 21, 2018
Page 13 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please
visit our website to make sure you have the latest revision.
DATE
REVISION
FN6052.5
CHANGE
Nov 21, 2018
Updated part marking in the ordering information table to represent what the brand has been on the products.
Added PDIP note in the thermal information section and specified the Pb-free reflow note is applicable to SOIC
pages only.
Updated disclaimer.
Jul 27, 2018
FN6052.4
Added Related Literature on page 1.
Updated Ordering Information table.
Removed Retired parts, added tape and reel quantity column, and added MSL note.
Updated Typical Operating Circuits on page 4.
Thermal Information on page 5:
Removed Maximum Lead Temperature (Soldering 10s)+300°C (SOIC - Lead Tips Only)
Added Pb-Free Reflow information
Updated POD M8.15 from rev 0 to rev 4. Changes since rev 0:
Removed "u" symbol from drawing (overlaps the "a" on Side View).
Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Changed Note 1 "1982" to "1994"
Updated POD M14.15 from rev 0 to rev 1. Changes since rev 0:
Added land pattern and moved dimensions from table onto drawing
Added Revision History.
Updated disclaimer.
FN6052 Rev.5.00
Nov 21, 2018
Page 14 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
For the most recent package outline drawing, see E8.3.
Package Outline Drawings
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INDEX
AREA
INCHES MILLIMETERS
1
2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
BASE
PLANE
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
-
A
A
1
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
13. Controlling Dimensions: INCH. In case of conflict between
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
English and Metric dimensions, the inch dimensions control.
e
e
6
A
B
14. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
15. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
L
0.115
2.93
4
9
16. Dimensions A, A1 and L are measured with the package seated
N
8
8
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
17. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
18. E and
pendicular to datum
19. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
20. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
21. N is the maximum number of terminal positions.
22. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
FN6052 Rev.5.00
Nov 21, 2018
Page 15 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
For the most recent package outline drawing, see E14.3.
N
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1
2
3
N/2
INCHES MILLIMETERS
-B-
-C-
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-A-
A
A1
A2
B
-
4
D
E
BASE
PLANE
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
A2
A
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
SEATING
PLANE
L
C
L
-
D1
B1
B1
C
8
eA
A1
A
D1
e
-
eC
C
B
eB
D
5
0.010 (0.25) M
C
B S
D1
E
5
NOTES:
0.325
0.280
8.25
7.11
6
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
E1
e
5
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
e
6
A
B
-
0.430
0.150
-
10.92
3.81
7
4. Dimensions A, A1 and L are measured with the package seated in
L
0.115
2.93
4
9
JEDEC seating plane gauge GS-3.
N
14
14
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
Rev. 0 12/93
e
6. E and
dicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be perpen-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1maximumdimensionsdonotincludedambarprotrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
FN6052 Rev.5.00
Nov 21, 2018
Page 16 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
M8.15
For the most recent package outline drawing, see M8.15.
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
1.35 (0.053)
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN6052 Rev.5.00
Nov 21, 2018
Page 17 of 19
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
M14.15
For the most recent package outline drawing, see M14.15.
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
4
0.10 C A-B 2X
8.65
A
3
6
DETAIL"A"
0.22±0.03
D
14
8
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
(0.35) x 45°
4° ± 4°
5
0.31-0.51
0.25M C A-B D
B
3
6
TOP VIEW
0.10 C
H
1.75 MAX
1.25 MIN
0.25
GAUGE PLANE
SEATING PLANE
C
0.10-0.25
1.27
0.10 C
SIDE VIEW
DETAIL "A"
(1.27)
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
(1.50)
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
FN6052 Rev.5.00
Nov 21, 2018
Page 18 of 19
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Colophon 7.2
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