ISL78843ASRHF/PROTO_技术文档

Radiation Hardened, High Performance Industry

Standard Single-Ended Current Mode PWM Controller

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

The ISL7884xASRH is a high performance, radiation hardened

drop-in replacement for the popular 28C4x and 18C4x PWM

Features

• Electrically Screened to DLA SMD # 5962-07249

• QML Qualified Per MIL-PRF-38535 Requirements

• 1A MOSFET Gate Driver

controllers suitable for a wide range of power conversion

applications including boost, flyback, and isolated output

configurations. Its fast signal propagation and output

switching characteristics make this an ideal product for

existing and new designs.

• 90µA Typical Start-up Current, 125µA Max

• 35ns Propagation Delay Current Sense to Output

• Fast Transient Response with Peak Current Mode Control

• 9V to 13.2V Operation

Features include up to 13.2V operation, low operating current,

90µA typical start-up current, adjustable operating frequency

to 1MHz, and high peak current drive capability with 50ns rise

and fall times.

• Adjustable Switching Frequency to 1MHz

• 50ns Rise and Fall Times with 1nF Output Load

PART NUMBER

ISL78840ASRH

ISL78841ASRH

ISL78843ASRH

ISL78845ASRH

RISING UVLO

MAX. DUTY CYCLE

7.0

100%

50%

• Trimmed Timing Capacitor Discharge Current for Accurate

Deadtime/Maximum Duty Cycle Control

• 1.5MHz Bandwidth Error Amplifier

8.4V

100%

50%

• Tight Tolerance Voltage Reference Over Line, Load and

Temperature

• ±3% Current Limit Threshold

Specifications for Rad Hard QML devices are controlled by the

Defense Logistics Agency Land and Maritime (DLA). The SMD

numbers listed in the ordering information must be used when

ordering.

• Pb-Free Available (RoHS Compliant)

Applications

• Current Mode Switching Power Supplies

• Isolated Buck and Flyback Regulators

• Boost Regulators

Detailed Electrical Specifications for the ISL788xASRH are

contained in SMD 5962-07249. A “hot-link” is provided on our

website for downloading.

• Direction and Speed Control in Motors

• Control of High Current FET Drivers

Pin Configurations

ISL78840ASRH, ISL78841ASRH,

ISL78843ASRH, ISL78845ASRH

(8 LD FLATPACK)

ISL78840ASRH, ISL78841ASRH,

ISL78843ASRH, ISL78845ASRH

(8 LD SBDIP)

TOP VIEW

COMP

FB

1

2

3

4

8

7

6

5

V

REF

COMP

FB

1

2

3

4

8

7

6

5

V

REF

DD

CS

OUT

GND

CS

OUT

GND

RTCT

April 5, 2012

FN6991.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Ordering Information

TEMP. RANGE

PACKAGE

ORDERING NUMBER

ISL78840ASRHVX/SAMPLE

ISL78840ASRHF/PROTO

5962R0724901QXC

PART NUMBER

ISL78840ASRHVX/SAMPLE

(°C)

(Pb-Free)

PKG. DWG. #

-55 to +125

Die

ISL78840ASRHF/PROTO (Notes 1, 2)

ISL78840ASRHQF (Notes 1, 2)

ISL78840ASRHVF (Notes 1, 2)

ISL78840ASRHD/PROTO (Notes 1, 2)

ISL78840ASRHQD (Notes 1, 2)

ISL78840ASRHVD (Notes 1, 2)

ISL78841ASRHVX/SAMPLE

8 Ld Flatpack

8 Ld SBDIP

Die

K8.A

D8.3

5962R0724901VXC

ISL78840ASRHD/PROTO

5962R0724901QPC

5962R0724901VPC

ISL78841ASRHVX/SAMPLE

ISL78841ASRHF/PROTO

5962R0724902QXC

5962R0724902VXC

ISL78841ASRHF/PROTO (Notes 1, 2)

ISL78841ASRHQF (Notes 1, 2)

ISL78841ASRHVF (Notes 1, 2)

ISL78841ASRHD/PROTO (Notes 1, 2)

ISL78841ASRHQD (Notes 1, 2)

ISL78841ASRHVD (Notes 1, 2)

ISL78843ASRHVX/SAMPLE

8 Ld Flatpack

8 Ld SBDIP

Die

K8.A

D8.3

ISL78841ASRHD/PROTO

5962R0724902QPC

5962R0724902VPC

ISL78843ASRHVX/SAMPLE

ISL78843ASRHF/PROTO

5962R0724903QXC

5962R0724903VXC

ISL78843ASRHF/PROTO (Notes 1, 2)

ISL78843ASRHQF (Notes 1, 2)

ISL78843ASRHVF (Notes 1, 2)

ISL78843ASRHD/PROTO (Notes 1, 2)

ISL78843ASRHQD (Notes 1, 2)

ISL78843ASRHVD (Notes 1, 2)

ISL78845ASRHVX/SAMPLE

8 Ld Flatpack

8 Ld SBDIP

Die

K8.A

D8.3

ISL78843ASRHD/PROTO

5962R0724903QPC

5962R0724903VPC

ISL78845ASRHVX/SAMPLE

ISL78845ASRHF/PROTO

5962R0724904QXC

5962R0724904VXC

ISL78845ASRHF/PROTO (Notes 1, 2)

ISL78845ASRHQF (Notes 1, 2)

ISL78845ASRHVF (Notes 1, 2)

ISL78845ASRHD/PROTO (Notes 1, 2)

ISL78845ASRHQD (Notes 1, 2)

ISL78845ASRHVD (Notes 1, 2)

8 Ld Flatpack

8 Ld SBDIP

K8.A

D8.3

ISL78845ASRHD/PROTO

5962R0724904QPC

5962R0724904VPC

NOTES:

1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations.

2. For Moisture Sensitivity Level (MSL), please see device information page for ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH. For

more information on MSL please see techbrief TB363.

FN6991.2

April 5, 2012

2

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Absolute Maximum Ratings

Thermal Information

Supply Voltage V Without Ion Beam . . . . . . . . . . . .GND -0.3V to +30.0V

Supply Voltage V Under Ion Beam . . . . . . . . . . . . . .GND -0.3V to +14.7V

DD

Thermal Resistance (Typical)

8 Ld Flatpack Package (Notes 3, 5)

8 Ld SBDIP Package (Notes 4, 5)

θ

(°C/W)

140

98

θ

(°C/W)

15

DD

JA

JC

OUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to V + 0.3V

DD

Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 6.0V

Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A

ESD Rating

Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 2kV

Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 200V

Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Radiation Information

Maximum Total Dose

Recommended Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Supply Voltage (Typical Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 13.2V

(Dose Rate = 50 - 100radSi/s) . . . . . . . . . . . . . . . . . . . . . 100 krads (Si)

SEB (No Burnout) (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . 80Mev/mg/cm2

SEL (No latchup) (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 80Mev/mg/cm2

SET (Regulated V

within ±3%) (Note 9) . . . . . . . . . . . . 40Mev/mg/cm2

OUT

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

4. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

5. For θ , the "case temp" location is the center of the ceramic on the package underside.

JC

6. All voltages are with respect to GND.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic on page 3 and page 4. V = 13.2V, R = 10kΩ, C = 3.3nF, T = -55 to +125°C. Typical values are at T = +25°C. Boldface limits apply over

DD

T

A

the operating temperature range, -55 to +125°C.

MIN

MAX

PARAMETER

UNDERVOLTAGE LOCKOUT

START Threshold

TEST CONDITIONS

(Note 10)

TYP

(Note 10)

UNITS

ISL78840A, ISL78841A

ISL78843A, ISL78845A

ISL78840A, ISL78841A

ISL78843A, ISL78845A

ISL78840A, ISL78841A

ISL78843A, ISL78845A

6.5

7.0

8.4

6.6

7.6

7.5

9.0

6.9

8.0

-

V

8.0

STOP Threshold

Hysteresis

6.1

V

7.3

V

-

0.4

0.8

90

V

-

V

Start-up Current, I

V

< START Threshold

125

500

4.0

5.5

µA

mA

DD

< START Threshold, 100krad

300

2.9

4.75

Operating Current, I

DD

(Note 7)

Operating Supply Current, I

REFERENCE VOLTAGE

Overall Accuracy

Includes 1nF GATE loading

D

Over line (V = 9V to 13.2V), load of

DD

4.925

5.000

5.050

V

1mA and 10mA, temperature

Long Term Stability

Current Limit, Sourcing

Current Limit, Sinking

CURRENT SENSE

T

= +125°C, 1000 hours (Note 8)

-

5

-

mV

mA

A

-20

5

-

Input Bias Current

V

= 1V

-1.0

0.97

2.75

-

1.0

1.03

3.15

55

µA

V

CS

Input Signal, Maximum

1.00

2.82

35

Gain, A = ΔV

/ΔV

CS

0 < V < 910mV, V = 0V

CS FB

V/V

ns

CS COMP

CS to OUT Delay

FN6991.2

April 5, 2012

6

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic on page 3 and page 4. V = 13.2V, R = 10kΩ, C = 3.3nF, T = -55 to +125°C. Typical values are at T = +25°C. Boldface limits apply over

DD

T

A

the operating temperature range, -55 to +125°C. (Continued)

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 10)

TYP

(Note 10)

UNITS

ERROR AMPLIFIER

Open Loop Voltage Gain

Unity Gain Bandwidth

(Note 8)

-

90

-

dB

MHz

V

1.5

-

Reference Voltage, V

V

= V

COMP

2.475

-1.0

1.0

-0.4

4.80

0.4

-

2.500

2.530

REF

FB

FB Input Bias Current, FBI

COMP Sink Current

COMP Source Current

COMP VOH

= 0V

-0.2

1.0

µA

mA

V

IB

FB

= 1.5V, V = 2.7V

FB

-

COMP

= 1.5V, V = 2.3V

FB

-

= 2.3V

-

V

REF

FB

COMP VOL

= 2.7V

1.0

-

V

PSRR

Frequency = 120Hz, V = 9V to 13.2V

DD

80

dB

(Note 8)

OSCILLATOR

Frequency Accuracy

Initial, T = +25°C

48

51

0.2

5

53

kHz

%

A

Frequency Variation with V

Temperature Stability

T = +25°C, (f

A

- f )/f

13.2V 9V 12V

-

1.0

DD

(Note 8)

-

%

Amplitude, Peak-to-Peak

Static Test

RTCT = 2.0V

-

1.75

1.0

7.8

-

V

RTCT Discharge Voltage (Valley Voltage)

Discharge Current

OUTPUT

V

6.5

8.5

mA

Gate VOH

V

to OUT, I

OUT

= -100mA

= 100mA

-

1.0

35

20

-

2.0

-

V

DD

Gate VOL

OUT to GND, I

OUT

Peak Output Current

Rise Time

C

V

= 1nF (Note 8)

= 1nF

A

OUT

60

40

50

ns

µA

Fall Time

= 1nF

OUTPUT OFF state leakage

PWM

= 5V

DD

Maximum Duty Cycle

(ISL78840A, ISL78843A)

COMP = V

94.0

47.0

-

96.0

48.0

-

%

REF

Maximum Duty Cycle

(ISL78841A, ISL78845A)

Minimum Duty Cycle

NOTES:

COMP = GND

0

7. This is the V current consumed when the device is active but not switching. Does not include gate drive current.

DD

8. Limits established by characterization and are not production tested.

9. SEE tests performed with VREF bypass capacitor of 0.22µF and F = 200kHz. SEB/L tests done on a standalone open loop configuration. SET tests

SW

done in a closed loop configuration. For SEL no hard latch requiring manual intervention were observed. For more information see:

ISL7884xASRH SEE Test Report.

10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

FN6991.2

April 5, 2012

7

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Typical Performance Curves

1.01

1.001

1.000

0.999

0.998

0.997

0.996

0.995

1.00

0.99

0.98

-60 -40 -20

0

20 40 60 80 100 120 140

-60 -40 -20

0

20 40 60 80 100 120 140

TEMPERATURE (°C)

FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE

FIGURE 1. FREQUENCY vs TEMPERATURE

3

10

1.001

1.000

0.998

0.997

0.996

100pF

100

10

1

220pF

330pF

470pF

1.0nF

2.2nF

3.3nF

4.7nF

6.8nF

1

10

100

-60 -40 -20

0

20 40 60 80 100 120 140

RT (kΩ)

TEMPERATURE (°C)

FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN

FIGURE 3. EA REFERENCE vs TEMPERATURE

COMP - COMP is the output of the error amplifier and the input of

the PWM comparator. The control loop frequency compensation

network is connected between the COMP and FB pins.

Pin Descriptions

RTCT - This is the oscillator timing control pin. The operational

frequency and maximum duty cycle are set by connecting a

FB - The output voltage feedback is connected to the inverting

input of the error amplifier through this pin. The non-inverting

input of the error amplifier is internally tied to a reference

voltage.

resistor, RT, between V

and this pin and a timing capacitor,

REF

CT, from this pin to GND. The oscillator produces a sawtooth

waveform with a programmable frequency range up to 2.0MHz.

The charge time, t , the discharge time, t , the switching

C

D

frequency, f, and the maximum duty cycle, D

approximated from Equations 1 through 4:

, can be

MAX

CS - This is the current sense input to the PWM comparator. The

range of the input signal is nominally 0V to 1.0V and has an

internal offset of 100mV.

t

≈ 0.533 ⋅ RT ⋅ CT

(EQ. 1)

(EQ. 2)

C

GND - GND is the power and small signal reference ground for all

functions.

0.008 ⋅ RT – 3.83

0.008 ⋅ RT – 1.71

⎛

⎝

⎞

⎠

---------------------------------------------

t

≈ –RT ⋅ CT ⋅ In

D

OUT - This is the drive output to the power switching device. It is a

high current output capable of driving the gate of a power

MOSFET with peak currents of 1.0A. This GATE output is actively

f = 1 ⁄ (t + t

)

(EQ. 3)

(EQ. 4)

C

D

held low when V is below the UVLO threshold.

DD

D = t ⋅ f

V

- V is the power connection for the device. The total supply

DD DD

C

current will depend on the load applied to OUT. Total I current

DD

The formulae have increased error at higher frequencies due to

propagation delays. Figure 4 may be used as a guideline in

selecting the capacitor and resistor values required for a given

switching frequency for the ISL78841ASRH, ISL78845ASRH. The

value for the ISL78840ASRH, ISL78843ASRH will be twice that

shown in Figure 4.

is the sum of the operating current and the average output

current. Knowing the operating frequency, f, and the MOSFET

gate charge, Qg, the average output current can be calculated

from Equation 5:

(EQ. 5)

I

= Qg × f

OUT

FN6991.2

April 5, 2012

8

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

To optimize noise immunity, bypass V to GND with a ceramic

DD

resistor also damps any oscillations caused by the resonant tank

of the parasitic inductances in the traces of the board and the

FET’s input capacitance. TID environment of >50krads requires

the use of a bleeder resistor of 10k from the OUT pin to GND.

capacitor as close to the V and GND pins as possible.

DD

V

- The 5.00V reference voltage output. +1.0/-1.5% tolerance

REF

over line, load and operating temperature. The recommended

bypass to GND cap is in the range 0.1µF to 0.22µF. A typical

value of 0.15µF can be used.

Slope Compensation

For applications where the maximum duty cycle is less than 50%,

slope compensation may be used to improve noise immunity,

particularly at lighter loads. The amount of slope compensation

required for noise immunity is determined empirically, but is

generally about 10% of the full scale current feedback signal. For

applications where the duty cycle is greater than 50%, slope

compensation is required to prevent instability.

Functional Description

Features

The ISL7884xASRH current mode PWM makes an ideal choice

for low-cost flyback and forward topology applications. With its

greatly improved performance over industry standard parts, it is

the obvious choice for new designs or existing designs which

require updating.

Slope compensation may be accomplished by summing an

external ramp with the current feedback signal or by subtracting

the external ramp from the voltage feedback error signal. Adding

the external ramp to the current feedback signal is the more

popular method.

Oscillator

The ISL7884xASRH has a sawtooth oscillator with a

programmable frequency range to 2MHz, which can be

From the small signal current-mode model [1] it can be shown

that the naturally-sampled modulator gain, Fm, without slope

compensation is calculated in Equation 6:

programmed with a resistor from V

and a capacitor to GND on

REF

the RTCT pin. (Please refer to Figure 4 for the resistor and

capacitance required for a given frequency).

1

-----------------

Fm =

(EQ. 6)

Sntsw

Soft-Start Operation

Soft-start must be implemented externally. One method,

illustrated below, clamps the voltage on COMP.

where Sn is the slope of the sawtooth signal and tsw is the

duration of the half-cycle. When an external ramp is added, the

modulator gain becomes Equation 7:

1

(EQ. 7)

------------------------------------

-------------------------

Fm =

=

(Sn + Se)tsw

m Sntsw

c

V

REF

where Se is slope of the external ramp and becomes Equation 8:

D

C

R

1

COMP

GND

Se

Sn

-------

m

= 1 +

(EQ. 8)

c

Q

1

The criteria for determining the correct amount of external ramp

can be determined by appropriately setting the damping factor of

the double-pole located at the switching frequency. The

double-pole will be critically damped if the Q-factor is set to 1,

over-damped for Q < 1, and under-damped for Q > 1. An

under-damped condition may result in current loop instability.

FIGURE 5. SOFT-START

1

(EQ. 9)

-------------------------------------------------

Q =

π(m (1 – D) – 0.5)

The COMP pin is clamped to the voltage on capacitor C plus a

1

c

base-emitter junction by transistor Q . C is charged from V

1

REF

1

where D is the percent of on-time during a switching cycle.

Setting Q = 1 and solving for Se yields Equation 10:

through resistor R and the base current of Q . At power-up C is

1

fully discharged, COMP is at ~0.7V, and the duty cycle is zero. As

C charges, the voltage on COMP increases, and the duty cycle

increases in proportion to the voltage on C . When COMP

1

reaches the steady state operating point, the control loop takes

1

π

1

⎛⎛

⎝⎝

⎞

– 1

(EQ. 10)

--

-------------

= S

+ 0.5

e

n

⎠

1 – D

over and soft-start is complete. C continues to charge up to

1

Since Sn and Se are the on-time slopes of the current ramp and

the external ramp, respectively, they can be multiplied by t to

V

and no longer affects COMP. During power-down, diode D

REF

1

ON

quickly discharges C so that the soft-start circuit is properly

1

obtain the voltage change that occurs during t

.

ON

initialized prior to the next power-on sequence.

1

π

1

⎛⎛

⎝⎝

⎞

– 1

--

-------------

V

= V

+ 0.5

(EQ. 11)

e

n

⎠

Gate Drive

1 – D

The ISL7884xASRH is capable of sourcing and sinking 1A peak

current. To limit the peak current through the IC, an optional

external resistor may be placed between the totem-pole output of

the IC (OUT pin) and the gate of the MOSFET. This small series

where V is the change in the current feedback signal (ΔI) during

the on-time and Ve is the voltage that must be added by the

external ramp.

n

FN6991.2

April 5, 2012

9

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

For a flyback converter, Vn can be solved in terms of input

voltage, current transducer components, and primary

inductance, yielding Equation 12:

Assuming the designer has selected values for the RC filter (R

6

and C ) placed on the CS pin, the value of R required to add the

4

9

appropriate external ramp can be found by superposition.

2.05D ⋅ R

6

D ⋅ T

⋅ V ⋅ R

IN CS

1

π

1

SW

---------------------------

(EQ. 16)

V

=

e

V

⎛⎛

⎞

– 1

---------------------------------------------------- --

-------------

V

=

+ 0.5

V

R

+ R

9

e

⎝⎝

⎠

(EQ. 12)

6

L

1 – D

p

The factor of 2.05 in Equation 16 arises from the peak amplitude

of the sawtooth waveform on RTCT minus a base-emitter junction

drop. That voltage multiplied by the maximum duty cycle is the

voltage source for the slope compensation. Rearranging to solve

where R is the current sense resistor, T is the switching

CS sw

period, L is the primary inductance, V is the minimum input

p

IN

voltage, and D is the maximum duty cycle.

for R yields Equation 17:

9

The current sense signal at the end of the ON time for CCM

operation is Equation 13:

(2.05D – V ) ⋅ R

e

6

---------------------------------------------

R

=

Ω

(EQ. 17)

9

V

e

(1 – D) ⋅ V ⋅ T

sw

N

⋅ R

CS

⎛

⎜

⎝

⎞

⎟

⎠

O

S

------------------------

---------------------------------------------

V

=

I

+

O

V

(EQ. 13)

CS

The value of R determined in Equation 15 must be rescaled so

CS

that the current sense signal presented at the CS pin is that

N

P

2L

s

predicted by Equation 13. The divider created by R and R

makes this necessary.

6

9

where V is the voltage across the current sense resistor, L is

CS

s

the secondary winding inductance, and I is the output current at

current limit. Equation 13 assumes the voltage drop across the

output rectifier is negligible.

O

R

+ R

9

R

9

6

--------------------

R′

=

⋅ R

(EQ. 18)

CS

Since the peak current limit threshold is 1.00V, the total current

feedback signal plus the external ramp voltage must sum to this

value when the output load is at the current limit threshold as:

Example:

V

= 12V

IN

O

V

= 48V

V

+ V

= 1V

CS

(EQ. 14)

e

L = 800µH

s

shown in Equation 14.

Substituting Equations 12 and 13 into Equation 14 and solving

Ns/Np = 10

Lp = 8.0µH

for R yields Equation 15:

CS

I

= 200mA

O

1

--------------------------------------------------------------------------------------------------------------------------------------------------------

=

R

CS

Switching Frequency, f = 200kHz

sw

1

--

⎛

+ 0.5

⎞

⎟

D ⋅ T ⋅ V

N

(1 – D) ⋅ V ⋅ T

O sw

⎛

⎞

⎟

⎠

π

sw

IN

s

⎜

--------------------------------- -----------------

------

---------------------------------------------

⋅

–1

+

⋅ I

+

⎜

Duty Cycle, D = 28.6%

O

⎜

⎝

⎟

⎠

L

1 – D

N

p

2L

s

⎝

p

R = 499Ω

6

(EQ. 15)

Solve for the current sense resistor, R , using Equation 15.

CS

Adding slope compensation is accomplished in the

R

= 295mΩ

CS

ISL7884xASRH using an external buffer transistor and the RTCT

signal. A typical application sums the buffered RTCT signal with

the current sense feedback and applies the result to the CS pin

as shown in Figure 6.

Determine the amount of voltage, Ve, that must be added to the

current feedback signal using Equation 12.

Ve = 92.4mV

Using Equation 17, solve for the summing resistor, R , from CT to

9

CS.

V

R = 2.67kΩ

REF

9

Determine the new value of R (R’ ) using Equation 18.

CS CS

R9

R’ = 350mΩ

CS

R6

Additional slope compensation may be considered for design

margin. The above discussion determines the minimum external

ramp that is required. The buffer transistor used to create the

external ramp from RTCT should have a sufficiently high gain

(>200) so as to minimize the required base current. Whatever

base current is required reduces the charging current into RTCT

and will reduce the oscillator frequency.

RTCT

C4

FIGURE 6. SLOPE COMPENSATION

FN6991.2

April 5, 2012

10

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Fault Conditions

References

[1] Ridley, R., “A New Continuous-Time Model for Current Mode

Control”, IEEE Transactions on Power Electronics, Vol. 6,

No. 2, April 1991.

A Fault condition occurs if V

falls below 4.65V. When a Fault

REF

is detected, OUT is disabled. When V

exceeds 4.80V, the Fault

REF

condition clears, and OUT is enabled.

Ground Plane Requirements

Careful layout is essential for satisfactory operation of the device.

A good ground plane must be employed. A unique section of the

ground plane must be designated for high di/dt currents

associated with the output stage. V should be bypassed

DD

directly to GND with good high frequency capacitors.

Die Map

FN6991.2

April 5, 2012

11

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest Rev.

DATE

REVISION

CHANGE

February 28, 2012 FN6991.2 Pg 10 - Updated Equations 13 and 15 – Changed f

to T . Changed Equation 14 – added“V” to 1 making it 1V.

SW

Paragraph under Equation 12, changed f

Converted to new datasheet template.

is the switching frequency to T

is the switching period.

SW

November 9, 2011

Added Abs Max, Thermal Information, and MIN/MAX data for Electrical Spec table. Added boldface over-temp limit

notes.

Pg 14: Replaced POD K8.A rev 1 with rev 2. Changes as follows: : In Side View, added 0.045 (1.14) dimension and

removed "MIN" label from 0.026(0.66) dimension

April 22, 2010

April 8, 2010

FN6991.1 Added Electrical Spec Table showing only the typical values. Removed boldface over-temp limit notes.

Added SBDIP parts, pinout and Flatpack & SBDIP PODs.

December 21, 2009 FN6991.0 Initial pre-release

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page

on intersil.com: ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

FN6991.2

April 5, 2012

12

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Package Outline Drawing

K8.A

8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

Rev 2, 12/10

PIN NO. 1

ID OPTIONAL

0.015 (0.38)

0.008 (0.20)

1

2

0.050 (1.27 BSC)

0.005 (0.13)

0.265 (6.73)

0.245 (6.22)

MIN

PIN NO. 1

ID AREA

4

0.022 (0.56)

0.015 (0.38)

TOP VIEW

0.115 (2.92)

0.070 (1.18)

0.045 (1.14)

0.026 (0.66)

0.09 (0.23)

0.04 (0.10)

6

0.265 (6.75)

0.245 (6.22)

-D-

-H-

-C-

0.180 (4.57)

0.170 (4.32)

0.370 (9.40)

0.250 (6.35)

SEATING AND

BASE PLANE

0.03 (0.76) MIN

SIDE VIEW

0.007 (0.18)

0.004 (0.10)

NOTES:

LEAD FINISH

Index area: A notch or a pin one identification mark shall be located

adjacent to pin one and shall be located within the shaded area shown.

The manufacturer’s identification shall not be used as a pin one

identification mark. Alternately, a tab may be used to identify pin one.

1.

0.009 (0.23)

0.004 (0.10)

BASE

METAL

2. If a pin one identification mark is used in addition to a tab, the limits

of the tab dimension do not apply.

0.019 (0.48)

0.015 (0.38)

3. The maximum limits of lead dimensions (section A-A) shall be

measured at the centroid of the finished lead surfaces, when solder

dip or tin plate lead finish is applied.

0.0015 (0.04)

MAX

0.022 (0.56)

0.015 (0.38)

4. Measure dimension at all four corners.

3

5. For bottom-brazed lead packages, no organic or polymeric materials

shall be molded to the bottom of the package to cover the leads.

SECTION A-A

6. Dimension shall be measured at the point of exit (beyond the

meniscus) of the lead from the body. Dimension minimum shall

be reduced by 0.0015 inch (0.038mm) maximum when solder dip

lead finish is applied.

7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

8. Controlling dimension: INCH.

FN6991.2

April 5, 2012

13

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Ceramic Dual-In-Line Metal Seal Packages (SBDIP)

c1 LEAD FINISH

D8.3 MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C)

8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

-A-

-D-

E

INCHES

MIN

MILLIMETERS

BASE

(c)

METAL

SYMBOL

MAX

0.200

0.026

0.023

0.065

0.045

0.018

0.015

0.405

0.310

MIN

-

MAX

5.08

0.66

0.58

1.65

1.14

0.46

0.38

10.29

7.87

NOTES

b1

A

b

-

M

A

M

(b)

0.014

0.045

0.023

0.008

-

0.36

1.14

0.58

0.20

-

2

-B-

b1

b2

b3

c

3

SECTION A-A

S

D

bbb

C

A - B

-

D

4

BASE

S2

Q

PLANE

2

-C-

SEATING

PLANE

c1

D

3

L

-

S1

b2

eA

A A

E

0.220

5.59

-

e

eA/2

aaa M C A - B S D S

b

c

e

0.100 BSC

2.54 BSC

-

eA

eA/2

L

0.300 BSC

0.150 BSC

7.62 BSC

3.81 BSC

-

ccc

M

C A - B S D S

-

NOTES:

0.125

0.200

3.18

5.08

-

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark.

Q

0.015

0.005

0.060

0.38

0.13

1.52

5

S1

S2

α

-

6

7

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when

solder dip or tin plate lead finish is applied.

o

90

105

90

105

-

aaa

bbb

ccc

M

-

0.015

0.030

0.010

0.0015

-

0.38

0.76

0.25

0.038

-

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

-

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces

dimension b2.

2

8

N

8

5. Dimension Q shall be measured from the seating plane to the

base plane.

Rev. 0 4/94

6. Measure dimension S1 at all four corners.

7. Measure dimension S2 from the top of the ceramic body to the

nearest metallization or lead.

8. N is the maximum number of terminal positions.

9. Braze fillets shall be concave.

10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

11. Controlling dimension: INCH.

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6991.2

April 5, 2012

14


型号：	ISL78843ASRHF/PROTO
厂家：	RENESAS TECHNOLOGY CORP
描述：	1A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, CDFP8, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, FP-8 CD 开关
文件：	总14页 (文件大小：867K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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