ISL78845ASRH [INTERSIL]

Radiation Hardened, High Performance IndustryStandard Single-Ended Current Mode PWM Controller; 抗辐射，高性能工业标准的单端电流模式PWM控制器


型号：	ISL78845ASRH
厂家：	Intersil
描述：	Radiation Hardened, High Performance IndustryStandard Single-Ended Current Mode PWM Controller 抗辐射，高性能工业标准的单端电流模式PWM控制器控制器
文件：	总11页 (文件大小：648K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Radiation Hardened, High Performance Industry

Standard Single-Ended Current Mode PWM

Controller

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

The ISL7884xASRH is a high performance, radiation

hardened drop-in replacement for the popular 28C4x and

Features

• Electrically Screened to DSCC SMD # 5962-07249

• QML Qualified Per MIL-PRF-38535 Requirements

• 1A MOSFET Gate Driver

18C4x PWM controllers suitable for a wide range of

power conversion applications including boost, flyback,

and isolated output configurations. Its fast signal

propagation and output switching characteristics make

this an ideal product for existing and new designs.

• 90µA Typ Start-up Current, 125µA Max

• 35ns Propagation Delay Current Sense to Output

Features include up to 13.2V operation, low operating

current, 90µA typ start-up current, adjustable operating

frequency to 1MHz, and high peak current drive

capability with 50ns rise and fall times.

• Fast Transient Response with Peak Current Mode

Control

• 9V to 13.2V Operation

• Adjustable Switching Frequency to 1MHz

• 50ns Rise and Fall Times with 1nF Output Load

PART NUMBER

ISL78840ASRH

ISL78841ASRH

ISL78843ASRH

ISL78845ASRH

RISING UVLO

MAX. DUTY CYCLE

7.0

100%

50%

• Trimmed Timing Capacitor Discharge Current for

Accurate Deadtime/Maximum Duty Cycle Control

• 1.5MHz Bandwidth Error Amplifier

8.4V

100%

50%

• Tight Tolerance Voltage Reference Over Line, Load

and Temperature

• ±3% Current Limit Threshold

Specifications for Rad Hard QML devices are

controlled by the Defense Supply Center in

Columbus (DSCC). The SMD numbers listed in the

ordering information must be used when ordering.

• Pb-Free Available (RoHS Compliant)

Applications

• Current Mode Switching Power Supplies

• Isolated Buck and Flyback Regulators

• Boost Regulators

Detailed Electrical Specifications for the

ISL788xASRH are contained in SMD 5962-07249. A

“hot-link” is provided on our website for

downloading.

• Direction and Speed Control in Motors

• Control of High Current FET Drivers

Pin Configuration

ISL78840ASRH, ISL78841ASRH,

ISL78843ASRH, ISL78845ASRH

(8 LD FLATPACK)

TOP VIEW

COMP

REF

OUT

GND

RTCT

December 21, 2009

FN6991.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Ordering Information

TEMP. RANGE

(°C)

PACKAGE

ORDERING NUMBER

ISL78840ASRHF/PROTO

PART NUMBER

(Pb-Free)

8 Ld Flatpack

Die

ISL78840ASRHF/PROTO (Notes 1, 2)

ISL78840ASRHQF (Notes 1, 2)

ISL78840ASRHVF (Notes 1, 2)

ISL78840ASRHVX/SAMPLE

-55 to +125

5962R0724901QXC

5962R0724901VXC

ISL78840ASRHVX/SAMPLE

ISL78841ASRHF/PROTO

5962R0724902QXC

5962R0724902VXC

ISL78841ASRHF/PROTO (Notes 1, 2)

ISL78841ASRHQF (Notes 1, 2)

ISL78841ASRHVF (Notes 1, 2)

ISL78841ASRHVX/SAMPLE

8 Ld Flatpack

Die

ISL78841ASRHVX/SAMPLE

ISL78843ASRHF/PROTO

5962R0724903QXC

5962R0724903VXC

ISL78843ASRHF/PROTO (Notes 1, 2)

ISL78843ASRHQF (Notes 1, 2)

ISL78843ASRHVF (Notes 1, 2)

ISL78843ASRHVX/SAMPLE

8 Ld Flatpack

Die

ISL78843ASRHVX/SAMPLE

ISL78845ASRHF/PROTO

5962R0724904QXC

5962R07 24904VXC

ISL78845ASRHVX/SAMPLE

NOTES:

ISL78845ASRHF/PROTO (Notes 1, 2)

ISL78845ASRHQF (Notes 1, 2)

ISL78845ASRHVF (Notes 1, 2)

ISL78845ASRHVX/SAMPLE

8 Ld Flatpack

Die

1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant

and compatible with both SnPb and Pb-free soldering operations.

2. For Moisture Sensitivity Level (MSL), please see device information page for ISL78840ASRH, ISL78841ASRH, ISL78843ASRH,

ISL78845ASRH. For more information on MSL please see techbrief TB363.

FN6991.0

December 21, 2009

Functional Block Diagram

REF

START/STOP

UV COMPARATOR

ENABLE

FAULT

REF

UV COMPARATOR

GND

4.65V 4.80V

2.5V

A = 0.5

PWM

COMPARATOR

100mV

ONLY

ISL78841A,

ISL78845A

1.1V

CLAMP

VF TOTAL = 1.15V

ERROR

AMPLIFIER

COMP

OUT

36k

RESET

DOMINANT

REF

100k

2.9V

1.0V

150k

OSCILLATOR

COMPARATOR

<10ns

RTCT

CLOCK

8.4mA

Typical Application - 48V Input Dual Output Flyback

CR5

+3.3V

+1.8V

C21

+ C15

+ C16

R21

CR4

C22

C17

C20

C19

CR2

RETURN

CR6

36V TO 75V

R16

R17

R18

R19

C14

R28

R22

R15

C13

R27

R20

COMP

R26

REF

OUT

RTCT

GND

ISL7884xASRH

R10

CR1

C12

VR1

C11

R13

Typical Application - Boost Converter

C10

CR1

VIN+

+VOUT

RETURN

VIN+

COMP

REF

OUT

GND

RTCT

VIN-

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Typical Performance Curves

1.01

1.001

1.000

0.999

0.998

0.997

0.996

0.995

1.00

0.99

0.98

-60 -40 -20

20 40 60 80 100 120 140

-60 -40 -20

20 40 60 80 100 120 140

TEMPERATURE (°C)

FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE

FIGURE 1. FREQUENCY vs TEMPERATURE

1.001

1.000

0.998

0.997

0.996

100pF

100

220pF

330pF

470pF

1.0nF

2.2nF

3.3nF

4.7nF

6.8nF

100

-60 -40 -20

20 40 60 80 100 120 140

RT (kΩ)

TEMPERATURE (°C)

FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES

GIVEN

FIGURE 3. EA REFERENCE vs TEMPERATURE

COMP - COMP is the output of the error amplifier and

the input of the PWM comparator. The control loop

frequency compensation network is connected between

the COMP and FB pins.

Pin Descriptions

RTCT - This is the oscillator timing control pin. The

operational frequency and maximum duty cycle are set

by connecting a resistor, RT, between V

and this pin

REF

and a timing capacitor, CT, from this pin to GND. The

oscillator produces a sawtooth waveform with a

programmable frequency range up to 2.0MHz. The

FB - The output voltage feedback is connected to the

inverting input of the error amplifier through this pin. The

non-inverting input of the error amplifier is internally tied

to a reference voltage.

charge time, t , the discharge time, t , the switching

frequency, f, and the maximum duty cycle, D

, can be

(EQ. 1)

(EQ. 2)

MAX

CS - This is the current sense input to the PWM

comparator. The range of the input signal is nominally 0V

to 1.0V and has an internal offset of 100mV.

approximated from the Equations 1 through 4:

≈ 0.533 ⋅ RT ⋅ CT

GND - GND is the power and small signal reference

ground for all functions.

0.008 ⋅ RT – 3.83

0.008 ⋅ RT – 1.71

⎛

⎝

⎞

⎠

---------------------------------------------

≈ –RT ⋅ CT ⋅ In

OUT - This is the drive output to the power switching

device. It is a high current output capable of driving the

gate of a power MOSFET with peak currents of 1.0A. This

f = 1 ⁄ (t + t

)

(EQ. 3)

(EQ. 4)

GATE output is actively held low when V

UVLO threshold.

is below the

D = t ⋅ f

- V is the power connection for the device. The

The formulae have increased error at higher frequencies

due to propagation delays. Figure 4 may be used as a

guideline in selecting the capacitor and resistor values

required for a given switching frequency for the

ISL78841, ISL78845ASRH. The value for the ISL78840,

ISL78843ASRH will be twice that shown in Figure 4.

total supply current will depend on the load applied to

OUT. Total I current is the sum of the operating

current and the average output current. Knowing the

operating frequency, f, and the MOSFET gate charge, Qg,

FN6991.0

December 21, 2009

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

the average output current can be calculated from

Equation 5:

Gate Drive

The ISL7884xASRH is capable of sourcing and sinking 1A

peak current. To limit the peak current through the IC, an

optional external resistor may be placed between the

totem-pole output of the IC (OUT pin) and the gate of

the MOSFET. This small series resistor also damps any

oscillations caused by the resonant tank of the parasitic

inductances in the traces of the board and the FET’s input

capacitance. TID environment of >50krads requires the

use of a bleeder resistor of 10k from OUT pin to GND.

(EQ. 5)

= Qg × f

OUT

To optimize noise immunity, bypass V

to GND with a

and GND pins as

ceramic capacitor as close to the V

possible.

- The 5.00V reference voltage output. +1.0/-1.5%

REF

tolerance over line, load and operating temperature. The

recommended bypass to GND cap is in the range 0.1µF

to 0.22µF. A typical value of 0.15µF can be used.

Slope Compensation

For applications where the maximum duty cycle is less

than 50%, slope compensation may be used to improve

noise immunity, particularly at lighter loads. The amount

of slope compensation required for noise immunity is

determined empirically, but is generally about 10% of the

full scale current feedback signal. For applications where

the duty cycle is greater than 50%, slope compensation

is required to prevent instability.

Functional Description

Features

The ISL7884xASRH current mode PWM makes an ideal

choice for low-cost flyback and forward topology

applications. With its greatly improved performance over

industry standard parts, it is the obvious choice for new

designs or existing designs which require updating.

Slope compensation may be accomplished by summing

an external ramp with the current feedback signal or by

subtracting the external ramp from the voltage feedback

error signal. Adding the external ramp to the current

feedback signal is the more popular method.

Oscillator

The ISL7884xASRH has a sawtooth oscillator with a

programmable frequency range to 2MHz, which can be

programmed with a resistor from V

GND on the RTCT pin. (Please refer to Figure 4 for the

and a capacitor to

REF

From the small signal current-mode model [1] it can be

shown that the naturally-sampled modulator gain, Fm,

without slope compensation is calculated in Equation 6:

resistor and capacitance required for a given frequency).

Soft-Start Operation

Soft-start must be implemented externally. One method,

illustrated below, clamps the voltage on COMP.

-------------------

Fm =

(EQ. 6)

SnTsw

where Sn is the slope of the sawtooth signal and tsw is

the duration of the half-cycle. When an external ramp is

added, the modulator gain becomes Equation 7:

REF

(EQ. 7)

------------------------------------

-------------------------

Fm =

(Sn + Se)tsw

m Sntsw

COMP

GND

where Se is slope of the external ramp and becomes

Equation 8:

-------

= 1 +

(EQ. 8)

The criteria for determining the correct amount of

external ramp can be determined by appropriately

FIGURE 5. SOFT-START

setting the damping factor of the double-pole located at

the switching frequency. The double-pole will be critically

damped if the Q-factor is set to 1, over-damped for Q <

1, and under-damped for Q > 1. An under-damped

condition may result in current loop instability.

The COMP pin is clamped to the voltage on capacitor C

plus a base-emitter junction by transistor Q . C is

charged from V

through resistor R and the base

REF

current of Q . At power-up C is fully discharged, COMP

is at ~0.7V, and the duty cycle is zero. As C1 charges,

the voltage on COMP increases, and the duty cycle

(EQ. 9)

-------------------------------------------------

Q =

π(m (1 – D) – 0.5)

increases in proportion to the voltage on C . When COMP

reaches the steady state operating point, the control loop

takes over and soft start is complete. C continues to

charge up to V

and no longer affects COMP. During

REF

power down, diode D1 quickly discharges C1 so that the

soft start circuit is properly initialized prior to the next

power on sequence.

FN6991.0

December 21, 2009

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

where D is the percent of on time during a switching

cycle. Setting Q = 1 and solving for Se yields

Equation 10:

RTCT signal with the current sense feedback and applies

the result to the CS pin as shown in Figure 6.

⎛⎛

⎝⎝

⎞

– 1

(EQ. 10)

-------------

= S

+ 0.5

⎠

1 – D

REF

Since Sn and Se are the on time slopes of the current

ramp and the external ramp, respectively, they can be

multiplied by t

to obtain the voltage change that

occurs during t

RTCT

⎛⎛

⎝⎝

⎞

– 1

-------------

= V

+ 0.5

(EQ. 11)

⎠

1 – D

where V is the change in the current feedback signal

(ΔI) during the on time and Ve is the voltage that must

be added by the external ramp.

FIGURE 6. SLOPE COMPENSATION

For a flyback converter, Vn can be solved for in terms of

input voltage, current transducer components, and

primary inductance, yielding Equation 12:

Assuming the designer has selected values for the RC

filter (R and C ) placed on the CS pin, the value of R

required to add the appropriate external ramp can be

found by superposition.

D ⋅ T

⋅ V ⋅ R

IN CS

⎛⎛

⎞

– 1

---------------------------------------------------- --

-------------

+ 0.5

⎝⎝

⎠

(EQ. 12)

1 – D

2.05D ⋅ R

---------------------------

(EQ. 16)

+ R

where R

is the current sense resistor, f is the

switching frequency, L is the primary inductance, V is

The factor of 2.05 in Equation 16 arises from the peak

amplitude of the sawtooth waveform on RTCT minus a

base-emitter junction drop. That voltage multiplied by

the maximum duty cycle is the voltage source for the

the minimum input voltage, and D is the maximum duty

cycle.

The current sense signal at the end of the ON time for

CCM operation is Equation 13:

slope compensation. Rearranging to solve for R yields

Equation 17:

(1 – D) ⋅ V ⋅ f

⋅ R

⎛

⎜

⎝

⎞

⎟

⎠

(2.05D – V ) ⋅ R

------------------------

-------------------------------------------

(EQ. 13)

---------------------------------------------

(EQ. 17)

The value of R

determined in Equation 15 must be

rescaled so that the current sense signal presented at the

where V

is the voltage across the current sense

resistor, L is the secondary winding inductance, and I is

CS pin is that predicted by Equation 13. The divider

the output current at current limit. Equation 13 assumes

the voltage drop across the output rectifier is negligible.

created by R and R makes this necessary.

+ R

--------------------

R′

⋅ R

(EQ. 18)

Since the peak current limit threshold is 1.00V, the total

current feedback signal plus the external ramp voltage

must sum to this value when the output load is at the

current limit threshold as shown in Equation 14.

Example:

= 12V

+ V

= 1

(EQ. 14)

V = 48V

L = 800µH

Substituting Equations 12 and 13 into Equation 14 and

solving for R

yields Equation 15:

Ns/Np = 10

Lp = 8.0µH

----------------------------------------------------------------------------------------------------------------------------------------------------

⎛

+ 0.5

⎞

⎟

D ⋅ f ⋅ V

(1 – D) ⋅ V ⋅ f

O sw

⎛

⎜

⎝

⎞

⎟

⎠

I = 200mA

⎜

------------------------------- -----------------

------

-------------------------------------------

⋅

–1

⋅

⎜

⎝

⎟

⎠

1 – D

Switching Frequency, f

= 200kHz

(EQ. 15)

Duty Cycle, D = 28.6%

R = 499Ω

Adding slope compensation is accomplished in the

ISL7884xASRH using an external buffer transistor and

the RTCT signal. A typical application sums the buffered

Solve for the current sense resistor, R , using

Equation 15.

FN6991.0

December 21, 2009

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

= 295mΩ

current is required reduces the charging current into

RTCT and will reduce the oscillator frequency.

Determine the amount of voltage, Ve, that must be

added to the current feedback signal using Equation 12.

Fault Conditions

A Fault condition occurs if V

falls below 4.65V. When a

Fault is detected OUT is disabled. When V exceeds

Ve = 92.4mV

REF

Using Equation 17, solve for the summing resistor, R ,

from CT to CS.

4.80V, the Fault condition clears, and OUT is enabled.

Ground Plane Requirements

R = 2.67kΩ

Careful layout is essential for satisfactory operation of

the device. A good ground plane must be employed. A

unique section of the ground plane must be designated

for high di/dt currents associated with the output stage.

Determine the new value of R (R’ ) using

Equation 18.

R’ = 350mΩ

should be bypassed directly to GND with good high

Additional slope compensation may be considered for

design margin. The above discussion determines the

minimum external ramp that is required. The buffer

transistor used to create the external ramp from RTCT

should have a sufficiently high gain (>200) so as to

minimize the required base current. Whatever base

frequency capacitors.

References

[1] Ridley, R., “A New Continuous-Time Model for

Current Mode Control”, IEEE Transactions on Power

Electronics, Vol. 6, No. 2, April 1991.

FN6991.0

December 21, 2009

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Die Map

FN6991.0

December 21, 2009

ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to

web to make sure you have the latest Rev.

DATE

REVISION

CHANGE

12/21/09

FN6991.0

Initial Release

Products

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Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,

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processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device

information page on intersil.com: ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH

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FN6991.0

December 21, 2009

ISL78845ASRH [INTERSIL]

相关型号：

ISL78845ASRHF/PROTO

ISL78845ASRHF/PROTO

ISL78845ASRHVX/SAMPLE

ISL78845ASRHVX/SAMPLE

ISL80015

ISL80015A

ISL80015AFRZ-T

ISL80015AFRZ-T7A

ISL80015AIRZ-T

ISL80015AIRZ-T7A

ISL80015FRZ-T

ISL80015FRZ-T7A