ISL78220_技术文档

DATASHEET

ISL78220

FN7688

Rev 4.00

September 2, 2014

6-Phase Interleaved Boost PWM Controller with Light Load Efficiency

Enhancement

The ISL78220 6-phase controller is targeted for applications

Features

where high efficiency (>95%) and high power are required. The

• Peak current mode PWM control with adjustable slope

compensation

multiphase boost converter architecture uses interleaved

timing to multiply channel ripple frequency and reduce input

and output ripple. Lower ripple results in fewer input/output

capacitors and therefore lower component cost and smaller

implementation area.

• Precision resistor/DCR current sensing

• 2-, 3-, 4- or 6-phase operation

• Adjustable phase dropping/diode emulation/pulse skipping

for high efficiency at light load

The ISL78220 has a dedicated pin to initiate the phase

dropping scheme for higher efficiency at light load by dropping

phases based on the load current, so the switching and core

losses in the converter are reduced significantly. As the load

increases, the dropped phase(s) are added back to

• Phase dropping facilitated with companion FET driver

ISL78420 (featuring tri-level input control)

• Adjustable switching frequency or external synchronization

from 75kHz up to 1MHz per phase

accommodate heavy load transients and improve efficiency.

Input current is sensed continuously by measuring the voltage

across a dedicated current sense resistor or by inductor DCR.

This current sensing provides precision channel-current

balancing, and per-phase overcurrent protection. A separate

totalizing current limit function provides overcurrent protection

for all the phases combined. This two-stage current protection

provides maximum performance and circuit reliability.

• Over-temperature/overvoltage protection

• 2V ±1.0% internal reference

• Pb-free, 44 Ld 10x10 EP-TQFP package (RoHS compliant)

• -40°C to +125°C operating temperature range

• AEC-Q100 qualified

Applications

The ISL78220 can also provide for input voltage tracking via

the VREF2 pin. The comparison reference voltage will be the

lower of the VREF2 pin or the internal 2V reference. By using a

resistor network between VIN and VREF2 pin, the output

voltage can track input voltage to limit the output power during

automotive cranking conditions.

• Automotive power supplies

- Start/stop DC/DC converter

- Electronic power steering systems (EPAS)

- Fuel pumps

- Injection system

The ISL78220 can output a clock signal for expanding

operation to 12 phases, which offers high system flexibility.

The threshold-sensitive enable input is available to accurately

coordinate the start-up of the ISL78220 with any other voltage

rail.

• Audio trunk amplifier power supplies

• Telecom and industrial power supplies

Related Literature

• AN1726, “ISL78220EVAL1Z: 6-Phase Interleaved

Synchronous Boost Converter”

0.98

WITH PHASE DROPPING

0.97

0.96

0.95

0.94

0.93

0.92

0.91

0.90

0.89

0.88

WITHOUT PHASE DROPPING

6V INPUT, 12V OUTPUT

SYNCHRONOUS BOOST

0

5

10

15

20

25

30

OUTPUT CURRENT (A)

FIGURE 1. EFFICIENCY vs OUTPUT CURRENT vs PHASE DROPPING MODE

FN7688 Rev 4.00

September 2, 2014

Page 1 of 22

ISL78220

Pin Configuration

ISL78220

(44 LD 10x10 EP-TQFP)

TOP VIEW

44 43 42 41 40 39 38 37 36 35 34

FS

SS

VIN

1

33

2

ISEN6P

ISEN6N

ISEN4P

ISEN4N

32

31

30

29

3

4

5

6

7

8

9

COMP

FB

VREF2

GND

ISEN2P

ISEN2N

ISEN5P

ISEN5N

ISEN3P

ISEN3N

28

27

26

25

24

23

SLOPE

PLL_COMP

SYNC

10

11

CLK_OUT

PWM_INV

12 13 14 15 16 17 18 19 20 21 22

Functional Pin Description

PIN #

SYMBOL

DESCRIPTION

1

2

FS

A resistor placed from FS to ground will set the PWM switching frequency.

SS

Use this pin to set-up the desired soft-start time. A capacitor placed from SS to ground will set up the soft-start

ramp rate and in turn determine the soft-start time.

3

4

5

COMP

FB

The output of the transconductance amplifier. Place the compensation network between COMP and GND for

compensation loop design.

The inverting input of the transconductance amplifier. A resistor network should be placed between FB pin and

output rail to set the output voltage.

VREF2

External reference input to the transconductance amplifier. When the VREF2 pin voltage drops below 1.8V, the

internal reference will be shifted from 2V to VREF2. The VREF2 voltage can be programmed by connecting a

resistor divider network from VCC or VIN.

6

7

GND

Bias and reference ground for the IC.

SLOPE

This pin programs the slope of the internal slope compensation. A resistor should be connected from SLOPE pin

to GND. Please refer to “Adjustable Slope Compensation” on page 18 for how to choose the resistor value.

8

9

PLL_COMP

SYNC

This pin serves as the compensation node for the PLL. A second order passive loop filter connected between

PLL_COMP pin and GND compensates the PLL feedback loop.

Frequency synchronization pin. Connecting the SYNC pin to an external square pulse waveform (typically 20% to

80% duty cycle) will synchronize the converter switching frequency to the fundamental frequency of the input

waveform. If SYNC function is not used, tie SYNC pin to GND. A 500nA current source is connected internally to

pull-down the SYNC pin if it is left open.

10

11

CLK_OUT

PWM_INV

This pin provides a clock signal to synchronize with another ISL78220. This provides scalability and flexibility. The

rising edge signal on the CLKOUT pin is in phase with the leading edge of the PWM1 signal.

This pin determines the polarity of the PWM output signal. Pulling this pin to GND will force normal operation with

inverting MOSFET drivers. Pulling this pin to VCC will invert the PWM signal for operation with non-inverting

MOSFET drivers. This function provides the flexibility for the ISL78220 to work with different drivers.

FN7688 Rev 4.00

September 2, 2014

Page 2 of 22

ISL78220

Functional Pin Description(Continued)

PIN #

SYMBOL

DESCRIPTION

12

PWM_TRI

This pin enables the tri-level of the PWM output signal. Pulling this pin to GND forces the PWM output to be

traditional two level logic. Pulling the PWM_TRI pin to VCC will enable tri level PWM signals, then PWM output can

be at the 2.5V tri level condition.

13,14,15, PWM1, PWM3, PWM5, Pulse width modulation outputs. Connect these pins to the PWM input pins of the external driver ICs. The number

16, 17, 18 PWM2, PWM4, PWM6 of active channels is determined by the state of PWM3, PWM4, PWM5 and PWM6. For 2-phase operation, connect

PWM3 to VCC; similarly, connect PWM4 to VCC for 3-phase, connect PWM5 or PWM6 to VCC for 4-phase

operation.

19

20

DRIVE_EN

NC

Driver enable output pin. This pin is connected to the enable pin of MOSFET drivers.

Not Connected – This pin is not electrically connected internally.

21,22,23, ISEN1N, ISEN1P, ISEN3N, The ISENxP and ISENxN pins are current sense inputs to individual differential amplifiers. The sensed current is

24,25,26, ISEN3P, ISEN5N, ISEN5P, used as a reference for current mode control and overcurrent protection. Inactive channels should have their

27,28,29, ISEN2N, ISEN2P, ISEN4N, respective ISENxN pins connected to VIN and ISENxP pins left open or tied to VIN. The ISL78220 utilizes external

30, 31, 32 ISEN4P, ISEN6N, ISEN6P sense resistor current sensing method or Inductor DCR sensing method.

33

VIN

Connect input rail to this pin. This pin is connected to the internal linear regulator, generating the power necessary

to operate the chip. It is recommended the DC voltage applied to the VIN pin does not exceed 40V.

34

VCC

This pin is the output of the internal linear regulator that supplies the bias and gate voltage for the IC. A minimum

4.7µF decoupling ceramic capacitor should be connected from VCC to GND. The controller starts to operate when

the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below

the falling POR threshold. This pin can be connected directly to a +5V supply if VIN falls below 5.6V.

35

36

GND

Bias and reference ground for the IC.

MODE

Mode selection pin. Pull this pin to logic HIGH for forced PWM mode; phase dropping/adding is inactive during

forced PWM mode. Connecting a resistor from MODE pin to GND will initialize phase dropping mode (PDM). In

PDM, a 5µA fixed reference current will flowing out of MODE pin, and the phase dropping threshold can be

programmed by adjusting the resistor value.

37

38

IOUT

IOUT is the current monitor pin with an additional OCP adjustment function. An RC network needs to be placed

between IOUT and GND to ensure the proper operation. The voltage at the IOUT pin will be proportional to the input

current. If the voltage on the IOUT pin is higher than 2V, the ISL78220 will go into overcurrent protection mode

and the chip will latch off until the EN pin is toggled.

VIN_SEN

The VIN_SEN pin is used for sensing the VIN voltage. A resistor divider network is connected between this pin and

boost power stage input voltage rail. When the voltage on VIN_SEN is greater than 2.4V, the VIN_OVB pin will be

pulled low to indicate an input overvoltage condition. The threshold voltage can be programmed by changing the

divider ratios.

39

40

VIN_OVB

The VIN_OVB pin is an open drain indicator of an overvoltage condition at the input. When the voltage on the

VIN_SEN pin is greater than the 2.4V threshold, the VIN_OVB pin will be pulled low.

VOUT_SEN

The VOUT_SEN pin is used for sensing the output voltage, a resistor divider network is connected between this pin

and output voltage rail. When the voltage on VOUT_SEN pin is greater than 2.4V, VOUT_OVB pin will be pulled low,

indicating an output overvoltage condition.

41

42

43

VOUT_OVB

DMAX

EN

The VOUT_OVB pin is an open drain indicator of an overvoltage condition at the output. When the voltage on the

VOUT_SEN pin is greater than the 2.4V threshold, the VOUT_OVB pin will be pulled low and latched, toggling VIN

or EN will reset the latch.

DMAX pin sets the maximum duty cycle of the PWM modulator. If the DMAX pin is connected to GND, the

maximum duty cycle will be set to 91.7%. Floating this pin will limit the duty cycle to 75% and connecting the

DMAX pin to VCC will limit the duty cycle to 83.3%.

This pin is a threshold-sensitive enable input for the controller. Connecting the power supply input to EN pin

through an appropriate resistor divider provides a means to synchronize power-up of the controller and the

MOSFET driver ICs. When EN pin is driven above 1.2V, the ISL78220 is active depending on status of the internal

POR, and pending fault states. Driving EN pin below 1.1V will clear all fault states and the ISL78220 will soft-start

when re-enabled.

44

PGOOD

This pin is used as an indication of the end of soft-start and output regulation. It is an open-drain logic output that

is low impedance until the soft-start is completed. It will be pulled low again once the UV/OV/OC/OT conditions

are detected.

Exposed Pad

It is recommended to solder the Exposed Pad to the ground plane.

FN7688 Rev 4.00

September 2, 2014

Page 3 of 22

ISL78220

Ordering Information

PART NUMBER

PART

MARKING

TEMP RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

(Notes 2, 3)

ISL78220ANEZ (Note 1)

ISL78220EVAL1Z

NOTES:

ISL78220 ANEZ

-40 to +125

44 Ld EP-TQFP

Q44.10x10A

Evaluation Board: 6-phase synchronous boost (6V to 11V input, 12V, 30A output - see AN1726 for details)

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78220. For more information on MSL please see tech brief TB363.

ISL78220 Block Diagram

VIN_OVB

VOUT_SEN

PGOOD

VOUT_OVB

SYNC

PLL_COMP

OV_OUT

OV_IN

VIN_SEN

OV_IN

OC_ALL

OC_PH

2.4V

UV

OC

OT

2.4V

SYNC DETECT

REF

VIN

FAULT CONTROL

CIRCUITS

5V LDO

2V

VCC

S

Q

R

POR

CLK_OUT

DMAX

FS

DMAX

VCO

EN

2.4V

OV_OUT

1.2V

FB

OVER

TEMP

OT

UV

0.8V_REF

SLOPE

COMPENSATION

SLOPE

5µA

SS

SOFT- START LOGIC

DRIVE_EN

ISEN1P

ISEN1N

ISEN1

20k

CSA

DUPLICATE FOR EACH CHANNEL

IOUT1

160µA

OC_PH

Q

S

(FOR PH1 & PH2

ZCD

ONLY)

2V

R1

R2

Gm

VREF2

FB

DMAX

OT

OC

PWM CONTROL

PWM1

OV_OUT

PWM_TRI

PWM_INV

MODE

PH3

PH4

PH5

PH6

COMP

PHASE DROP CONTROL

IOUT1

IOUT6

MODE

ADDER

IOUT

OC_ALL

2V

GND

FN7688 Rev 4.00

September 2, 2014

Page 4 of 22

ISL78220

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-0.3V to +45V

All ISEN_ Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V - 5V to V + 0.3V

Thermal Resistance (Typical)

44 Ld EP-TQFP Package (Notes 4, 5) . . . . . .



(°C/W)

28



(°C/W)

2.5

JA

JC

IN

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6V

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V + 0.3V

CC

ESD Rating

Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .2.5kV

Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 200V

Charge Device Model (Tested per AEC-Q100-11) . . . . . . . . . . . . . . 1.5kV

Latch-up (Tested per JESD78B, Class II, Level A) . . . . . . . . . . . . . . . 100mA

Operating Conditions

Voltage at VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.6V to +40V

All ISEN_ Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 5V to VIN + 0.3V

Voltage at VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

Ambient Temperature (Auto) . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4.  is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

5. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Operating Conditions: V = 12V, T = -40°C to +125°C, unless otherwise specified. Typical specifications

IN

A

are at T = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C.

A

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 6)

TYP

(Note 6) UNITS

SUPPLY INPUT

Input Voltage Range

5.6

12

8

40

12

10

V

Input Supply Current (Normal Mode)

Input Supply Current (Shutdown Mode)

INTERNAL LINEAR REGULATOR

LDO Output Voltage (VCC Pin)

LDO Current Limit (VCC pin)

V

= 12V, R = 158kΩ(For f = 250kHz)EN = 5V

FS

mA

µA

IN

S

= 12V, R = 158kΩ(For f = 250kHz)EN = 0V

FS

IN

S

V

> 5.6V, C = 4.7µF from VCC to GND, I

< 50mA

4.75

5

5.25

V

IN

L

VCC

VCC = 3V, C = 4.7µF from VCC to GND

L

200

mA

(Note 7)

POWER-ON RESET (POR) AND ENABLE

POR Threshold

VCC Rising

VCC Falling

Rising

4.4

4.1

1.1

4.5

4.2

1.2

70

4.6

4.3

1.3

V

EN Threshold

V

Hysteresis

mV

OSCILLATOR

Accuracy of Switching Frequency Setting

Adjustment Range of Switching Frequency

FS pin voltage

R

= 158kΩfrom FS to GND

225

75

250

1

275

kHz

V

FS

1000

SOFT-START

Soft-Start Current

C

= 2.2nF from SS to GND

= 500mV

4

0

5

6

2

µA

V

SS

Soft-Start Pre-Bias Voltage Range

Soft-Start Pre-Bias Voltage Accuracy

Soft-Start Clamp Voltage

REFERENCE VOLTAGE

V

-25

25

mV

V

FB

3.4

2

System Accuracy

-40°C to +125°C, measure at FB pin, V

> 2.5V

1.98

-1

2.02

1

V

REF2

FB Pin Input Bias Current

VREF2 Pin Input Bias Current

V

= 2V, V

> 2.5V

REF2

µA

FB

VREF2 = 1.6V

-1

1

FN7688 Rev 4.00

September 2, 2014

Page 7 of 22

ISL78220

Electrical Specifications Operating Conditions: V = 12V, T = -40°C to +125°C, unless otherwise specified. Typical specifications

IN

A

are at T = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) (Continued)

A

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 6)

TYP

(Note 6) UNITS

V

External Reference Voltage Range

External Reference Voltage Accuracy

0.7

1.8

1

V

REF2

-40°C to +125°C, measure at FB pin, VREF2 = 1.8V

-40°C to +125°C, measure at FB pin, VREF2 = 0.7V

-1

%

-1.5

1.5

ERROR AMPLIFIER

Transconductance Gain

Output Impedance

Unity Gain Bandwidth

Slew Rate

2

5

mS

MΩ

MHz

V/µs

µA

C

= 100pF from COMP pin to GND

11

COMP

2.5

±300

COMP

Output Current Capability

Maximum Output Voltage

Minimum Output Voltage

PWM CORE

3.5

V

0.5

V

Duty Cycle Matching

I

V

= 60µA, R

SLOPE

= 30.1k, f = 250kHz,

-6

6

%

mV

ns

ISENxP

S

= 2V, 6-phase, T = +25°C

COMP

A

Zero Crossing Detection (ZCD) Threshold for

PWM1/PWM2

R

= 750Ω

3

SEN1, 2

Leading Edge Blanking (Audio Mode)

V

= VCC, V

= GND, V

= 0.5V

Ts/12

(Note 8)

MODE

PWM_TRI

COMP

Leading Edge Blanking (Other Mode)

SLOPE pin Voltage

V

<4V or V

130

515

0.3

ns

mV

µA

V

COMP

385

650

ISENxN Bias Current

V

= V

, from V - 1V to V

ISENxP IN

ISENxN

IN

ISENxN, ISENxP Common Mode Voltage Range

PWMx OUTPUT

> 12V

V

- 5

V

IN

PWMx Output Voltage LOW

PWMx Output Voltage HIGH

PWMx Tri-State Output Voltage

PWMx Pull-Down Current

I

= -500µA

= +500µA

= ±100µA

0.5

2.7

V

PWMx

4.5

2.3

2.5

50

V

During Phase Detection Time (t on Figure 14), V

= 1V

PWM

µA

V

3

PWM3 - PWM6 Disable Threshold

PHASE ADDING/DROPPING

MODE Pull-up Current

During Phase Detection Time (t on Figure 14)

3.5

4.2

3

V

= 2.4V

= 1.6V

= 1.8V

5.1

1.6

1.2

0.8

1.2

0.8

1.2

40

6

µA

V

MODE

V

Threshold, 6-phase, Drop Phase 5/6

Threshold, 6-phase, Drop Phase 4

Threshold, 6-phase, Drop Phase 3

Threshold, 4-phase, Drop Phase 4

Threshold, 4-phase, Drop Phase 3

Threshold, 3-phase, Drop Phase 3

Threshold Hysteresis

1.575

1.175

0.775

1.175

0.775

1.175

1.625

1.225

0.825

1.225

0.825

1.225

IOUT

V

mV

V

Phase Drop Disable Threshold at MODE pin

CURRENT SENSE AND OVERCURRENT PROTECTION

Peak Current Limit for Individual Channel

IOUT Current Tolerance

3.5

4

160

280

2.0

µA

V

I

= 60µA, 6-phase

260

300

ISENxP

Maximum Voltage Limit at IOUT Pin

FN7688 Rev 4.00

September 2, 2014

Page 8 of 22

ISL78220

Electrical Specifications Operating Conditions: V = 12V, T = -40°C to +125°C, unless otherwise specified. Typical specifications

IN

A

are at T = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) (Continued)

A

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 6)

TYP

(Note 6) UNITS

DMAX PIN

DMAX Threshold, High

DMAX Threshold, Low

DMAX Floating Voltage

Max Duty Cycle, DMAX = GND

Max Duty Cycle, DMAX = FLOAT

Max Duty Cycle, DMAX = VCC

DMAX Source/Sink Current

PWM_TRI, PWM_INV, SYNC PIN DIGITAL LOGIC

Input Leakage Current

Input Pull-Down Current

Logic Input Low

3

V

2

V

During phase detection time (t on Figure 14)

2.5

91.7

75

3

V

= 3.5V

%

COMP

%

83.3

50

%

During t on Figure 14

µA

3

After t on Figure 14

3

-1

1

EN < 1V

1

µA

V

EN > 2V, Pin Voltage = 2.1V

0.4

1.5

0.8

Logic Input High

2

V

DRIVE_EN, CLK_OUT PIN

Output High Voltage

I

= 500µA

= -500µA

4.5

V

DRIVE_EN

Output Low Voltage

0.5

VOUT SENSE PIN

Input Leakage Current

Threshold Voltage

-1

1

µA

V

2.325

2.4

2.475

VIN SENSE PIN

Input Leakage Current

Threshold Voltage

-1

1

µA

V

2.325

2.4

2.475

Hysteresis

110

mV

VOUT_OVB, VIN_OVB PIN

Leakage Current

V

= High

1

µA

V

Low Voltage

I

= 0.5mA

0.2

POWER-GOOD MONITOR PIN

PGOOD Leakage Current

PGOOD Low Voltage

PGOOD = High

= 0.5mA

1

µA

V

I

0.2

123

PGOOD

Overvoltage Rising Trip Point

Overvoltage Rising Hysteresis

Undervoltage Rising Trip Point

Undervoltage Rising Hysteresis

OVER-TEMPERATURE PROTECTION

Over-Temperature Trip Point

Over-Temperature Recovery Threshold

NOTES:

V

/V , V

> 2.5V

117

77

120

5

%

FB REF REF2

/V , V

FB REF REF2

/V , V

FB REF REF2

80

5

83

/V , V

FB REF REF2

160

145

°C

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise noted. Compliance to datasheet limits is assured by one or more

methods: production test, characterization and/or design.

7. Please refer to LDO current derating curve in “Internal 5V LDO Output Current Limit Derating Curves” on page 19 for I

8. Ts = switching period = 1/(switching frequency).

vs V

IN.

MAX

FN7688 Rev 4.00

September 2, 2014

Page 9 of 22

ISL78220

Typical Performance Curves

0.98

0.99

0.98

0.97

0.96

0.95

0.94

0.93

0.92

0.91

0.90

0.89

WITH PHASE DROPPING

0.97

WITH PHASE DROPPING

WITHOUT PHASE DROPPING

0.96

WITHOUT PHASE DROPPING

0.95

0.94

0.93

0.92

0.91

0.90

6V INPUT, 12V OUTPUT

11V INPUT, 12V OUTPUT

SYNCHRONOUS BOOST

0.89

0.88

0

5

10

15

20

25

30

0

5

10

15

20

25

30

OUTPUT CURRENT (A)

FIGURE 2. 6V INPUT EFFICIENCY vs OUTPUT CURRENT vs PHASE

DROPPING MODE

FIGURE 3. 11V INPUT EFFICIENCY vs OUTPUT CURRENT vs PHASE

DROPPING MODE

12.5

12.4

12.3

12.2

12.1

12.0

11.9

11.8

11.7

12.5

12.4

12.3

12.2

12.1

12.0

11.9

11.8

11.7

11.6

11.5

6V INPUT

25

30A OUTPUT

11.5

0

5

10

15

20

30

6

7

8

9

10

11

INPUT VOLTAGE (V)

OUTPUT CURRENT (A)

FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE

FIGURE 4. OUTPUT VOLTAGE vs OUTPUT CURRENT

5V

PHASE 1

100mV

50mV

VOUT

(AC-COUPLED)

VOUT

(AC-COUPLED)

6V INPUT, 30A OUTPUT

6V INPUT, 0 TO 30A TO 0 STEP LOAD

2ms/DIV

1µs/DIV

FIGURE 6. FULL LOAD OUTPUT RIPPLE

FIGURE 7. FULL STEP LOAD TRANSIENT

FN7688 Rev 4.00

September 2, 2014

Page 10 of 22

ISL78220

Typical Performance Curves(Continued)

PWM1

5V

PWM3

PWM5

5V

PWM5

5V

CLK_OUT

1µs/DIV

FIGURE 9. WAVEFORMS WITH PWM_INV = VCC

FIGURE 8. WAVEFORMS WITH PWM_INV = GND

PWM1

5V

6V INPUT, 1A OUTPUT

2V

5V

EN

5V

PWM4

VCC

5V

PWM6

PGOOD

VOUT

5A

IL1

PWM_INV = GND, 8V INPUT, 30A OUTPUT

1µs/DIV

5ms/DIV

FIGURE 11. ENABLE/DISABLE WAVEFORMS

FIGURE 10. FULL LOAD WAVEFORMS

6V INPUT, 30A OUTPUT

VREF2

1V

5V

VOUT

5ms/DIV

FIGURE 12. MODULATING VREF2 INPUT

FN7688 Rev 4.00

September 2, 2014

Page 11 of 22

ISL78220

Operation Description

Multiphase Power Conversion

IL1 + IL2 + IL3

The technical challenges associated with producing a

single-phase converter, which is both cost-effective and thermally

viable for high power applications have forced a change to the

cost-saving approach of multiphase solution. The ISL78220

controller helps reduce the complexity of implementation by

integrating vital functions and requiring minimal output

components.

IL3

PWM3

IL2

PWM2

Interleaving

IL1

The switching of each channel in a multiphase converter is timed

to be symmetrically out-of-phase with each of the other channels.

Take a 3-phase converter for example, each channel switches

1/3 cycle after the previous channel and 1/3 cycle before the

following channel. As a result, the three-phase converter has a

combined ripple frequency three times greater than the ripple

frequency of any one phase. In addition, the peak-to-peak

amplitude of the combined inductor current is reduced in

proportion to the number of phases (Equations 1 and 2). The

increased ripple frequency and the lower ripple amplitude mean

that the designer can use less per-channel inductance and lower

total input and output capacitance for any performance

specification.

PWM1

TIME

FIGURE 13. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR

3-PHASE CONVERTER

PWM Operations

The timing of each channel is set by the total number of active

channels. The default channel setting for the ISL78220 is 6, and

the switching cycle is defined as the time between PWM pulse

initiation signals of each channel. The cycle time of the pulse

initiation signal is the inversion of the switching frequency set by

the resistor between the FS pin and ground. The PWM signals

command the MOSFET drivers to turn on/off the channel

MOSFETs. Normal operation assumes PWM_INV is tied to GND

and inverting MOSFET drivers are used.

Figure 13 illustrates the multiplicative effect on input ripple

current. The three channel currents (I , I , and I ) combine to

L1 L2 L3

form the AC ripple current and the DC input current. The ripple

component has three times the ripple frequency of each

individual channel current. Each PWM pulse is triggered 1/3 of a

cycle after the start of the PWM pulse of the previous phase.

In the default 6-phase operation, the PWM2 pulse starts 1/6 of a

cycle after PWM1, the PWM3 pulse starts 1/6 of a cycle after

PWM2, the PWM4 pulse starts 1/6 of a cycle after PWM3, the

PWM5 pulse starts 1/6 of a cycle after PWM4, and the PWM6

pulse starts 1/6 of a cycle after PWM5.

To understand the reduction of the ripple current amplitude in the

multiphase circuit, examine the equation representing an

individual channel’s peak-to-peak inductor current.

In Equation 1, V and V

IN OUT

respectively, L is the single-channel inductor value, and f is the

are the input and the output voltages

Phase Selection

S

The ISL78220 can work in 1, 2, 3, 4, 5 or 6-phase configuration.

Connecting the PWM5 or PWM6 to VCC selects 4-phase

operation and the pulse times are spaced in 1/4 cycle

increments. Connecting the PWM4 to VCC selects 3-phase

operation and the pulse times are spaced in 1/3 cycle

increments. Connecting the PWM3 to VCC selects 2-phase

operation and the pulse times are spaced in 1/2 cycle

increments. For the unused ISENxN and ISENxP, a 1kΩ resistor is

recommended to connect ISENxN and ISENxP, and connect

ISENxN to VIN.

switching frequency.

V

– V  V

IN IN

OUT

Lf

(EQ. 1)

I

= -----------------------------------------------

P-P

V

S

OUT

The input capacitors conduct the ripple component of the

inductor current. In the case of multiphase converters, the

capacitor current is the sum of the ripple currents from each of

the individual channels. Compare Equation 1 to the expression for

the peak-to-peak current after the summation of N symmetrically

phase-shifted inductor currents in Equation 2. Peak-to-peak

ripple current decreases by an amount proportional to the

number of channels. Reducing the inductor ripple current allows

the designer to use fewer or less costly input capacitors.

Modes of Operations

The different mode of operations will be determined by the

voltage combinations of the MODE pin and the PWM_TRI pin.

V

– N V  V

IN IN

OUT

Lf

If automatic phase adding/dropping function is not needed, the

MODE pin should be tied to VCC (Logic HIGH). If higher light load

efficiency is preferred, phase adding/dropping function could be

implemented by connecting the MODE pin through a resistor to

GND. A 5µA reference current will flow out of MODE pin to

I

= -----------------------------------------------------

(EQ. 2)

CP-P

V

S

OUT

generate corresponding V

. V

is used to compare with

MODE MODE

V

to determine the phase adding/dropping level.

IOUT

FN7688 Rev 4.00

September 2, 2014

Page 12 of 22

ISL78220

When PWM_TRI is tied to GND (Logic LOW), the PWM outputs will

be 2-levels (i.e., 0V and 5V).When PWM_TRI is pulled to VCC

(Logic HIGH), apart from generating the 0V and 5V PWM signals,

the PWM outputs can also generate 2.5V tri-level signal. The

external driver can identify this tri-level signal and turn off both

low-side and high-side output signals accordingly.

Operation Initialization Before

Soft-Start

Prior to converter initialization, proper conditions must exist on the

enable inputs (EN pin) and VCC pin. When both conditions are met,

the controller begins soft-start. Once the output voltage is within

the proper window of operation, V

is asserted logic high.

The truth table regarding V

and V for different

PWM_TRI

PGOOD

MODE

mode of applications is summarized in Table 1.

Figure 14 shows the ISL78220 internal circuit functions before

the soft-start begins.

TABLE 1. OPERATION MODE FOR DIFFERENT APPLICATIONS

EXTERNAL

DRIVER

IDENTIFY

EN

PWM 2.5V TRI-LEVEL

CASE MODE _TRI

SIGNAL?

APPLICATIONS

t

0

A

1

Yes

Synchronous boost for audio

amplifier power supply. No

phase dropping. (Note)

VCC

POR

t

0

B

Analog

1

Yes

Applications that need

t1 t2

t3

t4

t5

THENSOFT- START BEGINS

improving light load efficiency

(automatic phase dropping +

cycle-by-cycle diode emulation

+ pulse skipping).

PWM_DETECTION

t

0

C

1

0

No

Applications that the external

driver cannot identify tri-level

signal, no phase dropping.

PWM

t

D

Analog

Applications that the external

driver cannot identify tri-level

signal, with improved light load

efficiency (e.g., 6-phase

non-synchronous boost with

phase dropping).

FIGURE 14. CIRCUIT INITIALIZATION BEFORE SOFT-START

As shown on Figure 14, there are 5x intervals before the

soft-start is initialized, they are specified as t , t , t , t and t ,

1

2

3

4

5

respectively. The descriptions for each time interval are as

follows:

NOTE: Forced minimum ON pulses exists.

Time t : The enable comparator holds the ISL78220 in shutdown

1

until the V rises above 1.2V at the beginning of t time period.

Considerations for Audio

Amplifier Power Supply

Application

For multiphase boost converters used in audio amplifier

applications, it is preferred to have the following features:

EN

1

During t , V

will gradually increase until it reaches the internal

1

VCC

power-on reset (POR) rising threshold. Then the system enters t .

2

Time t : During t time, the device initialization occurs. The time

2

duration for t is typically from 60µs to 100µs.

2

Time t : The internal PWM detection signal will be asserted and

3

1. Automatic phase dropping function is NOT needed because

the load is fast changing.

the system enters the t period. During t the ISL78220 will

3 3

detect the voltage on each PWM pin to determine the active

phase number. If PWM1 or PWM2 is accidentally pulled to VCC,

the chip will be latched off and wait for power recycling. The time

2. In car audio amplifier applications, the switching frequency is

preferred to be fixed, such that it will not interfere with

FM/AM band.

duration for t is fixed to around 30µs.

3

3. For synchronous boost, diode emulation is needed during

start-up in order to prevent negative current dumping to the

input side.

Time t : When internal PWM detection signal is released the

4

system enters t period. During t period the ISL78220 will wait

4

until the internal PLL circuits are locked to the pre-set oscillator

frequency. When PLL locking is achieved, the oscillator will

4. For synchronous boost, a maximum duty cycle limitation on

the synchronous FET is preferred.

generate output at CLK_OUT pin. The time duration for t is

4

typically around 0.5ms, depending on PLL_COMP pin

configuration.

Based on the above mentioned “preferred features”, For audio

amplifier applications, it does not need phase dropping/adding,

but it needs a tri-state PWM signal if synchronous boost structure

is used. Also in order to limit the maximum duty cycle of the

synchronous FET, the minimal turn on time of the active FET

(Low-side FET for boost structure) will be changed from fixed

130ns to variable time, which is 1/12 of the switching periods.

Time t : After the PLL locks the frequency, the system enters the

5

t period. During t the PWM outputs are held in a

5

high-impedance state (If V

= 1) or logic low (if

is logic LOW to assure the

PWM_TRI

DRIVE_EN

V

= 0), and the V

PWM_TRI

external drivers remain off. The ISL78220 has one unique

FN7688 Rev 4.00

September 2, 2014

Page 13 of 22

ISL78220

feature to pre-bias the V based on V information during this

SS FB

SOFT-START WAVEFORM (CASE A)

V

time. The duration time for t is around 50µs.

5

After t the soft-start process will begin. The following section will

5

Vfb

discuss the soft-start in detail for different applications.

Vref

t4

Soft-Start Process for Different

Modes ^{(Refer to Table 1})

t7

0

t6

t5

SYNCHRONOUS

OPERATION

DIODE EMULATION

V

At the beginning of soft-start, the SS pin voltage will start ramping

up from a voltage equaling to FB voltage. The soft-start period ends

when the SS pin voltage reaches the lower power-good threshold

that is 80% of the lower value of VREF2 or 2V.

5V

LOWER FET TURN ON

(PWM_INV= 0)

PWM

2.5V

0

Case A (V

= VCC, V

= VCC)

SYNCHRONOUS

OPERATION

MODE

PWM_TRI

DIODE EMULATION

Figure 15 shows the pre-bias start-up PWM waveform for case A

in Table 1. The V = VCC so that PWM can output tri-level

5V

PWM_TRI

signal, which the external drivers need to identify, and

= VCC to ban the automatic phase dropping function.

(PWM_INV= 1)

PWM

2.5V

V

MODE

Time t , t : Same as the t , t in Figure 14, soft-start has not started

4

5

4 5

0

yet. See “Operation Initialization Before Soft-Start” on page 13 for a

detailed description.

5V

Time t : At the beginning of t the SS pin has already been

6

DRIVE_EN

pre-biased to a value very close to the V , so that the internal

FB

reference signal will start from the voltage close to FB pin. This

scheme will eliminate the internal delay for a non pre-biased

application.

0

FIGURE 15. SOFT-START WAVEFORM (CASE A)

(Note: t4, t5 periods are from Figure 5)

The DRIVE_EN pin, which is connected to the enable pins of the

external drivers, will be pulled high when first PWM toggles at the

beginning of t as a results external drivers will start working.

6,

Case B (V

Load Condition)

The only difference between the case A and case B start-up

waveforms is that at light load, case B can drop phases and have

cycle-by-cycle diode emulation at PWM1 and PWM2.

< 4V, V

= VCC, Light

The PWM signals will switch between tri-level and low. The driver

will only turn on the lower MOSFET accordingly, and the duty

cycle will increase gradually from 0 to steady state. The

synchronous MOSFET (Upper FET for Boost converter) will never

turn on during this time, so diode emulation can be achieved

during the start-up and in turn prevent negative current flowing

from output to input.

MODE

PWM_TRI

For the case B applications, where good light load efficiency is

always preferred, the ISL78220 provides three light load

efficiency enhancement methods. When the load current

reduces, the ISL78220 will first assert the automatic phase

dropping function to reduce the active phase number according

to the load level. The minimum active phase number is two. If the

load current further reduces even when running at two-phase

operation, the ISL78220 will assert a second method by utilizing

cycle-by-cycle diode emulation. During this time the IC will sense

the inductor current, and when the current is approximately zero

it will turn off the synchronous MOSFET. If the load current is

further reduced to deep light load operation, pulse skipping

function will kick in to optimize the overall efficiency.

Time t : Soft-start finishes at the beginning of t . The PWMs will

7

change to a 2-level 0V to 5V switching signal and the

synchronous MOSFET will be turned on.

FN7688 Rev 4.00

September 2, 2014

Page 14 of 22

ISL78220

SOFT-START WAVEFORM (CASE C)

SOFT-START WAVEFORM(CASEB, LIGHTLOAD)

V

Vfb

Vref

t4

Vref

t4

0

t6

t5

t7

0

t6

t5

SYNCHRONOUS

OPERATION WITH

CYCLE-BY-CYCLE

DIODE EMULATION

V

DIODE EMULATION

V

LOWER FET TURN ON

5V

LOWER FET TURN ON

DIODE EMULATION

(PWM_INV= 0)

PWM

(PWM_INV=0)

PWM

2.5V

0

SYNCHRONOUS

OPERATION WITH

CYCLE-BY-CYCLE

DIODE EMULATION

5V

(PWM_INV= 1)

PWM

(PWM_INV=1)

PWM

2.5V

0

5V

DRIVE_EN

0

FIGURE 17. SOFT-START WAVEFORM (CASE C, LIGHT LOAD)

(Note: t4, t5 periods are from Figure 5)

FIGURE 16. SOFT-START WAVEFORM (CASE B, LIGHT LOAD)

(Note: t4, t5 periods are from Figure 5)

Case C (V

= 0)

PWM_TRI

For applications that the driver cannot identify a tri-state PWM signal,

the V should be connected to GND (Logic LOW), such that

PWM_TRI

the PWM signal will only be two levels between 0V and 5V. Then

DRIVE_EN pin can be connected to the EN pin of the external drivers.

DRIVE_EN will be asserted when the PWM first toggles such that the

pre-bias start up capability can be achieved. Detailed soft-start for

case C is shown in Figure 17.

Time t , t : Same as the t , t in Figure 14, soft-start has not

4

5

4 5

started yet, see “Operation Initialization Before Soft-Start” on

page 13 for detailed description.

Time t : At the beginning of t , the PWM signal will start to

6

switch between 0V and 5V. The driver will turn on the lower and

upper MOSFETs accordingly, and the duty cycle for lower MOSFET

will increase gradually from 0 to steady state. DRIVE_EN will be

pulled high when the first PWM toggles at the beginning of t to

6

enable the external drivers.

FN7688 Rev 4.00

September 2, 2014

Page 15 of 22

ISL78220

The maximum frequency at each PWM output is 1MHz. If the FS

pin is accidentally shorted to GND or connected to a low

impedance node, the internal circuits will detect this fault

condition and fold back the switching frequency to the 75kHz

minimal value.

Soft-Start Ramp Slew Rate

Calculation

The soft-start ramp slew rate SR_SSis determined by the capacitor

value C from SS pin to GND. C_SScan be calculated based on

SS

Equation 3:

The ISL78220 contains a phase lock loop (PLL) circuit and has

frequency synchronization capability by simply connecting SYNC

pin to an external square pulse waveform (typically 20% to 80%

duty cycle). In normal operation, the external SYNC frequency

needs to be at least 20% faster than the internal oscillator

frequency setting. The ISL78220 will synchronize its switching

frequency to the fundamental frequency of the input waveform.

The frequency synchronization feature will synchronize the rising

edge of the PWM1 clock signal with the rising edge of the

external clock signal at the SYNC pin.

–12

5X10

V

s

(EQ. 3)







----------------------- ------

=

SR

SS



C

SS

Figure 18 shows the relationship between C and SR_SS

.

SS

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

The PLL is compensated with a series resistor-capacitor (Rc and

Cc) from the PLL_COMP pin to GND and a capacitor (Cp) from

PLL_COMP to GND. Typical values are Rc = 6.8kΩ, Cc = 6.8nF,

Cp = 1nF. The typical lock time is around 0.5ms.

The CLK_OUT pin provides a square pulse waveform at the

switching frequency. The amplitude is 5V with approximately

40% positive duty cycle, and the rising edge is synchronized with

the leading edge of PWM1.

10

Css (nF)

100

1

FIGURE 18. SOFT- START CAPACITOR vs SLEW RATE

Current Sensing

Oscillator and Synchronization

The ISL78220 senses the current continuously for fast response.

It supports both sense resistor and inductor DCR current sensing

methods. The sensed current for each active channel will be used

for loop control, phase current balance, individual channel

overcurrent protection and total average current protection. The

internal circuitry, shown in Figures 20 and 21, represents a single

channel. This circuitry is repeated for each channel, but may not

be active depending on the status of the PWM3, PWM4, PWM5,

and PWM6 pin voltage.

The switching frequency is determined by the selection of the

frequency-setting resistor, R , connected from FS pin to GND.

FS

Equation 4 is provided to assist in selecting the correct resistor

value.

10

–8



1







----------

R

= 4X10

– 5X10

(EQ. 4)

FS

f

SW

where f

SW

is the switching frequency of each phase. Figure 19

Peak current mode control is implemented by feeding back the

current output of the current sense amplifier (CSA) to the

regulator control loop. Individual channel peak current limit is

implemented by comparing the CSA output current with 160µA.

When the peak current limit comparator is tripped, the PWM

on-pulse is terminated and the IC is latched off.

shows the relationship between R and switching frequency.

FS

1000

900

800

700

600

500

400

300

200

100

0

Sense Resistor Current Sensing

A sense resistor can be placed in series with the power inductor.

As shown in Figure 20, The ISL78220 acquires the channel

current information by sensing the voltage signal across the

sense resistor. Because the voltage on both the positive input

and the negative input of CSA are forced to be equal, the voltage

across R

is equivalent to the voltage drop across the R

SET

resistor. The resulting current into the ISENxP pin is proportional

SEN

0

100

200

300

(k)

400

500

600

to the channel current, I . Equation 5 for I

is derived where I

L

SEN

L

R

FS

is the channel current:

FIGURE 19. R vs SWITCHING FREQUENCY

FS

R

SEN

----------------

I

= I



L

(EQ. 5)

SEN

R

ISET

FN7688 Rev 4.00

September 2, 2014

Page 16 of 22

ISL78220

voltage drop across the DCR, i.e., proportional to the channel

current.

VIN

V_OUT

R_SEN

L

With the internal low-offset differential current sense amplifier,

the capacitor voltage V is replicated across the sense resistor

C

R_SET

R

. Therefore the current flows into the ISENxP pin is

SET

I_SEN

proportional to the inductor current. Equation 8 shows that the

ratio of the channel current to the sensed current I is driven

SEN

by the value of the sense resistor and the DCR of the inductor.

SENSE RESISTOR

CURRENT SENSING

DCR

--------------

I

= I



(EQ. 8)

SEN

L

R

SET

I_SEN

ISEN(n)P

ISEN(n)N

CSA

Light Load Efficiency

Enhancement Schemes

ISL78220 INTERNAL CIRCUITS

For switching mode power supplies, the total loss is related to

both the conduction loss and the switching loss. At heavy load

the conduction loss is dominant while the switching loss will take

charge at light load condition. Therefore, if a multiphase

converter is running at a fixed phase number for the entire load

range, we will observe that below a certain load point the total

efficiency starts to drop heavily. The ISL78220 has automatic

phase dropping, cycle-by-cycle diode emulation and pulse

skipping features to enhance the light load efficiency. By

observing the total input current on-the-fly and dropping the

active phase numbers accordingly, the overall system can

achieve optimized efficiency over the entire load range. All the

above mentioned light load enhancement features can be

disabled by simply pulling the MODE pin to VCC.

FIGURE 20. SENSE RESISTOR CURRENT SENSING

Inductor DCR Sensing

An inductor’s winding is characteristic of a distributed resistance

as measured by the DCR (Direct Current Resistance) parameter.

I_L

DCR

C

L

V_IN

V_OUT

R

I_SEN

R_SET

Adjustable Automatic Phase

INDUCTOR DCR

CURRENT SENSING

Dropping/Adding at Light Load Condition

If the MODE pin is connected to a resistor to GND, and the voltage

on the MODE pin is lower than its disable threshold 4V, the

adjustable automatic phase dropping/adding mode will be

enabled. When the ISL78220 controller works in this mode, it

will automatically adjust the active phase number by comparing

I_SEN

ISEN(n)P

ISEN(n)N

CSA

ISL78220 INTERNAL CIRCUITS

the V

and V , which represents sensed total current

MODE

IOUT

information. The V

MODE

sets the overall phase dropping

is proportional to the input current,

FIGURE 21. INDUCTOR DCR CURRENT SENSING

threshold, and the V

IOUT

which is in turn proportional to the load current. The smaller the

load current, the lower the voltage observed on the IOUT pin, and

the ISL78220 will drop phases in operation. Once the MODE pin

voltage is fixed, the threshold to determine how many phases are

in operation is dependent on two factors:

Consider the inductor DCR as a separate lumped quantity, as

shown in Figure 21. The channel current I , flowing through the

L

inductor, will also pass through the DCR. Equation 6 shows the

S-domain equivalent voltage across the inductor V .

L

V

= I  s  L + DCR

L

(EQ. 6)

1. The maximum configured phase number.

L

2. The voltage on the IOUT pin (V

).

IOUT

A simple R-C network across the inductor extracts the DCR

voltage, as shown in Figure 21.

For example, if the converter is working in 6-phase operation and

the MODE pin is set to 1.2V, in this case the converter will

The voltage on the capacitor V , can be shown to be proportional

C

monitor the V

and compare to 1.2V, such that when the

IOUT

is less than 800mV (66.6% of 1.2V), it will drop from

to the channel current I , see Equation 7.

L

V

IOUT

L







-------------

6-phase to 4-phase; if less than 600mV (50% of 1.2V), it will drop

to 3-phase; if less than 400mV (33% of 1.2V), it will drop to

2-phase. The detailed threshold setting is shown in the “Electrical

Specifications” table on page 8.

s 

+ 1  DCR  I 

L



(EQ. 7)

DCR

V

= --------------------------------------------------------------------

C

s  RC + 1

If the R-C network components are selected such that the RC

time constant (= R*C) matches the inductor time constant

If PWM_TRI is tied to VCC, the dropped phase will provide a 2.5V

tri-level signal at its PWM output. The external driver has to

(= L/DCR), the voltage across the capacitor V is equal to the

C

FN7688 Rev 4.00

September 2, 2014

Page 17 of 22

ISL78220

identify this tri-state signal and turn off both the lower and upper

switches accordingly. For better transient response during phase

dropping, the ISL78220 will gradually reduce the duty cycle of

the phase from steady state to zero, typically within 15 switching

cycles. This gradual dropping scheme will help smooth the

change of the PWM signal and, in turn, will help to stabilize the

system when phase dropping happens.

Adjustable Slope Compensation

For a boost converter working in current mode control, slope

compensation is needed when steady state duty cycle is larger

than 50%. When slope compensation is too low the converter

can suffer from jitter or oscillation. On the other hand, over

compensation of the slope will cause the reduction of the phase

margin. Therefore, proper design of the slope compensation is

needed.

The ISL78220 also has an automatic phase adding feature

similar to phase dropping, but when doing phase adding there

will not be 15 switching cycles gradually adding. It will add

phases instantly to take care of the increased load condition. The

phase adding scheme is controlled by three factors.

The ISL78220 features adjustable slope compensation by

setting the resistor value R

from the SLOPE pin to GND.

SLOPE

This function will ease the compensation design and provide

more flexibility in choosing the external components.

1. The maximum configured phase number

For current mode control, typically we need the compensation

2. The voltage on the IOUT pin (V

).

IOUT

slope m to be 50% of the inductor current down ramp slope m

A

B

3. Individual phase current

when the lower MOSFET is off. The equation for choosing the

suitable resistor value is as follows:

Factors 1 and 2 are similar to the phase dropping scheme. If the

is higher than the phase dropping threshold plus the

V

IOUT

6

1.136x10 xLxR

SET

hysteresis voltage, the dropped phase will be added back one by

one instantly.

(EQ. 9)

---------------------------------------------------------



R

=

SLOPE

V

– V R



SEN

OUT

IN

The previously mentioned phase-adding method can take care of

the condition that the load current increases slowly. However, if

the load is fast increasing the IC will using different phase adding

scheme. The ISL78220 monitors the individual channel current

for all active phases. During phase adding the system will bring

down the pre-set channel current limit to 2/3 of its original value

(160µA). If any of the phase’s sensed current hit the 2/3 of

pre-set channel current limit threshold (i.e., 106.7µA), all the

phases will be added back instantly. After a fixed 1.5ms delay,

the phase dropping circuit will be activated and the system will

react to drop the phase number to the correct value.

Fault Monitoring and Protection

The ISL78220 actively monitors input/output voltage and current to

detect fault conditions. Fault monitors trigger protective measures

to prevent damage to the load. Common power-good indicator pin

(PGOOD pin) and VIN_OVB, VOUT_OVB pins are provided for linking

to external system monitors.

PGOOD Signal

The PGOOD pin is an open-drain logic output to indicate that the

soft-start period is completed and the output voltage is within the

specified range. This pin is pulled low during soft-start and

releases high after a successful soft-start. PGOOD will be pulled

low when a UV/OV/OC/OT fault occurs.

During phase adding when either phase hit the pre-set channel

current limit, there will be 200µs blanking time such that

per-channel OCP will not be triggered during this blanking time.

Diode Emulation at Very Light Load Condition

Input Overvoltage Detection

When phase dropping is asserted and the minimum phase

operation is 2 phases, if the load is still reducing and

synchronous boost structure is used, the ISL78220 controller will

enter into forced cycle-by-cycle diode emulation mode. The PWM

output will be tri-stated when inductor current falls to zero, such

that the synchronous MOSFET can be turned off accordingly

cycle-by-cycle for forced diode emulation. This cycle-by-cycle

diode emulation scheme will only be asserted when two

conditions are met:

The ISL78220 utilizes VIN_SEN and VIN_OVB pins to deal with a

high input voltage. The VIN_SEN pin is used for sensing the input

voltage. A resistor divider network is connected between this pin

and the boost power stage input voltage rail. When the voltage

on VIN_SEN is higher than 2.4V, the open drain output VIN_OVB

pin will be pulled low to indicate an input overvoltage condition,

The V overvoltage sensing threshold can be programmed by

IN

changing the resistor values, and hysteresis voltage of the

internal comparator is fixed to be 100mV.

1. The PWM_TRI pin voltage is logic HIGH.

Output Undervoltage Detection

2. Only two phases are running either by phase dropping or

initial configuration.

The undervoltage threshold is set at 80% of the internal voltage

reference. When the output voltage at FB pin is below the

undervoltage threshold minus the hysteresis, PGOOD is pulled

low. When the output voltage comes back to 80% of the

reference voltage, PGOOD will return back to high.

By utilizing the cycle-by-cycle diode emulation scheme in this

way, negative current is prevented and the system can still

optimize the efficiency even at very light load condition.

Pulse Skipping at Deep Light Load Condition

Output Overvoltage Detection/Protection

The ISL78220 overvoltage detection circuit monitors the FB pin

If the converter enters diode emulation mode and the load is still

reducing, eventually pulse skipping will occur to increase the

deep light load efficiency.

and is active after time t in Figure 14. The OV trip point is set to

2

120% of the internal reference level. Once an overvoltage

FN7688 Rev 4.00

September 2, 2014

Page 18 of 22

ISL78220

condition is detected, the PGOOD will be pulled low but the

controller will continue to operate.

Internal 5V LDO Output Current

Limit Derating Curves

The ISL78220 contains an internal 5V/200mA LDO, and the

input of LDO (VIN pin) can go as high as 40V. Based on the

The ISL78220 also provides the flexibility for output overvoltage

protection by utilizing the VOUT_SEN and VOUT_OVB pins. The

VOUT_SEN pin is used for sensing the output voltage. A resistor

divider network is connected between this pin and the boost

power stage output voltage rail. When the voltage on VOUT_SEN

is higher than 2.4V, the open drain output VOUT_OVB will be

pulled low, and the ISL78220 IC will be latched off to indicate an

junction to ambient thermal resistance R of the package, we

JA

need to guarantee that the maximum junction temperature

should be below +125°C T

. Figure 22 shows the relationship

MAX

between maximum allowed LDO output current and input

voltage. The curve is based on +35°C/W thermal resistance R

for the package, different curve represents different ambient

output overvoltage condition. The V

overvoltage sensing

JA

OUT

threshold can be programmed by changing the resistor values.

temperature T .

A

Overcurrent Protection

The ISL78220 has two levels of overcurrent protection. Each

phase is protected from an overcurrent condition by limiting its

peak current, and the combined total current is protected on an

average basis.

For the individual channel overcurrent protection, the ISL78220

continuously compares the CSA output current of each channel

with a 160µA reference current. If any channel’s current trips the

current limit comparator, the ISL78220 will be shut down.

However, during the phase adding period, the individual channel

current protection function will be blanked for 200µs, in order to

give other phases the chance to take care of the current.

The IOUT pin serves for both input current monitoring and total

average current OCP functions. The CSA output current for each

channel is scaled and summed together at this pin. An RC

network should be connected between IOUT pin and GND, such

that the ripple current signal can be filtered out and converted to

a voltage signal to represent the averaged total input current. The

relationship between total input current I_INand V_IOUTcan be

calculated as Equation 10: (Please refer to Figure 20 for RSEN

and RSET positions).

FIGURE 22. I

vs V

IN

LDO(MAX)

Dedicated VREF2 Pin for Input

Voltage Tracking

A second reference input pin, VREF2, is added to the input of the

transconductance amplifier. The ISL78220 internal reference will

automatically change to VREF2 when it is pulled below 1.8V. The

VREF2 pin can be connected to VIN through resistor network to

implement the automatic input voltage tracking function. This

function is very useful under car battery voltage cranking

conditions (such as when the car is parked and the driver is

listening to the stereo), where the full load power is typically not

needed. In this case, the ISL78220 can limit the output power by

allowing the output voltage to track the input voltage. If VREF2 is

not used, the pin should be connected to VCC.

R

SEN

---------------

V

= 0.75I

R

(EQ. 10)

IOUT

IN

IOUT

R

SET

When the V_IOUTis higher than 2V for a consecutive 100µs, the

ISL78220 IC will be triggered to shut down. This provides

additional safety for the voltage regulator.

Equation 11 can be used to calculate the value of the resistor R

IOUT

based on the desired OCP level I

.

AVG, OCP2

2

-------------------------------

R

=

(EQ. 11)

IOUT

Configurations for 12-Phase

Operation

For high power applications, two ISL78220 ICs can be easily

configured to support 12-phase operation. The IC that provide the

CLK_OUT signal is called master IC, and the IC that received the

CLK_OUT signal is called slave IC. Note that the two PWM1

signals are synchronized and the net effect is 6-phase operation

with double the output current.

I

AVG OCP2

The total average overcurrent protection scheme will not be

asserted until the soft-start pin voltage V reaches its clamped

value (approximately 3.5V). During the soft-start time the system

does not latch-off if per-channel or overall OC limit is reached.

Instead the individual channel current will run at its pre-set peak

current limit level.

SS

Thermal Protection

The ISL78220 will be disabled if the die junction temperature

reaches a nominal of +160°C. It will recover when the junction

temperature falls below a +15°C hysteresis. The +15°C

hysteresis insures that the device will not be re-enabled until the

junction temperature has dropped to below about +145°C.

FN7688 Rev 4.00

September 2, 2014

Page 19 of 22

ISL78220

ISL78220EVAL1Z Evaluation

Board

SYSTEM

DRIVE_EN

The ISL78220EVAL1Z evaluation board is designed for

automotive start-stop application to maintain a 12V at 30A rail

over a 6V to 11V input range. The ISL6609A inverting MOSFET

drivers with tri-state input capability facilitate synchronous boost

rectification and phase-dropping for high efficiency over the

entire load range. See AN1726 on for more information on

ISL78220EVAL1Z.

DRIVE_EN

CLK_OUT

DRIVE_EN

SYNC

MASTER IC

SLAVE IC

COMP

FB

SS

COMP

FB

SS

FIGURE 23. CONFIGURATIONS FOR 12-PHASE OPERATION

Figure 23 shows the step-by-step setup as follows:

1. Connect the CLK_OUT pin of the master IC to the SYNC pin of

the slave IC.

2. Set the master IC’s switching frequency as desired frequency,

set the slave IC’s switching frequency 20% below the master

IC’s.

3. Connect both IC’s COMP, SS and FB pins together.

4. Both IC’s DRIVE_EN pin should be ANDed together to provide

system’s driver enable signal.

5. Since PGOOD, VOUT_OVB and VIN_OVB pins are open drain

structure, both IC’s PGOOD, VOUT_OVB and VIN_OVB pins can

be tied together and use one pull-up resistor to connect to

VCC.

6. If phase dropping function is needed, tie both IC’s IOUT and

MODE pins together.

FN7688 Rev 4.00

September 2, 2014

Page 20 of 22

ISL78220

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest revision.

DATE

REVISION

FN7668.4

CHANGE

September 2, 2014

Updated ESD Rating Section in “Absolute Maximum Ratings” on page 7 as written below:

From: Charge Device Model (Tested per JESD22-C101C) to Charge Device Model (Tested per AEC-Q100-11)

December 24, 2013

December 5, 2012

FN7668.3

FN7668.2

Page 21

- 2nd line of the disclaimer changed from:

"Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted"

to:

"Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality

systems as noted"

Added bulk part (ISL78220ANEZ) to “Ordering Information” table on page 4.

Added the following sentence to “Soft-Start Process for Different Modes” on page 14:

“At the beginning of soft-start, the SS pin voltage will start ramping up from a voltage equaling to FB voltage.

The soft-start period ends when the SS pin voltage reaches the lower power-good threshold that is 80% of

the lower value of VREF2 or 2V.”

In “Phase Selection” on page 12, changed the first sentence to “The ISL78220 can work in 1, 2, 3, 4, 5 or 6-

phase configuration.” Deleted the last sentence, which read “Unused current sense inputs must be left

floating.” Added “For the unused ISENxN and ISENxP, a 1kΩ resistor is recommended to connect ISENxN and

ISENxP, and connect ISENxN to VIN.”

In Table 1 on page 13, added note “Forced minimum ON pulses exists.”

June 28, 2012

FN7668.1

FN7688.0

Update guidance for unused current sense inputs, specified normal operation with inverting MOSFET drivers,

and added pointer to ISL78220EVAL1Z evaluation board.

Changed the symbols of the main switching devices from IGBT to N-MOSFET in “Typical Application 1: 6-

Phase Synchronous Boost Converter with Sense Resistor Current Sensing” on page 5, “Typical Application 2:

6-Phase Standard Boost Converter with DCR Current Sensing” on page 6, Figure 20 on page 17 and Figure

21 on page 17

December 15, 2011

Initial Release.

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com.

You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7688 Rev 4.00

September 2, 2014

Page 21 of 22

ISL78220

Package Outline Drawing

Q44.10x10A

44 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE WITH EXPOSED PAD (EP-TQFP)

Rev 2, 12/10

4

5

12.00

10.00

D

3

A

3

12.00

10.00

4.50±0.1

4

5

B

3

0.80

EXPOSED PAD

4X

0.20 C A-B D

TOP VIEW

4X

0.20 H A-B D

4.50±0.1

BOTTOM VIEW

11/13°

1.20 MAX

0.05

/ / 0.10 C

0.20 M C A-B

D

7

WITH LEAD FINISH

0.37 +0.08/-0.07

C

0.10

SIDE VIEW

SEE DETAIL "A"

0.09/0.20

0.09/0.16

0° MIN.

H

0.35 ±0.05

2

BASE METAL

1.00 ±0.05

0.08

0.05/0.15

0.25

GAUGE

PLANE

0-7°

R. MIN.

(10.00)

0.20 MIN.

0.60 ±0.15

DETAIL "A"

SCALE: NONE

(1.00)

(0.45) TYP

NOTES:

1. All dimensioning and tolerancing conform to ANSI Y14.5-1982.

2. Datum plane H located at mold parting line and coincident

with lead, where lead exits plastic body at bottom of parting line.

3. Datums A-B and D to be determined at centerline between

leads where leads exit plastic body at datum plane H.

10.00

4. Dimensions D1 and E1 do not include mold protrusion.

Allowable mold protrusion is 0.254mm on D1 and E1

dimensions.

(4.50)

5. These dimensions to be determined at datum plane H.

6. Package top dimensions are smaller than bottom dimensions

and top of package will not overhang bottom of package.

7. Dimension b does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm total in excess of the

b dimension at maximum material condition. Dambar cannot

be located on the lower radius or the foot.

(1.50) TYP

8. Controlling dimension: millimeter.

9.

This outline conforms to JEDEC publication 95 registration

MS-026, variation ACB.

(4.50)

TYPICAL RECOMMENDED LAND PATTERN

10. Dimensions in ( ) are for reference only.

11. The corners of the exposed heatspreader may appear different

due to the presence of the tiebars.

FN7688 Rev 4.00

September 2, 2014

Page 22 of 22


型号：	ISL78220
厂家：	RENESAS TECHNOLOGY CORP
描述：	6-Phase Interleaved Boost PWM Controller with Light Load Efficiency Enhancement
文件：	总22页 (文件大小：1256K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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