ISL6844IU-T [RENESAS]
1A SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PDSO8, PLASTIC, MO-187AA, MSOP-8;
| 型号： | ISL6844IU-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1A SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PDSO8, PLASTIC, MO-187AA, MSOP-8 信息通信管理 开关 光电二极管 |
| 文件： | 总17页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
Improved Industry Standard Single-Ended Current Mode PWM Controller
The ISL6840, ISL6841, ISL6842, ISL6843, and
ISL6844 (ISL684x) family of adjustable frequency, low
power, Pulse-Width Modulating (PWM) current mode
Features
• 1A MOSFET gate driver
• 60µA start-up current, 100µA maximum
controllers is designed for a wide range of power
conversion applications including boost, flyback, and
isolated output configurations. Peak current mode
control effectively handles power transients and
provides inherent overcurrent protection.
• 25ns propagation delay current sense to output
• Fast transient response with peak current mode
control
• Adjustable switching frequency to 2MHz
• 20ns rise and fall times with 1nF output load
This advanced BiCMOS design is pin-compatible with
the industry standard 384x family of controllers and
offers significantly improved performance. Features
include low operating current, 60µA start-up current,
adjustable operating frequency to 2MHz, and high
peak current drive capability with 20ns rise and fall
times.
• Trimmed timing capacitor discharge current for
accurate deadtime/maximum duty cycle control
• High bandwidth error amplifier
• Tight tolerance voltage reference over line, load,
and temperature
Part Number
ISL6840
Rising UVLO (V) MAX. Duty Cycle (%)
• Tight tolerance current limit threshold
• Pb-free available (RoHS compliant)
7.0
7.0
100
50
ISL6841
ISL6842
14.4
8.4
100
100
50
Applications
ISL6843
• Telecom and datacom power
• Wireless base station power
• File server power
ISL6844
14.4
Related Literature
For a full list of related documents, visit our website:
• Industrial power systems
• PC power supplies
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
device pages
• Isolated buck and flyback regulators
• Boost regulators
FN9124 Rev.14.00
Jul.22.19
Page 1 of 17
1. Overview
1.1
Typical Applications
CR
5
+3.3V
+1.8V
C
+ C
+ C
16
21
C
15
T
1
R
21
VIN+
C
4
R
CR
3
4
+
+
22
C
C
20
C
17
2
C
CR
19
2
C
5
RETURN
CR
Q
6
R
1
36V to 75V
R
R
17
R
18
16
C
6
C
C
R
1
3
19
U
2
C
1
14
R
4
R
R
15
22
C
13
U
VIN-
3
R
27
R
20
U
4
R
26
COMP
VREF
V
CS
DD
FB
OUT
RTCT
GND
ISL684x
R
6
R10
CR
1
Q
3
C
12
C
8
VR
1
C
11
R
13
Figure 1. 48V Input Dual Output Flyback
R
8
C
10
CR
1
L
1
VIN+
+VOUT
+
C
C
2
3
R
RETURN
Q
4
1
R
5
C
9
C
1
R
R
2
1
U
1
R
7
VREF
VDD
OUT
COMP
FB
C
8
VIN+
R
6
CS
C
4
RTCT
GND
R
3
C
5
C
C
6
7
VIN-
Figure 2. Boost Converter
1.2
Functional Block Diagram
V
5.00V
VREF
VDD
REF
UVLO
Comparator
Enable
V
OK
DD
+
-
-
VREF Fault
+
+
BG
-
VREF
UV Comparator
4.65V 4.80V
GND
A
BG
2.5V
A = 0.5
PWM
Comparator
CS
+
-
100mV
Error
Amplifier
ISL6841/ISL6844
Only
2R
R
1.1V
Clamp
+
-
FB
Q
T
Q
COMP
OUT
VREF
S
R
Q
Q
2.6V
0.7V
Reset
Dominant
ON
Oscillator
Comparator
-
RTCT
+
Clock
UVLO On/Off
7.0/6.6V
14.3/8.8V
8.4/7.2V
P/N
-40, -41
-42, -44
-43
8.4mA
ON
Figure 3. Block Diagram
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
1. Overview
1.3
Ordering Information
Part Number
(Notes 2, 3)
Temp Range
(°C)
Tape and Reel
(Units) (Note 1)
Part Marking
6840 IBZ
40Z
Package
8 Ld SOIC
Pkg. Dwg. #
M8.15
ISL6840IBZ-T
ISL6840IRZ-T
ISL6840IUZ
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
2.5k
6k
-
8 Ld 2x3 DFN
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
L8.2x3
6840Z
M8.118
M8.118
M8.118
ISL6840IUZ-T
6840Z
2.5k
-
ISL6841IUZ (No longer available,
6841Z
recommended replacement: ISL8841AAUZ)
ISL6841IUZ-T (No longer available,
6841Z
-40 to +105
2.5k
8 Ld MSOP
M8.118
recommended replacement: ISL8841AAUZ-T)
ISL6842IBZ
ISL6842IBZ-T
ISL6843IBZ
ISL6843IBZ-T
ISL6843IUZ
ISL6843IUZ-T
6842 IBZ
6842 IBZ
6843 IBZ
6843 IBZ
6843Z
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld MSOP
8 Ld MSOP
8 Ld SOIC
M8.15
M8.15
M8.15
M8.15
M8.118
M8.118
M8.15
2.5k
-
2.5k
-
6843Z
2.5k
ISL6844IBZ (No longer available,
6844 IBZ
recommended replacement: ISL8844AABZ)
ISL6841EVAL3Z (No longer available or
Evaluation Board
supported)
Notes:
1. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J-STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL6840, ISL6841, ISL6842, ISL6843, and ISL6844 device information pages. For more
information about MSL, see TB363.
1.4
Pin Configurations
8 LD SOIC, MSOP
Top View
8 Ld DFN
Top View
COMP
FB
1
2
3
4
8
7
VREF
VDD
OUT
GND
COMP
VREF
1
2
3
4
8
7
6
5
FB
CS
VDD
OUT
GND
CS
6
5
RTCT
RTCT
FN9124 Rev.14.00
Jul.22.19
Page 5 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
1. Overview
1.5
Pin Descriptions
Pin Number
Pin Name
Description
1
2
3
4
COMP
The error amplifier output and the PWM comparator input. The control loop frequency compensation
network is connected between the COMP and FB pins.
FB
CS
The output voltage feedback is connected to the inverting input of the error amplifier through this pin. The
non-inverting input of the error amplifier is internally tied to a reference voltage.
The current sense input to the PWM comparator. The input signal range is nominally 0V to 1.0V and has
an internal offset of 100mV.
RTCT
The oscillator timing control pin. The operational frequency and maximum duty cycle are set by
connecting a resistor, RT, between VREF and this pin and a timing capacitor, CT, from this pin to GND.
The oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0MHz. The
charge time, tC, the discharge time, tD, the switching frequency, f, and the maximum duty cycle, Dmax,
can be calculated from Equations 1, 2, 3 and 4:
t
0.583 RT CT
(EQ. 1)
(EQ. 2)
C
0.0083 RT – 4.3
----------------------------------------------
t
–RT CT ln
D
0.0083 RT – 2.4
(EQ. 3)
(EQ. 4)
f = 1 t + t
C
D
D = t f
C
Figure 7 on page 10 can be used as a guideline in selecting the capacitor and resistor values required for
a given frequency.
5
6
GND
OUT
The power and small signal reference ground for all functions.
The drive output to the power switching device. It is a high current output capable of driving the gate of a
power MOSFET with peak currents of 1.0A.
7
VDD
The power connection for the devices. The total supply current depends on the load applied to OUT. Total
I
DD current is the sum of the operating current and the average output current. Knowing the operating
frequency, f, and the MOSFET gate charge, Qg, the average output current can be calculated in
Equation 5:
I
= Qg f
(EQ. 5)
OUT
To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND
pins as possible.
8
VREF
The 5V reference voltage output. +1.0/-1.5% tolerance over line, load, and operating temperature.
Bypass to GND with a 0.1µF to 3.3µF capacitor to filter this output as needed.
FN9124 Rev.14.00
Jul.22.19
Page 6 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
2. Specifications
2. Specifications
2.1
Absolute Maximum Ratings
Parameter
Minimum
GND - 0.3
GND - 0.3
GND - 0.3
Maximum
+20.0
VDD + 0.3
6.0
Unit
V
Supply Voltage, VDD
OUT
V
Signal Pins
V
Peak GATE Current
1
A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely
impact product reliability and result in failures not covered by warranty.
2.2
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W)
55
θJC (°C/W)
DFN Package (Notes 5, 7)
SOIC Package (Notes 4, 6)
MSOP Package (Notes 4, 6)
6
100
60
62
165
Notes:
4. θJA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for details.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. For θJC, the “case temp” location is taken at the package top center.
7. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features.
See TB379.
Parameter
Maximum Junction Temperature
Maximum Storage Temperature Range
Pb-Free Reflow Profile
Minimum
-55
Maximum
+150
Unit
°C
-65
+150
°C
see TB493
2.3
Recommended Operation Conditions
Parameter
Minimum
Maximum
Unit
Supply Voltage Range (Typical, Note 8)
ISL6840, ISL6841
ISL6843
7.5
9
14
16
18
V
V
V
ISL6842, ISL6844
Temperature Range
ISL684xIx
15
-40
+105
°C
Note:
8. All voltages are with respect to GND
FN9124 Rev.14.00
Jul.22.19
Page 7 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
2. Specifications
2.4
Electrical Specifications
Recommended operating conditions unless otherwise noted. See Functional Block Diagram and Typical Applications schematics. VDD = 15V
(Note 12), Rt = 10kΩ, Ct = 3.3nF, TA = -40°C to +105°C, Typical values are at TA = +25°C. Boldface limits apply across the operating
temperature range, -40°C to +105°C.
Min
Max
Parameter
Undervoltage Lockout
Test Conditions
(Note 9)
Typ
(Note 9)
Unit
START Threshold (ISL6840, ISL6841)
START Threshold (ISL6843)
START Threshold (ISL6842, ISL6844)
STOP Threshold (ISL6840, ISL6841)
STOP Threshold (ISL6843)
STOP Threshold (ISL6842, ISL6844)
Hysteresis (ISL6840, ISL6841)
Hysteresis (ISL6843)
Hysteresis (ISL6842, ISL6844)
Start-Up Current, IDD
Operating Current, IDD
Operating Supply Current, ID
Reference Voltage
6.5
7.8
13.3
6.1
6.7
8.0
7.0
8.4
14.3
6.6
7.2
8.8
0.4
0.8
5.4
60
7.5
9.0
15.3
6.9
7.7
9.6
V
V
V
V
V
V
V
V
V
VDD < START threshold
100
4.0
5.5
µA
mA
mA
(Note 10)
3.3
4.1
Includes 1nF GATE loading
Overall Accuracy
Over line (VDD = 12V to 18V), load, temperature
TA = +125°C, 1000 hours (Note 11)
4.925
5.000
5
5.050
4.85
V
Long Term Stability
mV
V
Fault Voltage
4.40
4.60
50
4.65
VREF Good Voltage
4.80 VREF - 0.05
V
Hysteresis
165
250
mV
mA
mA
Current Limit, Sourcing
Current Limit, Sinking
Current Sense
-20
5
Input Bias Current
VCS = 1V
-1.0
95
1.0
105
1.30
1.03
3.5
µA
mV
V
CS Offset Voltage
VCS = 0V (Note 11)
VCS = 0V (Note 11)
100
1.15
0.97
3.0
COMP to PWM Comparator Offset Voltage
Input Signal, Maximum
Gain, ACS = VCOMP/VCS
CS to OUT Delay
0.80
0.91
2.5
V
0 < VCS < 910mV, VFB = 0V (Note 11)
(Note 11)
V/V
ns
25
40
Error Amplifier
Open-Loop Voltage Gain
Reference Voltage
(Note 11)
60
2.475
-1.0
1.0
90
dB
V
VFB = VCOMP
2.514
-0.2
2.55
1.0
FB Input Bias Current
COMP Sink Current
VFB = 0V
µA
mA
mA
V
VCOMP = 1.5V, VFB = 2.7V
VCOMP = 1.5V, VFB = 2.3V
VFB = 2.3V
COMP Source Current
COMP VOH
-0.4
4.80
0.4
VREF
1.0
COMP VOL
VFB = 2.7V
V
PSRR
Frequency = 120Hz, VDD = 12V to 18V (Note 11)
60
80
dB
Oscillator
Frequency Accuracy
Frequency Variation with VDD
Temperature Stability
Initial, TJ = +25°C
T = +25°C (f18V - f12V)/f12V
(Note 11)
49
52
0.2
-
55
1.0
5
kHz
%
%
FN9124 Rev.14.00
Jul.22.19
Page 8 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
2. Specifications
Recommended operating conditions unless otherwise noted. See Functional Block Diagram and Typical Applications schematics. VDD = 15V
(Note 12), Rt = 10kΩ, Ct = 3.3nF, TA = -40°C to +105°C, Typical values are at TA = +25°C. Boldface limits apply across the operating
temperature range, -40°C to +105°C. (Continued)
Min
Max
Parameter
Amplitude, Peak-to-Peak
Test Conditions
(Note 9)
Typ
1.9
0.7
8.4
(Note 9)
Unit
V
RTCT Discharge Voltage
Discharge Current
Output
V
RTCT = 2.0V
7.2
9.5
mA
Gate VOH
VDD to OUT, IOUT = -200mA
OUT to GND, IOUT = 200mA
COUT = 1nF (Note 11)
1.0
1.0
1.0
20
2.0
2.0
V
V
Gate VOL
Peak Output Current
Rise Time
A
COUT = 1nF (Note 11)
40
40
ns
ns
Fall Time
COUT = 1nF (Note 11)
20
PWM
Maximum Duty Cycle
ISL6840, ISL6842, ISL6843
ISL6841, ISL6844
94
47
96
48
%
%
%
%
Minimum Duty Cycle
ISL6840, ISL6842, ISL6843
ISL6841, ISL6844
0
0
Notes:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
10. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current.
11. Limits established by characterization and are not production tested.
12. Adjust VDD above the start threshold and then lower to 15V.
FN9124 Rev.14.00
Jul.22.19
Page 9 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
3. Typical Performance Curves
3. Typical Performance Curves
1.001
1.000
0.999
1.02
1.01
1.00
0.99
0.98
0.97
0.998
0.997
0.996
0.995
-40
-10
20
50
80
110
-40 -25 -10
5
20 35 50 65 80 95 110
Temperature (°C)
Temperature (°C)
Figure 4. Frequency vs Temperature
Figure 5. Reference Voltage vs Temperature
3
1.002
10
1.000
0.998
0.996
100pF
100
10
1
220pF
330pF
470pF
1.0nF
2.2nF
3.3nF
4.7nF
0.994
-40 -25 -10
5
20 35 50 65 80 95 110
Temperature (°C)
10
20 30 40
50 60
RT (kΩ)
70 80 90 100
Figure 6. EA Reference vs Temperature
Figure 7. Resistance for CT Capacitor Values Given
FN9124 Rev.14.00
Jul.22.19
Page 10 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
4. Functional Description
4. Functional Description
4.1
Features
The ISL684x current mode PWMs make an ideal choice for low-cost flyback and forward topology applications.
With its greatly improved performance over industry standard parts, it is the obvious choice for new designs or
existing designs which require updating.
4.2
Oscillator
The ISL684x family of controllers have a sawtooth oscillator with a programmable frequency range to 2MHz,
which can be programmed with a resistor from VREF and a capacitor to GND on the RTCT pin. (See Figure 7 on
page 10 for the resistor and capacitance required for a given frequency.)
4.3
Soft-Start Operation
Soft-start must be implemented externally. Figure 8 shows one method that clamps the voltage on COMP.
VREF
COMP
GND
Figure 8. Soft-Start
4.4
Gate Drive
The ISL684x family is capable of sourcing and sinking 1A peak current. To limit the peak current through the ICs,
an optional external resistor can be placed between the totem-pole output of the IC (OUT pin) and the gate of the
MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input capacitance.
4.5
Slope Compensation
For applications where the maximum duty cycle is less than 50%, slope compensation can be used to improve
noise immunity, particularly at lighter loads. The amount of slope compensation required for noise immunity is
determined empirically, but is generally about 10% of the full scale current feedback signal. For applications
where the duty cycle is greater than 50%, slope compensation is required to prevent instability. The minimum
amount of slope compensation required corresponds to 1/2 the inductor downslope. Adding excessive slope
compensation, however, results in a control loop that behaves more as a voltage mode controller than as a
current mode controller.
Slope compensation may be added to the CS signal shown in Figure 10 on page 12.
Downslope
Current Sense Signal
Time
Figure 9. Current Sense Downslope
FN9124 Rev.14.00
Jul.22.19
Page 11 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
4. Functional Description
RTCT
VREF
CS
Figure 10. Slope Compensation
4.6
Fault Conditions
A fault condition occurs if VREF falls below 4.65V. When a fault is detected, OUT is disabled. When VREF
exceeds 4.80V, the fault condition clears, and OUT is enabled.
4.7
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A
unique section of the ground plane must be designated for high di/dt currents associated with the output stage.
Bypass V directly to GND with good high-frequency capacitors.
DD
FN9124 Rev.14.00
Jul.22.19
Page 12 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
5. Revision History
5. Revision History
Rev.
Date
Description
14
Jul.22.19
Applied new formatting and template.
Added Related Literature section
Updated Ordering Information table by adding tape and reel information, removing retired parts, and updating
notes.
Removed Note 2.
Updated Theta JA for DFN package changed from 77 to 55.
Updated Theta JC for SOIC package changed from N/A to 60.
Added Note 8 and updated references.
Removed ISL6843C information from document.
Removed ISL6845 information from document.
Updated the disclaimer.
13
12
Feb.18.16
Sep.29.15
-Updated Ordering Information table on page 5
- Updated Ordering Information Table on page 5.
- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD L8.2X3 to latest revision changes are as follow:
-Revision 1 to Revision 2 Changes:
Tiebar Note 5 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or
ends).
FN9124 Rev.14.00
Jul.22.19
Page 13 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
6. Package Outline Drawings
For the most recent package outline drawing, see M8.15.
6. Package Outline Drawings
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL “A”
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
1.35 (0.053)
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
Notes:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
FN9124 Rev.14.00
Jul.22.19
Page 14 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
6. Package Outline Drawings
M8.118
For the most recent package outline drawing, see M8.118.
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.10 C
0.25 - 0.36
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN9124 Rev.14.00
Jul.22.19
Page 15 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
6. Package Outline Drawings
L8.2x3
For the most recent package outline drawing, see L8.2x3.
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 3/15
2.00
A
2X 1.50
6X 0.50
PIN 1
INDEX AREA
B
1
6
PIN #1
INDEX AREA
1.80 +0.10/-0.15
(4X)
0.15
8
4
8X 0.25 +0.07/-0.05
8X 0.40 ±0.10
0.10 M C A B
TOP VIEW
1.65 +0.10/-0.15
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.90 ±0.10
(1.65)
(1.50)
C
BASE PLANE
SEATING PLANE
0.08 C
(8X 0.60)
0.05 MAX
SIDE VIEW
0.20 REF
(1.80)
(2.80)
C
(6X 0.50)
0.05 MAX
DETAIL "X"
(8X 0.25)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
6.
7. Compies to JEDEC MO-229 VCED-2.
FN9124 Rev.14.00
Jul.22.19
Page 16 of 17
1RWLFH
ꢃꢅ 'HVFULSWLRQVꢀRIꢀFLUFXLWVꢆꢀVRIWZDUHꢀDQGꢀRWKHUꢀUHODWHGꢀLQIRUPDWLRQꢀLQꢀWKLVꢀGRFXPHQWꢀDUHꢀSURYLGHGꢀRQO\ꢀWRꢀLOOXVWUDWHꢀWKHꢀRSHUDWLRQꢀRIꢀVHPLFRQGXFWRUꢀSURGXFWVꢀ
DQGꢀDSSOLFDWLRQꢀH[DPSOHVꢅꢀ<RXꢀDUHꢀIXOO\ꢀUHVSRQVLEOHꢀIRUꢀWKHꢀLQFRUSRUDWLRQꢀRUꢀDQ\ꢀRWKHUꢀXVHꢀRIꢀWKHꢀFLUFXLWVꢆꢀVRIWZDUHꢆꢀDQGꢀLQIRUPDWLRQꢀLQꢀWKHꢀGHVLJQꢀRIꢀ\RXUꢀ
SURGXFWꢀRUꢀV\VWHPꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀORVVHVꢀDQGꢀGDPDJHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀ
WKHVHꢀFLUFXLWVꢆꢀVRIWZDUHꢆꢀRUꢀLQIRUPDWLRQꢅ
ꢁꢅ 5HQHVDVꢀ(OHFWURQLFVꢀKHUHE\ꢀH[SUHVVO\ꢀGLVFODLPVꢀDQ\ꢀZDUUDQWLHVꢀDJDLQVWꢀDQGꢀOLDELOLW\ꢀIRUꢀLQIULQJHPHQWꢀRUꢀDQ\ꢀRWKHUꢀFODLPVꢀLQYROYLQJꢀSDWHQWVꢆꢀFRS\ULJKWVꢆꢀRUꢀ
RWKHUꢀLQWHOOHFWXDOꢀSURSHUW\ꢀULJKWVꢀRIꢀWKLUGꢀSDUWLHVꢆꢀE\ꢀRUꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀRUꢀWHFKQLFDOꢀLQIRUPDWLRQꢀGHVFULEHGꢀLQꢀWKLVꢀ
GRFXPHQWꢆꢀLQFOXGLQJꢀEXWꢀQRWꢀOLPLWHGꢀWRꢆꢀWKHꢀSURGXFWꢀGDWDꢆꢀGUDZLQJVꢆꢀFKDUWVꢆꢀSURJUDPVꢆꢀDOJRULWKPVꢆꢀDQGꢀDSSOLFDWLRQꢀH[DPSOHVꢅꢀ
ꢇꢅ 1RꢀOLFHQVHꢆꢀH[SUHVVꢆꢀLPSOLHGꢀRUꢀRWKHUZLVHꢆꢀLVꢀJUDQWHGꢀKHUHE\ꢀXQGHUꢀDQ\ꢀSDWHQWVꢆꢀFRS\ULJKWVꢀRUꢀRWKHUꢀLQWHOOHFWXDOꢀSURSHUW\ꢀULJKWVꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀRUꢀ
RWKHUVꢅ
ꢈꢅ <RXꢀVKDOOꢀQRWꢀDOWHUꢆꢀPRGLI\ꢆꢀFRS\ꢆꢀRUꢀUHYHUVHꢀHQJLQHHUꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢆꢀZKHWKHUꢀLQꢀZKROHꢀRUꢀLQꢀSDUWꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀ
DQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀORVVHVꢀRUꢀGDPDJHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀVXFKꢀDOWHUDWLRQꢆꢀPRGLILFDWLRQꢆꢀFRS\LQJꢀRUꢀUHYHUVHꢀHQJLQHHULQJꢅ
ꢉꢅ 5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDUHꢀFODVVLILHGꢀDFFRUGLQJꢀWRꢀWKHꢀIROORZLQJꢀWZRꢀTXDOLW\ꢀJUDGHVꢊꢀꢋ6WDQGDUGꢋꢀDQGꢀꢋ+LJKꢀ4XDOLW\ꢋꢅꢀ7KHꢀLQWHQGHGꢀDSSOLFDWLRQVꢀIRUꢀ
HDFKꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢀGHSHQGVꢀRQꢀWKHꢀSURGXFWꢌVꢀTXDOLW\ꢀJUDGHꢆꢀDVꢀLQGLFDWHGꢀEHORZꢅ
ꢋ6WDQGDUGꢋꢊ
&RPSXWHUVꢍꢀRIILFHꢀHTXLSPHQWꢍꢀFRPPXQLFDWLRQVꢀHTXLSPHQWꢍꢀWHVWꢀDQGꢀPHDVXUHPHQWꢀHTXLSPHQWꢍꢀDXGLRꢀDQGꢀYLVXDOꢀHTXLSPHQWꢍꢀKRPHꢀ
HOHFWURQLFꢀDSSOLDQFHVꢍꢀPDFKLQHꢀWRROVꢍꢀSHUVRQDOꢀHOHFWURQLFꢀHTXLSPHQWꢍꢀLQGXVWULDOꢀURERWVꢍꢀHWFꢅ
ꢋ+LJKꢀ4XDOLW\ꢋꢊ 7UDQVSRUWDWLRQꢀHTXLSPHQWꢀꢎDXWRPRELOHVꢆꢀWUDLQVꢆꢀVKLSVꢆꢀHWFꢅꢏꢍꢀWUDIILFꢀFRQWUROꢀꢎWUDIILFꢀOLJKWVꢏꢍꢀODUJHꢐVFDOHꢀFRPPXQLFDWLRQꢀHTXLSPHQWꢍꢀNH\ꢀ
ILQDQFLDOꢀWHUPLQDOꢀV\VWHPVꢍꢀVDIHW\ꢀFRQWUROꢀHTXLSPHQWꢍꢀHWFꢅ
8QOHVVꢀH[SUHVVO\ꢀGHVLJQDWHGꢀDVꢀDꢀKLJKꢀUHOLDELOLW\ꢀSURGXFWꢀRUꢀDꢀSURGXFWꢀIRUꢀKDUVKꢀHQYLURQPHQWVꢀLQꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢀRUꢀRWKHUꢀ5HQHVDVꢀ
(OHFWURQLFVꢀGRFXPHQWꢆꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDUHꢀQRWꢀLQWHQGHGꢀRUꢀDXWKRUL]HGꢀIRUꢀXVHꢀLQꢀSURGXFWVꢀRUꢀV\VWHPVꢀWKDWꢀPD\ꢀSRVHꢀDꢀGLUHFWꢀWKUHDWꢀWRꢀ
KXPDQꢀOLIHꢀRUꢀERGLO\ꢀLQMXU\ꢀꢎDUWLILFLDOꢀOLIHꢀVXSSRUWꢀGHYLFHVꢀRUꢀV\VWHPVꢍꢀVXUJLFDOꢀLPSODQWDWLRQVꢍꢀHWFꢅꢏꢆꢀRUꢀPD\ꢀFDXVHꢀVHULRXVꢀSURSHUW\ꢀGDPDJHꢀꢎVSDFHꢀV\VWHPꢍꢀ
XQGHUVHDꢀUHSHDWHUVꢍꢀQXFOHDUꢀSRZHUꢀFRQWUROꢀV\VWHPVꢍꢀDLUFUDIWꢀFRQWUROꢀV\VWHPVꢍꢀNH\ꢀSODQWꢀV\VWHPVꢍꢀPLOLWDU\ꢀHTXLSPHQWꢍꢀHWFꢅꢏꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀ
DQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀGDPDJHVꢀRUꢀORVVHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀDQ\ꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢀWKDWꢀLVꢀ
LQFRQVLVWHQWꢀZLWKꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢆꢀXVHUꢌVꢀPDQXDOꢀRUꢀRWKHUꢀ5HQHVDVꢀ(OHFWURQLFVꢀGRFXPHQWꢅ
ꢑꢅ :KHQꢀXVLQJꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢆꢀUHIHUꢀWRꢀWKHꢀODWHVWꢀSURGXFWꢀLQIRUPDWLRQꢀꢎGDWDꢀVKHHWVꢆꢀXVHUꢌVꢀPDQXDOVꢆꢀDSSOLFDWLRQꢀQRWHVꢆꢀꢋ*HQHUDOꢀ1RWHVꢀIRUꢀ
+DQGOLQJꢀDQGꢀ8VLQJꢀ6HPLFRQGXFWRUꢀ'HYLFHVꢋꢀLQꢀWKHꢀUHOLDELOLW\ꢀKDQGERRNꢆꢀHWFꢅꢏꢆꢀDQGꢀHQVXUHꢀWKDWꢀXVDJHꢀFRQGLWLRQVꢀDUHꢀZLWKLQꢀWKHꢀUDQJHVꢀVSHFLILHGꢀE\ꢀ
5HQHVDVꢀ(OHFWURQLFVꢀZLWKꢀUHVSHFWꢀWRꢀPD[LPXPꢀUDWLQJVꢆꢀRSHUDWLQJꢀSRZHUꢀVXSSO\ꢀYROWDJHꢀUDQJHꢆꢀKHDWꢀGLVVLSDWLRQꢀFKDUDFWHULVWLFVꢆꢀLQVWDOODWLRQꢆꢀHWFꢅꢀ5HQHVDVꢀ
(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀPDOIXQFWLRQVꢆꢀIDLOXUHꢀRUꢀDFFLGHQWꢀDULVLQJꢀRXWꢀRIꢀWKHꢀXVHꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀRXWVLGHꢀRIꢀVXFKꢀ
VSHFLILHGꢀUDQJHVꢅ
ꢒꢅ $OWKRXJKꢀ5HQHVDVꢀ(OHFWURQLFVꢀHQGHDYRUVꢀWRꢀLPSURYHꢀWKHꢀTXDOLW\ꢀDQGꢀUHOLDELOLW\ꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢆꢀVHPLFRQGXFWRUꢀSURGXFWVꢀKDYHꢀVSHFLILFꢀ
FKDUDFWHULVWLFVꢆꢀVXFKꢀDVꢀWKHꢀRFFXUUHQFHꢀRIꢀIDLOXUHꢀDWꢀDꢀFHUWDLQꢀUDWHꢀDQGꢀPDOIXQFWLRQVꢀXQGHUꢀFHUWDLQꢀXVHꢀFRQGLWLRQVꢅꢀ8QOHVVꢀGHVLJQDWHGꢀDVꢀDꢀKLJKꢀUHOLDELOLW\ꢀ
SURGXFWꢀRUꢀDꢀSURGXFWꢀIRUꢀKDUVKꢀHQYLURQPHQWVꢀLQꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢀRUꢀRWKHUꢀ5HQHVDVꢀ(OHFWURQLFVꢀGRFXPHQWꢆꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀ
DUHꢀQRWꢀVXEMHFWꢀWRꢀUDGLDWLRQꢀUHVLVWDQFHꢀGHVLJQꢅꢀ<RXꢀDUHꢀUHVSRQVLEOHꢀIRUꢀLPSOHPHQWLQJꢀVDIHW\ꢀPHDVXUHVꢀWRꢀJXDUGꢀDJDLQVWꢀWKHꢀSRVVLELOLW\ꢀRIꢀERGLO\ꢀLQMXU\ꢆꢀ
LQMXU\ꢀRUꢀGDPDJHꢀFDXVHGꢀE\ꢀILUHꢆꢀDQGꢓRUꢀGDQJHUꢀWRꢀWKHꢀSXEOLFꢀLQꢀWKHꢀHYHQWꢀRIꢀDꢀIDLOXUHꢀRUꢀPDOIXQFWLRQꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢆꢀVXFKꢀDVꢀVDIHW\ꢀ
GHVLJQꢀIRUꢀKDUGZDUHꢀDQGꢀVRIWZDUHꢆꢀLQFOXGLQJꢀEXWꢀQRWꢀOLPLWHGꢀWRꢀUHGXQGDQF\ꢆꢀILUHꢀFRQWUROꢀDQGꢀPDOIXQFWLRQꢀSUHYHQWLRQꢆꢀDSSURSULDWHꢀWUHDWPHQWꢀIRUꢀDJLQJꢀ
GHJUDGDWLRQꢀRUꢀDQ\ꢀRWKHUꢀDSSURSULDWHꢀPHDVXUHVꢅꢀ%HFDXVHꢀWKHꢀHYDOXDWLRQꢀRIꢀPLFURFRPSXWHUꢀVRIWZDUHꢀDORQHꢀLVꢀYHU\ꢀGLIILFXOWꢀDQGꢀLPSUDFWLFDOꢆꢀ\RXꢀDUHꢀ
UHVSRQVLEOHꢀIRUꢀHYDOXDWLQJꢀWKHꢀVDIHW\ꢀRIꢀWKHꢀILQDOꢀSURGXFWVꢀRUꢀV\VWHPVꢀPDQXIDFWXUHGꢀE\ꢀ\RXꢅ
ꢔꢅ 3OHDVHꢀFRQWDFWꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀVDOHVꢀRIILFHꢀIRUꢀGHWDLOVꢀDVꢀWRꢀHQYLURQPHQWDOꢀPDWWHUVꢀVXFKꢀDVꢀWKHꢀHQYLURQPHQWDOꢀFRPSDWLELOLW\ꢀRIꢀHDFKꢀ5HQHVDVꢀ
(OHFWURQLFVꢀSURGXFWꢅꢀ<RXꢀDUHꢀUHVSRQVLEOHꢀIRUꢀFDUHIXOO\ꢀDQGꢀVXIILFLHQWO\ꢀLQYHVWLJDWLQJꢀDSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢀWKDWꢀUHJXODWHꢀWKHꢀLQFOXVLRQꢀRUꢀXVHꢀRIꢀ
FRQWUROOHGꢀVXEVWDQFHVꢆꢀLQFOXGLQJꢀZLWKRXWꢀOLPLWDWLRQꢆꢀWKHꢀ(8ꢀ5R+6ꢀ'LUHFWLYHꢆꢀDQGꢀXVLQJꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀLQꢀFRPSOLDQFHꢀZLWKꢀDOOꢀWKHVHꢀ
DSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀGDPDJHVꢀRUꢀORVVHVꢀRFFXUULQJꢀDVꢀDꢀUHVXOWꢀRIꢀ\RXUꢀQRQFRPSOLDQFHꢀ
ZLWKꢀDSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢅ
ꢄꢅ 5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDQGꢀWHFKQRORJLHVꢀVKDOOꢀQRWꢀEHꢀXVHGꢀIRUꢀRUꢀLQFRUSRUDWHGꢀLQWRꢀDQ\ꢀSURGXFWVꢀRUꢀV\VWHPVꢀZKRVHꢀPDQXIDFWXUHꢆꢀXVHꢆꢀRUꢀVDOHꢀLVꢀ
SURKLELWHGꢀXQGHUꢀDQ\ꢀDSSOLFDEOHꢀGRPHVWLFꢀRUꢀIRUHLJQꢀODZVꢀRUꢀUHJXODWLRQVꢅꢀ<RXꢀVKDOOꢀFRPSO\ꢀZLWKꢀDQ\ꢀDSSOLFDEOHꢀH[SRUWꢀFRQWUROꢀODZVꢀDQGꢀUHJXODWLRQVꢀ
SURPXOJDWHGꢀDQGꢀDGPLQLVWHUHGꢀE\ꢀWKHꢀJRYHUQPHQWVꢀRIꢀDQ\ꢀFRXQWULHVꢀDVVHUWLQJꢀMXULVGLFWLRQꢀRYHUꢀWKHꢀSDUWLHVꢀRUꢀWUDQVDFWLRQVꢅ
ꢃꢂꢅ ,WꢀLVꢀWKHꢀUHVSRQVLELOLW\ꢀRIꢀWKHꢀEX\HUꢀRUꢀGLVWULEXWRUꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢆꢀRUꢀDQ\ꢀRWKHUꢀSDUW\ꢀZKRꢀGLVWULEXWHVꢆꢀGLVSRVHVꢀRIꢆꢀRUꢀRWKHUZLVHꢀVHOOVꢀRUꢀ
WUDQVIHUVꢀWKHꢀSURGXFWꢀWRꢀDꢀWKLUGꢀSDUW\ꢆꢀWRꢀQRWLI\ꢀVXFKꢀWKLUGꢀSDUW\ꢀLQꢀDGYDQFHꢀRIꢀWKHꢀFRQWHQWVꢀDQGꢀFRQGLWLRQVꢀVHWꢀIRUWKꢀLQꢀWKLVꢀGRFXPHQWꢅ
ꢃꢃꢅ 7KLVꢀGRFXPHQWꢀVKDOOꢀQRWꢀEHꢀUHSULQWHGꢆꢀUHSURGXFHGꢀRUꢀGXSOLFDWHGꢀLQꢀDQ\ꢀIRUPꢆꢀLQꢀZKROHꢀRUꢀLQꢀSDUWꢆꢀZLWKRXWꢀSULRUꢀZULWWHQꢀFRQVHQWꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢅ
ꢃꢁꢅ 3OHDVHꢀFRQWDFWꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀVDOHVꢀRIILFHꢀLIꢀ\RXꢀKDYHꢀDQ\ꢀTXHVWLRQVꢀUHJDUGLQJꢀWKHꢀLQIRUPDWLRQꢀFRQWDLQHGꢀLQꢀWKLVꢀGRFXPHQWꢀRUꢀ5HQHVDVꢀ
(OHFWURQLFVꢀSURGXFWVꢅ
ꢎ1RWHꢃꢏ ꢋ5HQHVDVꢀ(OHFWURQLFVꢋꢀDVꢀXVHGꢀLQꢀWKLVꢀGRFXPHQWꢀPHDQVꢀ5HQHVDVꢀ(OHFWURQLFVꢀ&RUSRUDWLRQꢀDQGꢀDOVRꢀLQFOXGHVꢀLWVꢀGLUHFWO\ꢀRUꢀLQGLUHFWO\ꢀFRQWUROOHGꢀ
VXEVLGLDULHVꢅ
ꢎ1RWHꢁꢏ ꢋ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢎVꢏꢋꢀPHDQVꢀDQ\ꢀSURGXFWꢀGHYHORSHGꢀRUꢀPDQXIDFWXUHGꢀE\ꢀRUꢀIRUꢀ5HQHVDVꢀ(OHFWURQLFVꢅ
ꢎ5HYꢅꢈꢅꢂꢐꢃꢀꢀ1RYHPEHUꢀꢁꢂꢃꢒꢏ
Corporate Headquarters
ContactInformation
TOYOSU FORESIA, 3-2-24 Toyosu,
For further information on a product, technology, the most up-to-date
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
version of a document, or your nearest sales office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas Electronics
Corporation. All trademarks and registered trademarks are the property
of their respective owners.
ꢀꢁꢂꢃꢄꢀ5HQHVDVꢀ(OHFWURQLFVꢀ&RUSRUDWLRQꢅꢀ$OOꢀULJKWVꢀUHVHUYHGꢅ
相关型号：
ISL6844IUZ
1A SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PDSO8, ROHS COMPLIANT, PLASTIC, MO-187AA, MSOP-8
RENESAS
ISL6844IUZ-T
1A SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PDSO8, ROHS COMPLIANT, PLASTIC, MO-187AA, MSOP-8
RENESAS
ISL6845IB
1 A SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO8, PLASTIC, MS-012AA, SOIC-8
ROCHESTER
ISL6845IBZ-T
1A SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PDSO8, ROHS COMPLIANT, PLASTIC, MS-012AA, SOIC-8
RENESAS
©2020 ICPDF网 联系我们和版权申明