ISL6845 [INTERSIL]
Improved Industry Standard Single Ended Current Mode PWM Controller; 提高行业标准的单端电流模式PWM控制器
| 型号： | ISL6845 |
| 厂家： | 
Intersil |
| 描述： | Improved Industry Standard Single Ended Current Mode PWM Controller |
| 文件： | 总9页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6842, ISL6843, ISL6844, ISL6845
®
Data Sheet
October 2003
FN9124.1
Improved Indus try Standard Single Ended
Current Mode PWM Controller
Features
• 1A MOSFET gate driver
The ISL6842, ISL6843, ISL6844, ISL6845 family of
adjustable frequency, low power, pulse width modulating
(PWM) current mode controllers is designed for a wide range
of power conversion applications including boost, flyback,
and isolated output configurations. Peak current mode
control effectively handles power transients and provides
inherent over-current protection.
• 60µA startup current, 100µA maximum
• 30ns propagation delay current sense to output
• Fast transient response with peak current mode control
• Adjustable switching frequency to 2MHz
• 20ns rise and fall times with 1nF output load
This advanced BiCMOS design is pin compatible with the
industry standard 384x family of controllers and offers
significantly improved performance. Features include low
operating current, 60µA start-up current, adjustable
operating frequency to 2MHz, and high peak current drive
capability with 20ns rise and fall times.
• Trimmed timing capacitor discharge current for accurate
deadtime/maximum duty cycle control
• High bandwidth error amplifier
• Tight tolerance voltage reference over line, load, and
temperature
• Tight tolerance current limit threshold
Ordering Information
Applications
TEMP. RANGE
PKG.
DWG. #
o
PART NUMBER
ISL6842IB
ISL6842IU
ISL6843IB
ISL6843IU
ISL6844IB
ISL6844IU
ISL6845IB
ISL6845IU
( C)
PACKAGE
8 Ld SOIC
8 Ld MSOP
8 Ld SOIC
8 Ld MSOP
8 Ld SOIC
8 Ld MSOP
8 Ld SOIC
8 Ld MSOP
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
M8.15
M8.118
M8.15
• Industrial Power Systems
• PC Power Supplies
M8.118
M8.15
• Isolated Buck and Flyback Regulators
• Boost Regulators
M8.118
M8.15
M8.118
Pinout
NOTE: Add -T to part number for Tape and Reel packaging.
ISL6842, ISL6843, ISL6844, ISL6845
(8-PIN SOIC, MSOP)
TOP VIEW
PART NUMBER
ISL6842
RISING UVLO
14.4V
MAX. DUTY CYCLE
COMP
FB
1
2
3
4
8
7
VREF
VDD
OUT
GND
100%
100%
50%
ISL6843
8.4V
CS
6
5
ISL6844
14.4V
RTCT
ISL6845
8.4V
50%
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
V
V
VREF
REF
DD
5.00 V
UVLO
COMPARATOR
ENABLE
V
OK
+
-
DD
VREF FAULT
-
+
+
BG
-
V
REF
UV COMPARATOR
4.65V 4.80V
GND
A
2.5 V
BG
A=0.5
PWM
COMPARATOR
CS
+
-
100mV
ERROR
AMPLIFIER
2R
1.1V
CLAMP
ISL6844/5 ONLY
Q
+
-
FB
R
T
Q
COMP
OUT
VREF
S
R
Q
Q
2.6V
0.7V
RESET
DOMINANT
ON
OSCILLATOR
COMPARATOR
-
RTCT
+
CLOCK
P/N
UVLO ON/OFF
8.4mA
ON
14.3 / 8.8V
8.4 / 7.2V
-42, -44
-43, -45
Typical Application - 48V Input Dual Output Flyback
CR5
+3.3V
+1.8V
C21
+ C15
+ C16
T1
R21
VIN+
C4
R3
CR4
+
C22
+
C17
C6
C20
C2
C19
CR2
C5
RETURN
CR6
R1
36-75V
R16
U2
R17
R18
C1
C3
R19
C14
Q1
R4
R22
R15
C13
U3
VIN-
R27
R20
U4
R26
COMP
VREF
V
CS
FB
DD
OUT
RTCT
GND
ISL684x
R6
R10
CR1
Q3
C12
C8
VR1
C11
R13
ISL6842, ISL6843, ISL6844, ISL6845
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
DD
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V
JA
+ 0.3V
DD
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
130
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V
Peak GATE Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
ESD Classification
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V
o
o
Maximum Junction Temperature . . . . . . . . . . . . . . . -55 C to 150 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
o
(SOIC- Lead Tips Only)
Operating Conditions
Temperature Range
ISL684xIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 105 C
Supply Voltage Range (Typical)
o
o
ISL6843/5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V-16V
ISL6842/4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V-18V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. All voltages are with respect to GND.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
o
schematic. V
= 15V (Note 6), Rt = 10kΩ, Ct = 3.3nF, T = -40 to 105 C (Note 3), Typical values are at
DD
A
o
T
= 25 C
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
UNDERVOLTAGE LOCKOUT
START Threshold (ISL6843, ISL6845)
START Threshold (ISL6842, ISL6844)
STOP Threshold (ISL6843, ISL6845)
STOP Threshold (ISL6842, ISL6844)
Hysteresis (ISL6843, ISL6845)
7.8
8.4
14.3
7.2
8.8
0.8
5.4
60
9.0
15.3
7.7
9.6
-
V
V
13.3
6.7
8.0
V
V
-
-
-
-
-
Hysteresis (ISL6842, ISL6844)
-
V
Start-Up Current, I
V
< START Threshold
DD
100
4.0
5.5
µA
mA
mA
DD
Operating Current, I
(Note 4)
3.3
4.1
DD
Operating Supply Current, I
REFERENCE VOLTAGE
Overall Accuracy
Includes 1nF GATE loading
D
Over line (V
temp
= 12V to 18V), load,
4.925
5.000
5.050
V
DD
o
Long Term Stability
Fault Voltage
T
= 125 C, 1000 hours (Note 5)
-
5
4.65
4.80
165
-
-
mV
V
A
4.40
4.60
50
4.85
VREF Good Voltage
Hysteresis
VREF-0.05
V
250
mV
mA
mA
Current Limit, Sourcing
Current Limit, Sinking
CURRENT SENSE
Input Bias Current
CS Offset Voltage
-20
5
-
-
-
V
V
V
= 1V
-1.0
95
-
1.0
105
1.30
1.03
µA
mV
V
CS
CS
CS
= 0V (Note 5)
= 0V (Note 5)
100
1.15
0.97
COMP to PWM Comparator Offset Voltage
Input Signal, Maximum
0.80
0.91
V
4
ISL6842, ISL6843, ISL6844, ISL6845
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
o
schematic. V
= 15V (Note 6), Rt = 10kΩ, Ct = 3.3nF, T = -40 to 105 C (Note 3), Typical values are at
DD
A
o
T
= 25 C (Continued)
A
PARAMETER
/∆V
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Gain, A
= ∆V
0 < V < 910mV, V = 0V
CS FB
2.5
3.0
3.5
V/V
CS
COMP
CS
(Note 5)
CS to OUT Delay
(Note 5)
-
25
40
nS
ERROR AMPLIFIER
Open Loop Voltage Gain
Unity Gain Bandwidth
Reference Voltage
FB Input Bias Current
COMP Sink Current
COMP Source Current
COMP VOH
(Note 5)
(Note 5)
60
3.5
90
-
dB
MHz
V
5
-
V
V
V
V
V
V
= V
2.475
-1.0
1.0
2.500
2.525
FB
FB
COMP
= 0V
-0.2
1.0
µA
mA
mA
V
= 1.5V, V = 2.7V
FB
-
-
-
COMP
COMP
= 1.5V, V = 2.3V
FB
-0.4
4.80
0.4
-
VREF
1.0
-
= 2.3V
-
FB
FB
COMP VOL
= 2.7V
-
V
PSRR
Frequency = 120Hz, V
18V (Note 5)
= 12V to
60
80
dB
DD
OSCILLATOR
o
Frequency Accuracy
Initial, T = 25 C
J
49
52
0.2
-
55
1.0
5
kHz
%
o
Frequency Variation with V
Temperature Stability
Amplitude, Peak to Peak
RTCT Discharge Voltage
Discharge Current
OUTPUT
T = 25 C (F
- F
18V
)/F
12V 12V
-
DD
(Note 5)
-
-
%
1.9
0.7
8.4
-
V
-
-
V
RTCT = 2.0V
7.2
9.5
mA
Gate VOH
V
- OUT, I
OUT
= -200mA
= 200mA
-
-
-
-
-
1.0
1.0
1.0
20
2.0
2.0
-
V
V
DD
Gate VOL
OUT - GND, I
OUT
Peak Output Current
Rise Time
C
C
C
= 1nF (Note 5)
= 1nF (Note 5)
= 1nF (Note 5)
A
OUT
OUT
OUT
40
40
nS
nS
Fall Time
20
PWM
Maximum Duty Cycle
ISL6842, ISL6843
ISL6844, ISL6845
ISL6842, ISL6843
ISL6844, ISL6845
94
47
-
96
48
-
-
-
%
%
%
%
Minimum Duty Cycle
0
0
-
-
NOTES:
3. Specifications at -40 C are guaranteed by design, not production tested.
4. This is the V current consumed when the device is active but not switching. Does not include gate drive current.
o
DD
5. Guaranteed by design, not 100% tested in production.
6. Adjust V
above the start threshold and then lower to 15V.
DD
5
ISL6842, ISL6843, ISL6844, ISL6845
Typical Performance Curves
1.001
1
1.02
1.01
1
0.999
0.998
0.997
0.99
0.98
0.996
0.97
0.995
-40
-10
20
50
80
110
-40 -25 -10
5
20 35 50 65 80 95 110
o
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 1. FREQUENCY vs TEMPERATURE
3
1-10
1.002
CT=
100pF
1
0.998
0.996
100
10
1
220pF
330pF
470pF
1.0nF
2.2nF
3.3nF
4.7nF
0.994
-40 -25 -10
5
20 35 50 65 80 95 110
o
10
20 30 40
50 60
70 80 90 100
TEMPERATURE ( C)
RT (kΩ)
FIGURE 4. RTCT vs FREQUENCY
FIGURE 3. EA REFERENCE vs TEMPERATURE
COMP - COMP is the output of the error amplifier and the
input of the PWM comparator. The control loop frequency
compensation network is connected between the COMP and
FB pins.
Pin Des criptions
RTCT - This is the oscillator timing control pin. The
operational frequency and maximum duty cycle are set by
connecting a resistor, RT, between VREF and this pin and a
timing capacitor, CT, from this pin to GND. The oscillator
produces a sawtooth waveform with a programmable
frequency range up to 2.0MHz. The charge time, T , the
discharge time, T , the switching frequency, f, and the
D
FB - The output voltage feedback is connected to the
inverting input of the error amplifier through this pin. The
non-inverting input of the error amplifier is internally tied to a
reference voltage.
C
maximum duty cycle, Dmax, can be calculated from the
following equations:
CS - This is the current sense input to the PWM comparator.
The range of the input signal is nominally 0 to 1.0V and has
an internal offset of 100mV.
(EQ. 1)
(EQ. 2)
T
T
≈ 0.583 • RT • CT
C
D
GND - GND is the power and small signal reference ground
for all functions.
0.0083 • RT – 4.3
≈ –RT • CT • ln ----------------------------------------------
0.0083 • RT – 2.4
OUT - This is the drive output to the power switching device.
It is a high current output capable of driving the gate of a
power MOSFET with peak currents of 1.0A. This GATE
f = 1 ⁄ (T + T
)
(EQ. 3)
(EQ. 4)
C
D
output is actively held low when V
threshold.
is below the UVLO
DD
D = T • f
C
Figure 4 may be used as a guideline in selecting the
capacitor and resistor values required for a given frequency.
6
ISL6842, ISL6843, ISL6844, ISL6845
V
- V
DD
is the power connection for the device. The total
damps any oscillations caused by the resonant tank of the
parasitic inductances in the traces of the board and the
FET’s input capacitance.
DD
supply current will depend on the load applied to OUT. Total
current is the sum of the operating current and the
I
DD
average output current. Knowing the operating frequency, f,
and the MOSFET gate charge, Qg, the average output
current can be calculated from:
Slope Compens ation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability. The minimum amount of slope
compensation required corresponds to 1/2 the inductor
downslope. Adding excessive slope compensation,
however, results in a control loop that behaves more as a
voltage mode controller than as current mode controller.
(EQ. 5)
I
= Qg × f
OUT
To optimize noise immunity, bypass V
to GND with a
and GND pins as
DD
ceramic capacitor as close to the V
possible.
DD
VREF - The 5.00V reference voltage output. +1.0/-1.5%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 3.3µF capacitor to filter this output as
needed.
Functional Des cription
DOWNSLOPE
Features
CURRENT SENSE SIGNAL
The ISL6842, ISL6843, ISL6844, ISL6845 current mode
PWMs make an ideal choice for low-cost flyback and forward
topology applications. With its greatly improved performance
over industry standard parts, it is the obvious choice for new
designs or existing designs which require updating.
TIME
Os cillator
FIGURE 6. CURRENT SENSE DOWNSLOPE
The ISL6842, ISL6843, ISL6844, ISL6845 controllers have a
sawtooth oscillator with a programmable frequency range to
2MHz, which can be programmed with a resistor from VREF
and a capacitor to GND on the RTCT pin. (Please refer to
Fig. 4 for the resistor and capacitance required for a given
frequency.)
Slope compensation may added to the CS signal in the
following manner.
RTCT
VREF
Soft Start Operation
Soft start must be implemented externally. One method,
illustrated below, clamps the voltage on COMP.
CS
VREF
COMP
GND
FIGURE 7. SLOPE COMPENSATION
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V. When a
Fault is detected OUT is disabled. When VREF exceeds
4.80V, the Fault condition clears, and OUT is enabled.
FIGURE 5. SOFT START
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
Gate Drive
The ISL6842, ISL6843, ISL6844, ISL6845 are capable of
sourcing and sinking 1A peak current. To limit the peak
current through the IC, an optional external resistor may be
placed between the totem-pole output of the IC (OUT pin)
and the gate of the MOSFET. This small series resistor also
currents associated with the output stage. V
should be
DD
bypassed directly to GND with good high frequency
capacitors.
7
ISL6842, ISL6843, ISL6844, ISL6845
Small Outline Plas tic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
8
ISL6842, ISL6843, ISL6844, ISL6845
Mini Small Outline Plas tic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.026 BSC
0.65 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
0
-
o
o
o
o
5
15
5
15
-
a
SIDE VIEW
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
to be determined at Datum plane
-A -
10. Datums
and
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
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