ISL6455IRZ [RENESAS]
1.3 A SWITCHING REGULATOR, 880 kHz SWITCHING FREQ-MAX, PQCC24, 4 X 4 MM, GREEN, PLASTIC, MO-220VGGD-2, QFN-24;
| 型号： | ISL6455IRZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1.3 A SWITCHING REGULATOR, 880 kHz SWITCHING FREQ-MAX, PQCC24, 4 X 4 MM, GREEN, PLASTIC, MO-220VGGD-2, QFN-24 开关 |
| 文件： | 总13页 (文件大小：591K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OBSOLETE PRODUCT
DATASHEET
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
ISL6455, ISL6455A
Triple Output Regulator with Single Synchronous Buck and Dual LDO
FN9196
Rev 1.00
Feb 19, 2014
The ISL6455 is a highly integrated triple output regulator
which provides a single chip solution for FPGAs and wireless
Features
• Fully integrated synchronous buck regulator + dual LDO
chipset power management. The device integrates an
adjustable high efficiency synchronous buck regulator with
two adjustable ultra low noise LDO regulators. Either the
ISL6455 or ISL6455A can be selected based on whether
3.3V ±10% or 5V ±10% is required as an input voltage.
• PWM output voltage adjustable.
- 0.8V to 2.5V with ISL6455 (VIN = 3.3V)
- 0.8V to 3.3V with ISL6455A (VIN = 5.0V)
• High output current. . . . . . . . . . . . . . . . . . . . . . . . . 600mA
The synchronous current mode control PWM regulator with
integrated N- Channel and P-Channel power MOSFET
provides adjustable voltages based on external resistor
setting. Synchronous rectification with internal MOSFETs is
used to achieve higher efficiency and reduced number of
external components. Operating frequency is typically
750kHz, allowing the use of smaller inductor and capacitor
values. The device can be synchronized to an external clock
signal in the range of 500kHz to 1MHz. The PG_PWM
output indicates loss of regulation on PWM output.
• Dual LDO adjustable options
- LDO1, 1.2V to Vin - 0.3V (3.3Vmax). . . . . . . . . . 300mA
- LDO2, 1.2V to Vin - 0.3V (3.3Vmax). . . . . . . . . . 300mA
• Ultra-compact DC/DC converter design
• Stable with small ceramic output capacitors and no load
• High conversion efficiency
• Low shutdown supply current
• Low dropout voltage for LDOs
- LDO1 . . . . . . . . . . . . . . . . . . 150mV (typical) at 300mA
- LDO2 . . . . . . . . . . . . . . . . . . 150mV (typical) at 300mA
The ISL6455 also has two LDO adjustable regulators using
internal PMOS transistors as pass devices. LDO2 features
ultra low noise typically below 30µV
to aid VCO stability.
• Low output voltage noise
RMS
The EN_LDO pin controls LDO1 and LDO2 outputs. The
ISL6455 also integrates a RESET function, which eliminates
the need for additional RESET IC required in WLAN and
other applications. The IC asserts a RESET signal whenever
- <30µV
(typical) for LDO2 (VCO supply)
RMS
• PG_LDO and PG_PWM (PWM and LDO) outputs
• Extensive circuit protection and monitoring features
- PWM overvoltage protection
- Overcurrent protection
the V supply voltage drops below a preset threshold,
IN
keeping it asserted for at least 25ms after V has risen
IN
above the reset threshold. The PG_LDO output indicates
loss of regulation on either of the two LDO outputs. Other
features include overcurrent protection and thermal
shutdown for all of the three outputs. High integration and
the thin Quad Flat No-lead (QFN) package makes ISL6455
an ideal choice for powering FPGAs and small form factor
wireless cards such as PCMCIA, mini-PCI and Cardbus-32.
- Shutdown
- Thermal shutdown
• Integrated RESET output for microprocessor reset
• Proven reference design for total WLAN system solution
• QFN package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
Ordering Information
- Near Chip-Scale package footprint Improves PCB
efficiency and is thinner in Profile
PART NUMBER*
(Note)
PART
TEMP.
PACKAGE
PKG.
MARKING RANGE (°C) (Pb-Free) DWG. #
• Pb-free (RoHS compliant)
ISL6455IRZ
64 55IRZ -40 to +85 24 Ld QFN L24.4x4B
64 55AIRZ -40 to +85 24 Ld QFN L24.4x4B
Applications
ISL6455AIRZ
Add “-TK” or T5K suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
• WLAN cards
- PCMCIA, Cardbus32, MiniPCI cards
- Compact flash cards
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
• Hand-held instruments
Related Literature
• TB363 - Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)
• TB389 - PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages
FN9196 Rev 1.00
Feb 19, 2014
Page 1 of 13
ISL6455, ISL6455A
Pinout
ISL6455, ISL6455A (24 LD QFN)
TOP VIEW
24 23 22 21 20 19
18
17
16
15
14
13
1
2
3
4
5
6
SGND
GND
CT
FB_LDO2
FB_LDO1
CC1
VOUT
RESET
EN
GND_LDO
VOUT1
SYNC
7
8
9
10 11 12
Typical Application Schematic
3.3V
C9
C10
1.0µF
10µF
L1
C8
Vopwm
8.2µH
C7
10µF
0.1µF
R1
10k
Re
Rf
1
22 21 20 19 18
FB_PWM
PG_PWM
VOUT
16
11
12
13
EN_LDO
VOUT2
24
9
SYNC
CC1
EN
Vout2
Vout1
ISL6455
C4
10µF
33nF
C2
GND_LDO
Ra
Rb
5
6
3
4
14
23
VOUT1
3.3V
R3
10k
Rc
FB_LDO1
PG_LDO
C3
10µF
15 17
7
8
10
2
Rd
C1
3.3V
10nF
C6
33nF
C5
4.7µF
NOTE: All capacitors are ceramic.
FN9196 Rev 1.00
Feb 19, 2014
Page 2 of 13
ISL6455, ISL6455A
Functional Block Diagram
VIN_LDO
VIN_LDO
Gm
10nF
CT
VIN_LDO
BAND
GAP
REF
VOUT1
RESET
RESET
+
-
1.2V
VOUT1
LDO1
0
3.3V
10k
WINDOW
COMP.
R
c
POR
POR
10µF
FB_LDO1
PG_LDO
R
d
EN
CC1
CC2
33nF
33nF
Gm
CONTROL
LOGIC
EN_LDO
VOUT2
+
-
GND_LDO
VOUT2
LDO2
THERMAL
SHUTDOWN
+150°C
0
R
R
a
WINDOW
COMP.
10µF
FB_LDO2
b
VIN
VIN
PVCC
3.3V
CURRENT
SENSE
RTN
SGND
SLOPE
COMPENSATION
SOFT-
START
8.2µH
EN
VOUT
PWM
LX
GATE
DRIVE
OVERCURRENT,
OVERVOLTAGE
LOGIC
FB_PWM
EA
GM
10µF
COMPENSATION
PGND
750kHz
OSCILLATOR
R
e
EN
POWER GOOD
PWM
R
f
GND
V
OUT
UVLO
PWM
REFERENCE
0.45V
VOUT
SYNC EN
10k
PG_PWM
3.3V
10k
3.3V
10k
FN9196 Rev 1.00
Feb 19, 2014
Page 3 of 13
ISL6455, ISL6455A
Absolute Maximum Ratings
Thermal Information
Supply Voltage V , PV , V _LDO. . . . . . . .GND -0.3V to +6.0V
CC
Max Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . 600mA
Thermal Resistance (Typical)
(°C/W)
42
(°C/W)
6
JA
JC
IN
IN
24 Ld QFN (Note 1) . . . . . . . . . . . . . . .
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature Range . . . . . . . . .-55°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended operating conditions unless otherwise noted. V = V _LDO = PV = 3.3V for ISL6455 and
IN
IN
CC
5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. T = -40°C to +85° (Note 2),
A
typical values are at T = +25°C.Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless
A
otherwise specified. Temperature limits established by characterization and are not production tested
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
SUPPLY
CC
VIN_PWM Supply Voltage Range
ISL6455
3.0
4.2
3.0
-
3.3
5.0
-
3.6
5.5
5.5
3.1
V
V
ISL6455A
VIN_LDO Supply Voltage Range
V
Operating Supply Current (Note 4) for ISL6455
V
= V _LDO = PV
IN
= 3.3V
2.5
mA
IN
CC
= 10µF, I = 0mA
f
= 750kHz, C
SW
OUT
L
Operating Supply Current (Note 4) for ISL6455A
V
= V _LDO = PV
= 5.0V
-
-
3.5
5
4.5
10
mA
µA
IN
IN
= 750kHz, C
CC
= 10µF, I = 0mA
f
SW
OUT
L
Shutdown Supply Current
ISL6455 and ISL6455A
EN = EN_LDO = GND
Input Bias Current (EN pin)
EN = EN_LDO = GND/V
-1.5
2.55
2.51
3.94
3.78
2.46
2.53
-
1.0
2.65
2.56
4.05
3.89
2.64
2.59
150
20
1.5
2.71
2.61
4.13
3.97
2.82
2.66
-
µA
V
IN
VIN_PWM UVLO Threshold for ISL6455
V
V
V
V
V
V
TR
TF
TR
TF
TR
TF
V
VIN_PWM UVLO Threshold for ISL6455A
V
V
VIN_LDO UVLO Threshold for ISL6455 and
ISL6455A
V
V
Thermal Shutdown Temperature (Note 6)
Thermal Shutdown Hysteresis (Note 6)
SYNCHRONOUS BUCK PWM REGULATOR
Output Voltage
Rising Threshold
°C
°C
-
-
ISL6455
0.8
0.8
-
-
-
-
2.5
3.3
0.9
0.5
V
V
ISL6455A
FB_PWM Initial Voltage Accuracy (Note 7)
FB_PWM Line Regulation
V
= 0.45V, I
OUT
= 3mA, T = -40°C to +85°C
-0.9
-0.5
%
%
REF
A
I
= 3mA, V = PV
IN
= 3.0V - 3.6V (ISL6455)
CC
O
or 4.2V - 5.5V (6455A)
FB_PWM Load Regulation
Peak Output Current Limit
I
= 3mA to 500mA, V = PV = 3.0V - 3.6V
CC
-1.1
-
+1.1
%
O
IN
(ISL6455) or 4.2V - 5.5V (ISL6455A)
700mA
-
-
1300
-
mA
PMOS r
I
= 200mA
OUT
170
m
DS(ON)
FN9196 Rev 1.00
Feb 19, 2014
Page 4 of 13
ISL6455, ISL6455A
Electrical Specifications Recommended operating conditions unless otherwise noted. V = V _LDO = PV = 3.3V for ISL6455 and
IN
IN
CC
5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. T = -40°C to +85° (Note 2),
A
typical values are at T = +25°C.Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless
A
otherwise specified. Temperature limits established by characterization and are not production tested
PARAMETER
TEST CONDITIONS
MIN
TYP
50
MAX
UNITS
m
%
NMOS r
DS(ON)
I
I
= 200mA
-
-
-
-
-
-
OUT
Efficiency
= 200mA, V = 3.3V, V
IN
= 1.8V
93
OUT
OUT
Soft-Start Time
OSCILLATOR
4096 Clock Cycles @ 750kHz
5.5
ms
Oscillator Frequency
T
= -40°C to +85°C
620
500
70
-
750
880
kHz
kHz
%
A
Frequency Synchronization Range (f
SYNC High Level Input Voltage
SYNC Low Level Input Voltage
Sync Input Leakage Current
)
Clock signal on SYNC pin
-
-
1000
SYNC
As % of V
As % of V
-
30
1.0
-
IN
IN
-
%
SYNC = GND or V
-1.0
-
-
A
%
IN
Min Duty Cycle of External Clock Signal (Note 6)
Max Duty Cycle of External Clock Signal (Note 6)
PG_PWM
20
80
-
-
%
Rising Threshold
1.2mA source/sink, FB_PWM vs 0.45V V
+5.5
-10.5
-
8.0
-8.0
0.01
+10.5
-5.5
0.1
%
%
REF
Falling Threshold
FB_PWM vs 0.45V V
REF
Leakage Current
PG_PWM = GND or V
A
IN
LDO1 SPECIFICATIONS
Output Voltage Range
VIN_VLDO > 3.0V
VIN_VLDO > 3.6V
1.2
1.2
-1.5
300
350
-
-
2.7
3.3
1.5
-
V
V
Output Voltage Range
-
FB_LDO1 Voltage Accuracy (Note 7)
Maximum Output Current (Note 6)
Output Current Limit (Note6)
Dropout Voltage (Note 4)
FB_LDO1 Line Regulation
FB_LDO1 Load Regulation
Output Voltage Noise (Note 6)
I
= 10mA
-
%
OUT
V
= 3.6V
-
420
150
-
mA
mA
mV
%/V
%
IN
600
300
0.5
0.5
I
I
I
= 300mA
OUT
OUT
OUT
= 10mA, VIN_LDO = 3.0-5.5V
= 10mA to 300mA
-0.5
-0.5
-
10Hz < f < 100kHz, I
= 10mA
OUT
C
= 2.2µ2F
= 10µF
-
-
65
60
-
-
V
V
OUT
OUT
RMS
RMS
C
LDO2 SPECIFICATIONS
Output Voltage Range
VIN_VLDO > 3.0V
VIN_VLDO > 3.6V
1.2
1.2
-1.5
300
350
-
-
2.7
3.3
1.5
-
V
V
Output Voltage Range
-
FB_LDO2 Voltage Accuracy (Note 7)
Maximum Output Current (Note 6)
Output Current Limit (Note 6)
Dropout Voltage (Note 4)
I
= 10mA
-
%
mA
mA
mV
%/V
%
OUT
V
= 3.6V
-
420
150
-
IN
600
300
0.5
0.5
I
I
I
= 300mA
OUT
OUT
OUT
FB_LDO2 Line Regulation
FB_LDO2 Load Regulation
= 10mA, VIN_LDO = 3.0V - 5.5V
= 10mA to 300mA
-0.5
-0.5
-
FN9196 Rev 1.00
Feb 19, 2014
Page 5 of 13
ISL6455, ISL6455A
Electrical Specifications Recommended operating conditions unless otherwise noted. V = V _LDO = PV = 3.3V for ISL6455 and
IN
IN
CC
5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. T = -40°C to +85° (Note 2),
A
typical values are at T = +25°C.Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless
A
otherwise specified. Temperature limits established by characterization and are not production tested
PARAMETER
TEST CONDITIONS
10Hz < f < 100kHz, I = 10mA
MIN
TYP
MAX
UNITS
Output Voltage Noise (Note 6)
OUT
C
C
= 2.2µF
= 10µF
-
-
30
20
-
-
µV
µV
OUT
RMS
RMS
OUT
ENABLE (EN and (EN_LDO)
EN High Level Input Voltage
EN Low Level Input Voltage
RESET BLOCK SPECIFICATIONS
RESET (reset released)
As % of VIN
As % of VIN
70
-
-
-
-
%
%
30
ISL6455, ISOURCE = 500µA, VIN = 2.90V
0.8 x
-
-
V
V
CC
-
RESET (reset asserted)
RESET Rising Threshold
RESET Falling Threshold
RESET (reset released)
ISL6455, ISINK = 1.2mA, VIN = 2.50V
-
0.3
2.84
2.81
-
V
V
V
V
ISL6455
2.71
2.69
0.8 x
2.77
2.75
-
ISL6455
ISL6455A, ISOURCE = 800µA, VIN = 4.70V
V
CC
-
RESET (reset asserted)
ISL6455A, ISINK = 3.2mA, VIN = 4.10V
-
0.4
V
V
RESET Rising Threshold
ISL6455A
ISL6455A
ISL6455
4.19
4.27
4.24
20
4.35
RESET Falling Threshold
4.16
4.32
V
RESET Threshold Hysteresis
RESET Threshold Hysteresis
RESET Active Timeout Period (Note 5)
POWER GOOD (PG_LDO)
Minimum Input Voltage for Valid PG_LDO
PGOOD Threshold (Rising)
PGOOD Threshold (Falling)
PGOOD Output Voltage Low
PGOOD Output Leakage Current
PWM OUTPUT OVERVOLTAGE
Overvoltage Threshold
-
-
-
-
-
-
mV
mV
ms
ISL6455A
30
C
= 0.01µF
25
T
-
+11
-17
-
1.2
+15
-15
-
-
V
%
%
V
+17
-11
0.4
0.1
FB_LDO vs 1.184V VREF
I
= 1.2mA
OL
PG_LDO = GND or VIN
-
0.01
µA
28
31
34
%
FB_PWM vs 0.45V VREF
NOTES:
3. This is the V current consumed when the device is active but not switching. Does not include gate drive current.
IN
4. The dropout voltage is defined as V - V
IN
, when V
OUT OUT
is 50mV below the value of V
for V = V
IN
+ 0.5V.
OUT
OUT
5. The RESET timeout period is linear with CT at the slope of 2.5ms/nF. Thus, at 10nF (0.01µF) the RESET time is 25ms; at 1000nF (0.1µF) the
RESET time would be 250ms.
6. Limits established by characterization and are not production tested.
7. Add the external feedback resistor mismatch error to get initial V
accuracy.
OUT
FN9196 Rev 1.00
Feb 19, 2014
Page 6 of 13
ISL6455, ISL6455A
PG_LDO Timing Diagram
V
IN
V
V
V
UVLO
UVLO
V
PG
PG
t
RISING
MAX +18%
VFB_LDO
PG_LDO
THRESHOLD
VOLTAGE
FALLING
MIN -17%
t
PG_LDO
OUTPUT
OUTPUT
UNDEFINED
OUTPUT
UNDEFINED
t
NOTE:
8. V
is the minimum input voltage for a valid PG_LDO.
PG
FN9196 Rev 1.00
Feb 19, 2014
Page 7 of 13
ISL6455, ISL6455A
V
- This pin is the output of LDO2. Bypass with a
Pin Descriptions
PVCC - Positive supply for the power (internal FET) stage of
the PWM section.
OUT2
minimum 2.2µF, low ESR capacitor to GND_LDO for stable
operation.
GND_LDO - Ground pin for LDO1 and LDO2.
SGND - Analog ground for the PWM. All internal control
circuits are referenced to this pin.
V
- This pin is the output of LDO1. Bypass with a
OUT1
minimum 2.2µF, low ESR capacitor to GND_LDO for stable
operation.
EN - The PWM controller is enabled when this pin is HIGH,
and disabled when the pin is pulled LOW. It is a CMOS
logic-level input (referenced to V ).
IN
PGND - Power ground for the PWM controller stage.
V
_LDO - This is the input voltage pin for LDO1 and LDO2.
V
- This I/O pin senses the output voltage of the PWM
IN
OUT
converter for the purpose of detecting the over and
undervoltage conditions.
EN_LDO - LDO1 and LDO2 are enabled when this pin is
HIGH, and disabled when the pin is pulled LOW. It is a
CMOS logic-level input (referenced to V ).
IN
PG_PWM - This pin is an active pull-down able to sink 1mA
(min). This output is HIGH IMPEDANCE when V
within ±8% (typical). For pull-up, add a resistor
approximately 10k from PG_PWM to VIN
is
OUT
CT - Timing capacitor pin to set the 25ms minimum pulse
width for the RESET signal.
RESET - This pin is the output of the reset supervisory
circuit, which monitors VIN_PWM. The IC asserts a RESET
signal whenever the supply voltage drops below a preset
threshold. It is kept asserted for a minimum of 25ms after
FB_LDO1 and FB_LDO2 - These pins are used to set the
LDO output with the proper selection of resistors. i.e. Ra and
Rb for LDO1 and Rc and Rd for LDO2. Resistors should be
chosen to provide a minimum current of 200µA load for each
LDO output.
V
(V ) has risen above the reset threshold. The output is
CC IN
push-pull. The device will continue to operate until V drops
IN
below the UVLO threshold.
LX - The LX pin is the switching node of synchronous buck
converter, connected internally at the junction point of the
upper MOSFET source and lower MOSFET drain. Connect
this pin to the output inductor.
When EN = LOW then RESET = HIGH and the moment EN
is made HIGH the RESET will pulse LOW for a period of
25ms minimum (VIN > Reset threshold). If VIN < reset
threshold then it will switch low and stay low for a period of
25ms after VIN_PWM crosses the reset threshold.
V
- This pin is the power supply for the PWM controller
IN
stage and must be closely decoupled to ground.
PG_LDO - This is a high impedance open drain output that
provides the status of both LDOs. When either of the outputs
are out of regulation, PG_LDO goes LOW. Add a pull-up
resistor approximately 10k from PG_LDO to VIN.
SYNC - This is the external clock synchronization input. The
device can be synchronized to 500kHz to 1MHz switching
frequency. If unused then it should be tied to GND or VCC
GND - Tie this pin to the ground plane with a low impedance,
CC1 - This is the compensation capacitor connection for
LDO1. Connect a 0.033µF capacitor from CC1 to
GND_LDO.
shortest possible path.
FB_PWM- This is used to set the value of the output voltage
of the PWM with external resistors Re and Rf.
CC2 - This is the compensation capacitor connection for
LDO2. Connect a 0.033µF capacitor from CC2 to
GND_LDO.
FN9196 Rev 1.00
Feb 19, 2014
Page 8 of 13
ISL6455, ISL6455A
on the SYNC pin is detected for a duration of two internal
1.3µs clock cycles.
Functional Description
The ISL6455 is a 3-in-1 multi-output regulator designed for
FPGA and wireless chipset power applications. The device
integrates a single synchronous buck regulator with dual
LDOs. The PWM output can be set by choosing appropriate
values for Re and Rf. At a setting of 1.8V the synchronous
buck regulator provides for an efficiency greater than 92%.
The LDO1 can be set with resistor pair Rc and Rd. The
LDO2 can be set with the resistor pair Ra and Rb.
Soft-Start
As the EN (Enable) pin goes high, the soft-start function will
generate an internal voltage ramp. This causes the start-up
current to slowly rise preventing output voltage overshoot
and high in-rush currents. The soft-start duration is typically
5.5ms with 750kHz switching frequency. When the soft-start
is completed, the error amplifier will be connected directly to
the internal voltage reference. The SYNC input is ignored
during soft-start.
Undervoltage lock-out (UVLO) prevents the converter from
turning on when the input voltage is less than 2.6V typical.
Additional blocks include output overcurrent protection,
thermal sensor, PGOOD detectors, RESET function and
shutdown logic.
Enable PWM
Logic low on EN pin forces the PWM section into shutdown.
In shutdown all the major blocks of the PWM including power
switches, drivers, voltage reference, and oscillator are
turned off.
Synchronous Buck Regulator
The synchronous buck regulator with integrated N-Channel
and P-Channel power MOSFETs and external voltage
setting resistors provides for adjustable voltages from the
PWM. Synchronous rectification with internal MOSFETs is
used to achieve higher efficiency and reduced number of
external components. Operating frequency is typically
750kHz allowing the use of smaller inductor and capacitor
values. The device can be synchronized to an external clock
signal in the range of 500kHz to 1MHz. The PG_PWM
output indicates loss of regulation on PWM output.
Power Good (PG_PWM)
When chip is enabled, this output is asserted HIGH, when
V
is within 8% of V value and active low outside
OUT
OPWM
this range. When the PWM is disabled, the output is active
low.
Leave the PG_PWM pin unconnected when not used.
PWM Overvoltage and Overcurrent Protection
The PWM output current is sampled at the end of each PWM
cycle. Should it exceed the overcurrent limit, a 4-bit up/down
counter counts up two LSB. Should it not be in overcurrent,
the counter counts down one LSB, (but the counter will not
"rollover" or count below 0000). If > 33% of the PWM cycles
go into overcurrent, the counter rapidly reaches count 1111
and the PWM output is shut down and the soft-start counter
is reset. After 16 clocks the PWM, output is enabled and the
SS cycle is started.
The PWM architecture uses a peak current mode control
scheme with internal slope compensation. At the beginning
of each clock cycle, the high side P-channel MOSFET is
turned on. The current in the inductor ramps up and is
sensed via an internal circuit. The error amplifier sets the
threshold for the PWM comparator. The high side switch is
turned off when the sensed inductor current reaches this
threshold. After a minimum dead time preventing shoot
through current, the low side N-Channel MOSFET will be
turned on, and the current ramps down again. As the clock
cycle is completed, the low side switch will be turned off and
the next clock cycle starts.
If V
OUT
exceeds the overvoltage limit for 32 consecutive
clock cycles, the PWM output is shut off and the SS counters
reset. The chip waits for the output voltage to go below
undervoltage (8% below nominal) then goes through two
dummy soft-start cycles (PWM disabled for 2 SS cycles =
11ms) and then starts a normal soft-start cycle.
The control loop is internally compensated reducing the
amount of external components.
The switch current is internally sensed and the maximum
peak current limit is 1300mA.
PG_LDO
PG_LDO is an open drain pulldown NMOS output that will
sink 1mA at 0.4V maximum. It goes to the active low state if
either LDO output is out of regulation by a value greater than
15%. When the LDO is disabled, the output is active low.
Synchronization
The typical operating frequency for the converter is 750kHz
if no clock signal is applied to SYNC pin. It is possible to
synchronize the converter to an external clock within a
frequency range from 500kHz to 1MHz. The device
LDO Regulators
Each LDO consists of a 1.184V reference, error amplifier,
MOSFET driver, P-Channel pass transistor, and dual-mode
comparator. The voltage is set by means of two resistors: the
Ra and Rb for LDO2 and Rc and Rd for LDO1. The 1.184V
band gap reference is connected to the error amplifier’s
inverting input. The error amplifier compares this reference
automatically detects the rising edge of the first clock and
will synchronize immediately to the external clock. If the
clock signal is stopped, the converter automatically switches
back to the internal clock and continues operation without
interruption. The switch-over will be initiated if no rising edge
FN9196 Rev 1.00
Feb 19, 2014
Page 9 of 13
ISL6455, ISL6455A
to the selected feedback voltage and amplifies the
difference. The MOSFET driver reads the error signal and
applies the appropriate drive to the P-Channel pass
transistor. If the feedback voltage is lower than the reference
voltage, the pass transistor gate is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the
pass transistor gate is driven higher, allowing less current to
pass to the output.
can be shorted to ground without damaging the part due to
the current limit and thermal protection features.
Thermal Overload Protection
Thermal overload protection limits total power dissipation in
the ISL6455, ISL6455A. When the junction temperature (T )
J
exceeds +150°C, the thermal sensor sends a signal to the
shutdown logic, turning off the pass transistor and allowing
the IC to cool. The pass transistor turns on again after the
IC’s junction temperature typically cools by +20°C, resulting
in an intermittent output condition during continuous thermal
overload. Thermal overload protection protects the ISL6455,
ISL6455A against fault conditions. For continuous operation,
the absolute maximum junction temperature rating of
+150°C in not to be exceeded.
Internal P-Channel Pass Transistors
Both the LDO Regulators in ISL6455 feature a typical 0.5
r
P-channel MOSFET pass transistor. This provides
DS(on)
several advantages over similar designs using PNP bipolar
pass transistors. The P-Channel MOSFET requires no base
drive, which reduces quiescent current considerably. PNP
based regulators waste considerable current in dropout
when the pass transistor saturates. They also use high base
drive currents under large loads. The ISL6455 does not have
these drawbacks.
Operating Region and Power Dissipation
The maximum power dissipation of ISL6455 depends on the
thermal resistance of the IC package and circuit board, the
temperature difference between the die junction and ambient
air, and the rate of air flow. The power dissipated in the
device is:
Integrated RESET for MAC/Baseband Processors
The ISL6455 includes a microprocessor supervisory block.
This block eliminates an extra RESET IC and external
components needed in wireless chipset applications. This
block performs a single function; it asserts a RESET signal
whenever the VIN_PWM supply voltage decreases below a
preset threshold, and keeps it asserted for a programmable
time period set by the external capacitor CT.
PT = P1 + P2 + P3, where:
P1 = I
P2 = I
P3 = I
x V x n, n is the efficiency of the PWM
OUT1
OUT1
(V – V
)
OUT2 IN OUT2
(V - V
OUT3 IN OUT3
)
UVLO Reset threshold is always lower than the RESET
The maximum power dissipation is:
= (T – T )/
threshold. This insures that as V falls, the reset goes low
IN
P
max
jmax
A
JA
before the LDOs and PWM are shut off.
Where T
= +150°C, T = ambient temperature, and
jmax
A
JA
Integrator Circuitry
is the thermal resistance from the junction to the surrounding
Both ISL6455 LDO Regulators use external 33nF
compensation capacitors for minimizing load and line
regulation errors and for lowering output noise. When the
output voltage shifts due to varying load current or input
voltage, the integrator capacitor voltage is raised or lowered
to compensate for the systematic offset at the error amplifier.
Compensation is limited to ±5% to minimize transient
overshoot when the device goes out of dropout, current limit,
or thermal shutdown.
environment.
The ISL6455, ISL6455A package feature an exposed
thermal pad on its underside. This pad lowers the thermal
resistance of the package by providing a direct heat
conduction path from the die to the PC board. Additionally,
the ISL6455 and ISL6455A ground (GND_LDO and PGND)
performs the dual function of providing an electrical
connection to system ground and channeling heat away.
Connect the exposed bottom pad direct to the GND_LDO
ground plane.
Shutdown
Driving the EN_LDO pin low will put LDO1 and LDO2 into
the shutdown mode. Driving the EN pin low will put the PWM
into shutdown mode. Pulling both the EN and EN_LDO pins
low simultaneously, puts the ISL6455, ISL6455A in a
shutdown mode, and supply current drops to 15µA typical.
Application Information
LDO Regulator Capacitor Selection and Regulator
Stability
Capacitors are required at the ISL6455, ISL6455A LDO
regulators’ input and output for stable operation over the
entire load range and the full temperature range. Use >1µF
Protection Features for the LDOs
Current Limit
capacitor at the input of LDO regulators, V _LDO pins. The
IN
The ISL6455 and ISL6455A monitor and control the pass
transistor’s gate voltage to limit the output current. The
current limit for both LDO1 and LDO2 is 330mA. The output
input capacitor lowers the source impedance of the input
supply. Larger capacitor values and lower ESR provide
better PSRR and line transient response. The input
FN9196 Rev 1.00
Feb 19, 2014
Page 10 of 13
ISL6455, ISL6455A
capacitor must be located at a distance of not more than 0.5
The overall output ripple voltage is the sum of the voltage spike
caused by the output capacitor ESR plus the voltage ripple
caused by charge and discharging the output capacitor as
shown in Equation 2:
inches from the V pins of the IC and returned to a clean
IN
analog ground. Any good quality ceramic capacitor can be
used as an input capacitor.
V
O
The output capacitor must meet the requirements of minimum
amount of capacitance and ESR for both LDOs. The ISL6455
is specifically designed to work with small ceramic output
capacitors. The output capacitor’s ESR affects stability and
output noise. Use an output capacitor with an ESR of 50m or
less to insure stability and optimum transient response. For
stable operation, a ceramic capacitor, with a minimum value of
1 – -------
V
I
1
(EQ. 2)
-----------------
V = V
O
------------------------- + ESR
O
L f
8 C f
O
Where the highest output voltage ripple occurs at the highest
input voltage.
3.3µF, is recommended for V
and 3.3µF is recommended for V
for 300mA output current,
at 300mA load current.
TABLE 2. RECOMMENDED CAPACITORS
OUT1
OUT2
CAPACITOR
VALUE
VENDOR PART
NUMBER
There is no upper limit to the output capacitor value. A larger
capacitor can reduce noise and improve load transient
response, stability and PSRR. A higher value output capacitor
(10µF) is recommended for LDO2 when used to power VCO
circuitry in wireless chipsets. The output capacitor should be
ESR/m
COMMENTS
10µF
<50
TDK
C2012X5R0J106M
Ceramic
INPUT CAPACITOR SELECTION
located very close to V
pins to minimize impact of PC
OUT
Because of the nature of the buck converter having a pulsating
input current, a low ESR input capacitor is required for best
input voltage filtering and minimizing the interference with
other circuits caused by high input voltage spikes.
board inductances and the other end of the capacitor should
be returned to a clean analog ground.
PWM Regulator Component Selection
INDUCTOR SELECTION
The input capacitor should have a minimum value of 10µF and
can be increased without any limit for better input voltage
filtering. The input capacitor should be rated for the maximum
input ripple current calculated as shown in Equation 3:
A 8.2µH typical output inductor is used with the ISL6455 and a
12µH typical with the ISL6455A PWM section. Values less than
this may cause stability problems because of the internal
compensation of the regulator. The important parameters of
the inductor that need to be considered are the current rating
of the inductor and the DC resistance of the inductor. The DC
resistance of the inductor will influence directly the efficiency of
the converter. Therefore, an inductor with lowest DC resistance
should be selected for highest efficiency. In order to avoid
saturation of the inductor, the inductor should be rated at least
for the maximum output current plus the inductor ripple current.
(See Table 1).
V
V
O
O
(EQ. 3)
-------
I
= I
Omax
1 – -------
RMS
V
I
V
I
The worst case RMS ripple current occurs at D = 0.5.
Ceramic capacitors show good performance because of their
low ESR value, and because they are less sensitive to voltage
transients, compared to tantalum capacitors.
TABLE 1. RECOMMENDED INDUCTORS
Place the input capacitor as close as possible to the input pin
of the IC for best performance.
OUTPUT INDUCTOR
VENDOR PART
NUMBER
CURRENT
VALUE
COMMENTS
600mA
8.2µH
Coilcraft
MSS6122-822MX
ISL6455
Output Voltage Setting
The equations for the Output voltages are shown in Equation
4:
600mA
12µH
Coilcraft
MSS6122-123MX
ISL6455A
0.45
Rf
-----------
VOUT =
VOUT1 =
VOUT2 =
Re + Rf
OUTPUT CAPACITOR SELECTION
For the best performance, a low ESR output capacitor is
needed. If an output capacitor is selected with an ESR value
120m, its RMS ripple current rating will always meet the
application requirements. The RMS ripple current is calculated
as shown in Equation 1:
1.184
(EQ. 4)
--------------
Ra + Rb
Rc + Rd
Rb
1.184
--------------
Rd
V
O
1 – -------
V
(EQ. 1)
1
I
----------------- ----------------
I
= V
O
RMSC
L f
O
2
3
FN9196 Rev 1.00
Feb 19, 2014
Page 11 of 13
ISL6455, ISL6455A
The output resistors should be selected so that the minimum
output load is about 200µA.
Layout Considerations
As for all switching power supplies, the layout is an important
step in the design of ISL6455, ISL6455A based power
supply due to the high switching frequency and low noise
LDO implementations.
Allocate two board levels as ground planes, with many vias
between them to create a low impedance, high-frequency
plane. Tie all the device ground pins through multiple vias
each to this ground plane, as close to the device as possible.
Also tie the exposed pad on the bottom of the device to this
ground plane.
Use wide and short traces for the high current paths. The
input capacitor should be placed as close as possible to the
IC pins as well as the inductor and output capacitor. Use a
common ground node to minimize the effects of ground
noise.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN9196 Rev 1.00
Feb 19, 2014
Page 12 of 13
ISL6455, ISL6455A
Package Outline Drawing
L24.4x4B
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06
4X
2.5
4.00
A
20X
0.50
PIN #1 CORNER
(C 0 . 25)
B
19
24
PIN 1
INDEX AREA
1
18
2 . 34 ± 0 . 15
13
0.15
(4X)
12
24X 0 . 4 ± 0 . 1
7
0.10 M C
A B
TOP VIEW
+ 0 . 07
24X 0 . 23
4
- 0 . 05
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
0 . 90 ± 0 . 1
C
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08
SIDE VIEW
C
(
2 . 34 )
( 20X 0 . 5 )
5
C
0 . 2 REF
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN9196 Rev 1.00
Feb 19, 2014
Page 13 of 13
相关型号：
ISL6455IRZ-T5K
1.3 A SWITCHING REGULATOR, 880 kHz SWITCHING FREQ-MAX, PQCC24, 4 X 4 MM, ROHS COMPLIANT, PLASTIC, MO-220VGGD-2, QFN-24
RENESAS
ISL6455IRZ-TK
1.3 A SWITCHING REGULATOR, 880 kHz SWITCHING FREQ-MAX, PQCC24, 4 X 4 MM, GREEN, PLASTIC, MO-220VGGD-2, QFN-24
RENESAS
ISL6455IRZ-TK
1.3 A SWITCHING REGULATOR, 880 kHz SWITCHING FREQ-MAX, PQCC24, 4 X 4 MM, GREEN, PLASTIC, MO-220VGGD-2, QFN-24
ROCHESTER
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