ISL6455IRZ-TK [ROCHESTER]

1.3 A SWITCHING REGULATOR, 880 kHz SWITCHING FREQ-MAX, PQCC24, 4 X 4 MM, GREEN, PLASTIC, MO-220VGGD-2, QFN-24;


型号：	ISL6455IRZ-TK
厂家：	Rochester Electronics
描述：	1.3 A SWITCHING REGULATOR, 880 kHz SWITCHING FREQ-MAX, PQCC24, 4 X 4 MM, GREEN, PLASTIC, MO-220VGGD-2, QFN-24 开关
文件：	总16页 (文件大小：1086K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6455, ISL6455A

Data Sheet

December 21, 2005

FN9196.0

Triple Output Regulator with Single

Synchronous Buck and Dual LDO

Features

• Fully integrated synchronous buck regulator + dual LDO

The ISL6455 is a highly integrated triple output regulator

which provides a single chip solution for FPGAs and wireless

chipset power management. The device integrates a high

efficiency synchronous buck regulator (adjustable) with two

ultra low noise LDO regulators (adjustable). Either the

ISL6455 or ISL6455A can be selected based on whether

3.3V ±10% or 5V ±10% is required as an input voltage.

• PWM output voltage adjustable.

- 0.8V to 2.5V with ISL6455 (VIN = 3.3V)

- 0.8V to 3.3V with ISL6455A (VIN = 5.0V)

• High output current. . . . . . . . . . . . . . . . . . . . . . . . . 600mA

• Dual LDO adjustable options

- LDO1, 1.2V to Vin-0.3V (3.3Vmax). . . . . . . . . . . 300mA

- LDO2, 1.2V to Vin-0.3V (3.3Vmax). . . . . . . . . . . 300mA

The synchronous current mode control PWM regulator with

integrated N- and P-channel power MOSFET provides

adjustable voltages based on external resistor setting.

Synchronous rectification with internal MOSFETs is used to

achieve higher efficiency and reduced number of external

components. Operating frequency is typically 750kHz

allowing the use of smaller inductor and capacitor values.

The device can be synchronized to an external clock signal

in the range of 500kHz to 1MHz. The PG_PWM output

indicates loss of regulation on PWM output.

• Ultra-compact DC/DC converter design

• Stable with small ceramic output capacitors and no load

• High conversion efficiency

• Low shutdown supply current

• Low dropout voltage for LDOs

- LDO1 . . . . . . . . . . . . . . . . . . 150mV (typical) at 300mA

- LDO2 . . . . . . . . . . . . . . . . . . 150mV (typical) at 300mA

• Low output voltage noise

The ISL6455 also has two LDO adjustable regulators using

internal PMOS transistors as pass devices. LDO2 features

- <30µV

(typical) for LDO2 (VCO supply)

RMS

• PG_LDO and PG_PWM (PWM and LDO) outputs

ultra low noise typically below 30µV

to aid VCO stability.

RMS

The EN_LDO pin controls LDO1 and LDO2 outputs. The

ISL6455 also integrates a RESET function, which eliminates

the need for additional RESET IC required in WLAN and

other applications. The IC asserts a RESET signal whenever

• Extensive circuit protection and monitoring features

- PWM overvoltage protection

- Overcurrent protection

- Shutdown

- Thermal shutdown

the V supply voltage drops below a preset threshold,

keeping it asserted for at least 25ms after V has risen

• Integrated RESET output for microprocessor reset

• Proven reference design for total WLAN system solution

• QFN package

- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat

No Leads - Product Outline

above the reset threshold. The PG_LDO output indicates

loss of regulation on either of the two LDO outputs. Other

features include overcurrent protection and thermal

shutdown for all the three outputs.

High integration and the thin Quad Flat No-lead (QFN)

package makes ISL6455 an ideal choice for powering

FPGAs and small form factor wireless cards such as

PCMCIA, mini-PCI and Cardbus-32.

- Near Chip-Scale package footprint Improves PCB

efficiency and is thinner in Profile

• Pb-free plus anneal available (RoHS compliant)

Ordering Information

Applications

• WLAN cards

PART NUMBER*

(Note)

PART

TEMP.

PACKAGE

PKG.

MARKING RANGE (°C) (Pb-Free) DWG. #

- PCMCIA, Cardbus32, MiniPCI cards

- Compact flash cards

ISL6455IRZ

6455IRZ

-40 to 85 24 Ld QFN L24.4x4B

ISL6455AIRZ

6455AIRZ

• Hand-held instruments

Add “-TK” or T5K suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

Related Literature

• TB363 - Guidelines for Handling and Processing Moisture

Sensitive Surface Mount Devices (SMDs)

• TB389 - PCB Land Pattern Design and Surface Mount

Guidelines for QFN Packages

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6455, ISL6455A

Pinout

ISL6455, ISL6455A (QFN)

TOP VIEW

24 23 22 21 20 19

SGND

GND

FB_LDO2

FB_LDO1

CC1

VOUT

RESET

GND_LDO

VOUT1

SYNC

10 11 12

Typical Application Schematic

3.3V

1.0µF

C10

10µF

Vopwm

8.2µH

10µF

0.1µF

10k

22 21 20

ISL6455

19 18

FB_PWM

PG_PWM

VOUT

EN_LDO

VOUT2

SYNC

CC1

Vout2

Vout1

10µF

33nF

3.3V

GND_LDO

VOUT1

10k

FB_LDO1

PG_LDO

10µF

15 17

3.3V

10nF

4.7µF

NOTE: All capacitors are ceramic.

33nF

FN9196.0

December 21, 2005

ISL6455, ISL6455A

Functional Block Diagram

VIN_LDO

10nF

VIN_LDO

BAND

GAP

REF

VOUT1

RESET

1.2V

VOUT1

LDO1

3.3V

10k

WINDOW

COMP.

POR

10µF

FB_LDO1

PG_LDO

CC1

CC2

33nF

CONTROL

LOGIC

EN_LDO

VOUT2

GND_LDO

VOUT2

LDO2

THERMAL

SHUTDOWN

WINDOW

COMP.

150°C

10µF

FB_LDO2

VIN

PVCC

3.3V

CURRENT

SENSE

RTN

SGND

SLOPE

SOFT-

START

COMPENSATION

8.2µH

VOUT

PWM

GATE

OVERCURRENT,

OVERVOLTAGE

LOGIC

FB_PWM

DRIVE

10µF

COMPENSATION

PGND

750kHz

OSCILLATOR

POWER GOOD

PWM

GND

OUT

UVLO

PWM

REFERENCE

0.45V

VOUT

SYNC EN

10k

PG_PWM

3.3V

10k

3.3V

10k

FN9196.0

December 21, 2005

ISL6455, ISL6455A

Absolute Maximum Ratings (Note 1)

Thermal Information

Thermal Resistance (Typical)

24 Ld QFN (Note 1) . . . . . . . . . . . . . . .

Supply Voltage V , PV , V _LDO. . . . . . . .GND -0.3V to +6.0V

(°C/W)

Max Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . 600mA

Maximum Junction Temperature (Plastic Package) .-55°C to 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(Lead Tips Only)

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications Recommended operating conditions unless otherwise noted. V = V _LDO = PV = 3.3V for ISL6455 and

5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. T = -40°C to 85° (Note 2), typical

values are at T = 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

SUPPLY

VIN_PWM Supply Voltage Range

ISL6455

3.0

4.2

3.0

3.3

5.0

3.6

5.5

3.1

ISL6455A

VIN_LDO Supply Voltage Range

Operating Supply Current (Note 3) for ISL6455

Operating Supply Current (Note 3) for ISL6455A

= V _LDO = PV

IN CC

= 3.3V

2.5

= 750kHz, C = 10µF, I = 0mA

OUT

= V _LDO = PV

= 5.0V

3.5

4.5

IN CC

= 750kHz, C = 10µF, I = 0mA

OUT

Shutdown Supply Current

ISL6455 and ISL6455A

EN = EN_LDO = GND

µA

Input Bias Current (EN pin)

EN = EN_LDO = GND/V

-1.5

2.55

2.51

3.94

3.78

2.46

2.53

1.0

2.65

2.56

4.05

3.89

2.64

2.59

150

1.5

2.71

2.61

4.13

3.97

2.82

2.66

µA

VIN_PWM UVLO Threshold for ISL6455

VIN_PWM UVLO Threshold for ISL6455A

VIN_LDO UVLO Threshold for ISL6455 and

ISL6455A

Thermal Shutdown Temperature (Note 6)

Thermal Shutdown Hysteresis (Note 6)

SYNCHRONOUS BUCK PWM REGULATOR

Output Voltage

Rising Threshold

°C

ISL6455

0.8

2.5

3.3

0.9

0.5

ISL6455A

FB_PWM Initial Voltage Accuracy (Note 7)

FB_PWM Line Regulation

= 0.45V, I

OUT

= 3mA, T = -40°C to 85°C

-0.9

-0.5

REF

= 3mA, V = PV

= 3.0-3.6V (ISL6455)

or 4.2-5.5V (6455A)

FB_PWM Load Regulation

Peak Output Current Limit

= 3mA to 500mA, V = PV = 3.0-3.6V (ISL6455)

-1.1

+1.1

or 4.2-5.5V (ISL6455A)

700mA

1300

mΩ

PMOS r

NMOS r

= 200mA

170

DS(ON)

OUT

DS(ON)

FN9196.0

December 21, 2005

ISL6455, ISL6455A

Electrical Specifications Recommended operating conditions unless otherwise noted. V = V _LDO = PV = 3.3V for ISL6455 and

5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. T = -40°C to 85° (Note 2), typical

values are at T = 25°C. (Continued)

PARAMETER

TEST CONDITIONS

= 200mA, V = 3.3V, V = 1.8V

MIN

TYP

MAX

UNITS

Efficiency

OUT

Soft-Start Time

OSCILLATOR

4096 Clock Cycles @ 750kHz

5.5

Oscillator Frequency

= -40°C to +85°C

620

500

750

880

kHz

Frequency Synchronization Range (f

SYNC High Level Input Voltage

SYNC Low Level Input Voltage

Sync Input Leakage Current

)

Clock signal on SYNC pin

1000

SYNC

As % of V

1.0

SYNC = GND or V

-1.0

µA

Min Duty Cycle of External Clock Signal (Note 6)

Max Duty Cycle of External Clock Signal (Note 6)

PG_PWM

Rising Threshold

1.2mA source/sink, FB_PWM vs 0.45V V

+5.5

-10.5

8.0

-8.0

0.01

+10.5

-5.5

0.1

REF

Falling Threshold

FB_PWM vs 0.45V V

REF

Leakage Current

PG_PWM = GND or V

µA

LDO1 SPECIFICATIONS

Output Voltage Range

VIN_VLDO > 3.0V

VIN_VLDO > 3.6V

1.2

-1.5

300

350

2.7

3.3

1.5

Output Voltage Range

FB_LDO1 Voltage Accuracy (Note 7)

Maximum Output Current (Note 6)

Output Current Limit (Note 6)

Dropout Voltage (Note 4)

FB_LDO1 Line Regulation

FB_LDO1 Load Regulation

Output Voltage Noise (Note 6)

= 10mA

= 3.6V

OUT

420

150

%/V

600

300

0.5

= 300mA

OUT

= 10mA, VIN_LDO = 3.0-5.5V

= 10mA to 300mA

-0.5

10Hz < f < 100kHz, I

= 10mA

OUT

= 2.2µF

= 10µF

µV

OUT

RMS

OUT

LDO2 SPECIFICATIONS

Output Voltage Range

VIN_VLDO > 3.0V

VIN_VLDO > 3.6V

1.2

-1.5

300

350

2.7

3.3

1.5

Output Voltage Range

FB_LDO2 Voltage Accuracy (Note 7)

Maximum Output Current (Note 6)

Output Current Limit (Note 6)

Dropout Voltage (Note 4)

= 10mA

= 3.6V

%/V

OUT

420

150

600

300

0.5

= 300mA

OUT

FB_LDO2 Line Regulation

FB_LDO2 Load Regulation

Output Voltage Noise (Note 6)

= 10mA, VIN_LDO = 3.0-5.5V

= 10mA to 300mA

-0.5

10Hz < f < 100kHz, I

= 10mA

OUT

= 2.2µF

= 10µF

µV

OUT

RMS

µV

OUT

FN9196.0

December 21, 2005

ISL6455, ISL6455A

Electrical Specifications Recommended operating conditions unless otherwise noted. V = V _LDO = PV = 3.3V for ISL6455 and

5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. T = -40°C to 85° (Note 2), typical

values are at T = 25°C. (Continued)

PARAMETER

ENABLE (EN and (EN_LDO)

EN High Level Input Voltage

EN Low Level Input Voltage

RESET BLOCK SPECIFICATIONS

RESET (reset released)

TEST CONDITIONS

MIN

TYP

MAX

UNITS

As % of VIN

ISL6455, ISOURCE = 500µA, VIN = 2.90V

0.8 x

RESET (reset asserted)

RESET Rising Threshold

RESET Falling Threshold

RESET (reset released)

ISL6455, ISINK = 1.2mA, VIN = 2.50V

0.3

2.84

2.81

ISL6455

2.71

2.69

0.8 x

2.77

2.75

ISL6455

ISL6455A, ISOURCE = 800µA, VIN = 4.70V

RESET (reset asserted)

ISL6455A, ISINK = 3.2mA, VIN = 4.10V

0.4

RESET Rising Threshold

ISL6455A

ISL6455

4.19

4.27

4.24

4.35

RESET Falling Threshold

4.16

4.32

RESET Threshold Hysteresis

RESET Active Timeout Period (Note 5)

POWER GOOD (PG_LDO)

Minimum Input Voltage for Valid PG_LDO

PGOOD Threshold (Rising)

PGOOD Threshold (Falling)

PGOOD Output Voltage Low

PGOOD Output Leakage Current

PWM OUTPUT OVERVOLTAGE

Overvoltage Threshold

ISL6455A

= 0.01µF

+11

-17

1.2

+15

-15

+17

-11

0.4

0.1

FB_LDO vs 1.184V Vref

= 1.2mA

PG_LDO = GND or VIN

0.01

µA

FB_PWM vs 0.45V Vref

NOTES:

3. Specifications at -40°C and +85°C are guaranteed by 25°C test with margin limits.

4. This is the V current consumed when the device is active but not switching. Does not include gate drive current.

5. The dropout voltage is defined as V - V

, when V

is 50mV below the value of V

for V = V

+ 0.5V.

OUT OUT

OUT

6. The RESET timeout period is linear with CT at the slope of 2.5ms/nF. Thus, at 10nF (0.01µF) the RESET time is 25ms; at 1000nF (0.1µF) the

RESET time would be 250ms.

7. Guaranteed by design, not production tested.

8. Add the external feedback resistor mismatch error to get initial V

accuracy.

OUT

FN9196.0

December 21, 2005

ISL6455, ISL6455A

PG_LDO Timing Diagram

UVLO

RISING

VFB_LDO

PG_LDO

THRESHOLD

VOLTAGE

MAX +18%

FALLING

MIN -17%

PG_LDO

OUTPUT

UNDEFINED

NOTE:

9. V

is the minimum input voltage for a valid PG_LDO.

FN9196.0

December 21, 2005

ISL6455, ISL6455A

PG_PWM - This pin is an active pull-up/pull-down able to

Pin Descriptions

source/sink 1mA (min.) at 0.4V from V /SGND. This output

PVCC - Positive supply for the power (internal FET) stage of

is HIGH when V

is within ±8% (typical).

OUT

the PWM section.

FB_LDO1 and FB_LDO2 - These pins are used to set the

LDO output with the proper selection of resistors. i.e. Ra and

Rb for LDO1 and Rc and Rd for LDO2. Resistors should be

chosen to provide a minimum current of 200µA load for each

LDO output.

SGND - Analog ground for the PWM. All internal control

circuits are referenced to this pin.

EN - The PWM controller is enabled when this pin is HIGH,

and disabled when the pin is pulled LOW. It is a CMOS logic-

level input (referenced to V ).

LX - The LX pin is the switching node of synchronous buck

converter, connected internally at the junction point of the

upper MOSFET source and lower MOSFET drain. Connect

this pin to the output inductor.

_LDO - This is the input voltage pin for LDO1 and LDO2.

EN_LDO - LDO1 and LDO2 are enabled when this pin is

HIGH, and disabled when the pin is pulled LOW. It is a

CMOS logic-level input (referenced to V ).

- This pin is the power supply for the PWM controller

stage and must be closely decoupled to ground.

CT - Timing capacitor pin to set the 25ms minimum pulse

width for the RESET signal.

SYNC - This is the external clock synchronization input. The

device can be synchronized to 500kHz to 1MHz switching

frequency. If unused then it should be tied to GND or VCC

RESET - This pin is the output of the reset supervisory

circuit, which monitors VIN_PWM. The IC asserts a RESET

signal whenever the supply voltage drops below a preset

threshold. It is kept asserted for a minimum of 25ms after

GND - Tie this pin to the ground plane with a low impedance,

shortest possible path.

(V ) has risen above the reset threshold. The output is

CC IN

FB_PWM- This is used to set the value of the output voltage

of the PWM with external resistors Re and Rf.

push-pull. The device will continue to operate until V drops

below the UVLO threshold.

When EN = LOW then RESET = HIGH and the moment EN

is made HIGH the RESET will pulse LOW for a period of

25ms minimum (VIN > Reset threshold). If VIN < reset

threshold then it will switch low and stay low for a period of

25ms after VIN_PWM crosses the reset threshold.

Functional Description

The ISL6455 is a 3-in-1 multi-output regulator designed for

FPGA and wireless chipset power applications. The device

integrates a single synchronous buck regulator with dual

LDOs. The PWM output can be set by choosing appropriate

values for Re and Rf. At a setting of 1.8V the synchronous

buck regulator provides for an efficiency greater than 92%.

The LDO1 can be set with resistor pair Rc and Rd. The

LDO2 can be set with the resistor pair Ra and Rb.

PG_LDO - This is a high impedance open drain output that

provides the status of both LDOs. When either of the outputs

are out of regulation, PG_LDO goes LOW.

CC1 - This is the compensation capacitor connection for

LDO1. Connect a 0.033µF capacitor from CC1 to

GND_LDO.

Undervoltage lock-out (UVLO) prevents the converter from

turning on when the input voltage is less than 2.6V typical.

Additional blocks include output overcurrent protection,

thermal sensor, PGOOD detectors, RESET function and

shutdown logic.

CC2 - This is the compensation capacitor connection for

LDO2. Connect a 0.033µF capacitor from CC2 to

GND_LDO.

Synchronous Buck Regulator

- This pin is the output of LDO2. Bypass with a

minimum 2.2µF, low ESR capacitor to GND_LDO for stable

operation.

OUT2

The synchronous buck regulator with integrated N- and

P-channel power MOSFETs and external voltage setting

resistors provides for adjustable voltages from the PWM.

Synchronous rectification with internal MOSFETs is used to

achieve higher efficiency and reduced number of external

components. Operating frequency is typically 750kHz

allowing the use of smaller inductor and capacitor values.

The device can be synchronized to an external clock signal

in the range of 500kHz to 1MHz. The PG_PWM output

indicates loss of regulation on PWM output.

GND_LDO - Ground pin for LDO1 and LDO2.

- This pin is the output of LDO1. Bypass with a

minimum 2.2µF, low ESR capacitor to GND_LDO for stable

operation.

OUT1

PGND - Power ground for the PWM controller stage.

- This I/O pin senses the output voltage of the PWM

converter for the purpose of detecting the over and

undervoltage conditions.

OUT

The PWM architecture uses a peak current mode control

scheme with internal slope compensation. At the beginning

of each clock cycle, the high side P-channel MOSFET is

turned on. The current in the inductor ramps up and is

FN9196.0

December 21, 2005

ISL6455, ISL6455A

sensed via an internal circuit. The error amplifier sets the

and the PWM output is shut down and the soft-start counter

is reset. After 16 clocks the PWM output is enabled and the

SS cycle is started.

threshold for the PWM comparator. The high side switch is

turned off when the sensed inductor current reaches this

threshold. After a minimum dead time preventing shoot

through current, the low side N-channel MOSFET will be

turned on and the current ramps down again. As the clock

cycle is completed, the low side switch will be turned off and

the next clock cycle starts.

If V

OUT

exceeds the overvoltage limit for 32 consecutive

clock cycles, the PWM output is shut off and the SS counters

reset. The chip waits for the output voltage to go below

undervoltage (8% below nominal) the goes through two

dummy soft-start cycles (PWM disabled for 2 SS cycles =

11ms) and then starts a normal soft-start cycle.

The control loop is internally compensated reducing the

amount of external components.

PG_LDO

The switch current is internally sensed and the maximum

peak current limit is 1300mA.

PG_LDO is an open drain pulldown NMOS output that will

sink 1mA at 0.4V maximum. It goes to the active low state if

either LDO output is out of regulation by a value greater than

15%. When the LDO is disabled, the output is active low.

Synchronization

The typical operating frequency for the converter is 750kHz

if no clock signal is applied to SYNC pin. It is possible to

synchronize the converter to an external clock within a

frequency range from 500kHz to 1MHz. The device

automatically detects the rising edge of the first clock and

will synchronize immediately to the external clock. If the

clock signal is stopped, the converter automatically switches

back to the internal clock and continues operation without

interruption. The switch over will be initiated if no rising edge

on the SYNC pin is detected for a duration of two internal

1.3µs clock cycles.

LDO Regulators

Each LDO consists of a 1.184V reference, error amplifier,

MOSFET driver, P-Channel pass transistor, dual-mode

comparator. The voltage is set by means of two resistors the

Ra and Rb for LDO2 and Rc and Rd for LDO1. The 1.184V

band gap reference is connected to the error amplifier’s

inverting input. The error amplifier compares this reference

to the selected feedback voltage and amplifies the

difference. The MOSFET driver reads the error signal and

applies the appropriate drive to the P-Channel pass

transistor. If the feedback voltage is lower than the reference

voltage, the pass transistor gate is pulled lower, allowing

more current to pass and increasing the output voltage. If the

feedback voltage is higher then the reference voltage, the

pass transistor gate is driven higher, allowing less current to

pass to the output.

Soft-Start

As the EN (Enable) pin goes high, the soft-start function will

generate an internal voltage ramp. This causes the start-up

current to slowly rise preventing output voltage overshoot

and high inrush currents. The soft-start duration is typically

5.5ms with 750kHz switching frequency. When the soft-start

is completed, the error amplifier will be connected directly to

the internal voltage reference. The SYNC input is ignored

during soft-start.

Internal P-Channel Pass Transistors

Both the LDO Regulators in ISL6455 feature a typical 0.5Ω

P-channel MOSFET pass transistor. This provides

DS(on)

several advantages over similar designs using PNP bipolar

pass transistors. The P-Channel MOSFET requires no base

drive, which reduces quiescent current considerably. PNP

based regulators waste considerable current in dropout

when the pass transistor saturates. They also use high base

drive currents under large loads. The ISL6455 does not have

these drawbacks.

Enable PWM

Logic low on EN pin forces the PWM section into shutdown.

In shutdown all the major blocks of the PWM including power

switches, drivers, voltage reference, and oscillator are

turned off.

Power Good (PG_PWM)

When chip is enabled, this output is asserted HIGH, when

Integrated RESET for MAC/Baseband Processors

is within 8% of Vopwm value and active low outside

OUT

The ISL6455 includes a microprocessor supervisory block.

This block eliminates an extra RESET IC and external

components needed in wireless chipset applications. This

block performs a single function; it asserts a RESET signal

whenever the VIN_PWM supply voltage decreases below a

preset threshold, and keeps it asserted for a programmable

time period set by the external capacitor CT.

this range. When the PWM is disabled, the output is active

low.

Leave the PG_PWM pin unconnected when not used.

PWM Overvoltage and Overcurrent Protection

The PWM output current is sampled at the end of each PWM

cycle. Should it exceed the overcurrent limit, a 4 bit up/down

counter counts up two LSB. Should it not be in overcurrent

the counter counts down one LSB (but the counter will not

"rollover" or count below 0000). If >33% of the PWM cycles

go into overcurrent, the counter rapidly reaches count 1111

UVLO Reset threshold is always lower than the RESET

threshold. This insures that as V falls, the reset goes low

before the LDOs and PWM are shut off.

FN9196.0

December 21, 2005

ISL6455, ISL6455A

Where T

= 150°C, T = ambient temperature, and θ is

A JA

Integrator Circuitry

jmax

the thermal resistance from the junction to the surrounding

environment.

Both ISL6455 LDO Regulators use external 33nF

compensation capacitors for minimizing load and line

regulation errors and for lowering output noise. When the

output voltage shifts due to varying load current or input

voltage, the integrator capacitor voltage is raised or lowered

to compensate for the systematic offset at the error amplifier.

Compensation is limited to ±5% to minimize transient

overshoot when the device goes out of dropout, current limit,

or thermal shutdown.

The ISL6455, ISL6455A package feature an exposed

thermal pad on its underside. This pad lowers the thermal

resistance of the package by providing a direct heat

conduction path from the die to the PC board. Additionally,

the ISL6455 and ISL6455A ground (GND_LDO and PGND)

performs the dual function of providing an electrical

connection to system ground and channeling heat away.

Connect the exposed bottom pad direct to the GND_LDO

ground plane.

Shutdown

Driving the EN_LDO pin low will put LDO1 and LDO2 into

the shutdown mode. Driving the EN pin low will put the PWM

into shutdown mode. Pulling the EN and EN_LDO both pins

low simultaneously, puts the ISL6455, ISL6455A in a

shutdown mode, and supply current drops to 15µA typical.

Application Information

LDO Regulator Capacitor Selection and Regulator

Stability

Capacitors are required at the ISL6455, ISL6455A LDO

regulators’ input and output for stable operation over the

entire load range and the full temperature range. Use >1µF

Protection Features for the LDOs

Current Limit

The ISL6455 and ISL6455A monitor and control the pass

transistor’s gate voltage to limit the output current. The

current limit for both LDO1 and LDO2 is 330mA. The output

can be shorted to ground without damaging the part due to

the current limit and thermal protection features.

capacitor at the input of LDO regulators, V _LDO pins. The

input capacitor lowers the source impedance of the input

supply. Larger capacitor values and lower ESR provide

better PSRR and line transient response. The input

capacitor must be located at a distance of not more than 0.5

inches from the V pins of the IC and returned to a clean

analog ground. Any good quality ceramic capacitor can be

used as an input capacitor.

Thermal Overload Protection

Thermal overload protection limits total power dissipation in

the ISL6455, ISL6455A. When the junction temperature (T )

The output capacitor must meet the requirements of

minimum amount of capacitance and ESR for both LDOs.

The ISL6455 is specifically designed to work with small

ceramic output capacitors. The output capacitor’s ESR

affects stability and output noise. Use an output capacitor

with an ESR of 50mΩ or less to insure stability and optimum

transient response. For stable operation, a ceramic

capacitor, with a minimum value of 3.3µF, is recommended

exceeds +150°C, the thermal sensor sends a signal to the

shutdown logic, turning off the pass transistor and allowing

the IC to cool. The pass transistor turns on again after the

IC’s junction temperature typically cools by 20°C, resulting in

an intermittent output condition during continuous thermal

overload. Thermal overload protection protects the ISL6455,

ISL6455A against fault conditions. For continuous operation,

the absolute maximum junction temperature rating of

+150°C in not to be exceeded.

for V

for 300mA output current, and 3.3µF is

recommended for V at 300mA load current. There is no

OUT1

OUT2

upper limit to the output capacitor value. A larger capacitor

can reduce noise and improve load transient response,

stability and PSRR. A higher value output capacitor (10µF) is

recommended for LDO2 when used to power VCO circuitry

in wireless chipsets. The output capacitor should be located

Operating Region and Power Dissipation

The maximum power dissipation of ISL6455 depends on the

thermal resistance of the IC package and circuit board, the

temperature difference between the die junction and ambient

air, and the rate of air flow. The power dissipated in the

device is:

very close to V

pins to minimize impact of PC board

OUT

inductances and the other end of the capacitor should be

returned to a clean analog ground.

PT = P1 + P2 + P3, where

P1 = I

P2 = I

P3 = I

x V x n, n is the efficiency of the PWM

OUT1

PWM Regulator Component Selection

INDUCTOR SELECTION

A 8.2µH typical output inductor is used with the ISL6455 and

a 12µH typical with the ISL6455A PWM section. Values less

than this may cause stability problems because of the

internal compensation of the regulator. The important

parameters of the inductor that need to be considered are

the current rating of the inductor and the DC resistance of

OUT1

(V – V

)

OUT2 IN OUT2

(V - V

)

OUT3 IN OUT3

The maximum power dissipation is:

= (T – T )/θ

max

jmax

FN9196.0

December 21, 2005

ISL6455, ISL6455A

the inductor. The DC resistance of the inductor will influence

The input capacitor should have a minimum value of 10µF

and can be increased without any limit for better input

voltage filtering. The input capacitor should be rated for the

maximum input ripple current calculated as:

directly the efficiency of the converter. Therefore, an inductor

with lowest DC resistance should be selected for highest

efficiency.

In order to avoid saturation of the inductor, the inductor

should be rated at least for the maximum output current plus

the inductor ripple current.









-------

= I

× 1 – -------



RMS

O(max)



TABLE 1. RECOMMENDED INDUCTORS

OUTPUT INDUCTOR

The worst case RMS ripple current occurs at D = 0.5.

Ceramic capacitors show good performance because of

their low ESR value, and because they are less sensitive to

voltage transients, compared to tantalum capacitors.

CURRENT

VALUE

VENDOR PART #

COMMENTS

600mA

8.2µH

Coilcraft

MSS6122-822MX

ISL6455

Place the input capacitor as close as possible to the input pin

of the IC for best performance.

600mA

12µH

Coilcraft

MSS6122-123MX

ISL6455A

Output Voltage Setting

The equations for the Output voltages are given below:

OUTPUT CAPACITOR SELECTION

For the best performance, a low ESR output capacitor is

needed. If an output capacitor is selected with an ESR value

≤120mΩ, its RMS ripple current rating will always meet the

application requirements. The RMS ripple current is

calculated as:

0.45

-----------

VOUT =

VOUT1 =

VOUT2 =

(Re + Rf)

1.184

--------------

(Ra + Rb)

(Rc + Rd)

1 – -------

1.184

2 ×

--------------

----------------- ----------------

= V

RMS(C)

L × f

The output resistors should be selected so that the minimum

The overall output ripple voltage is the sum of the voltage

output load is about 200µA.

spike caused by the output capacitor ESR plus the voltage

Layout Considerations

ripple caused by charge and discharging the output

As for all switching power supplies, the layout is an important

step in the design of ISL6455, ISL6455A based power

supply due to the high switching frequency and low noise

LDO implementations.

capacitor:













1 – -------





-----------------

∆V = V

------------------------- + ESR

 

L × f

8 × C × f

Allocate two board levels as ground planes, with many vias

between them to create a low impedance, high-frequency

plane. Tie all the device ground pins through multiple vias

each to this ground plane, as close to the device as possible.

Also tie the exposed pad on the bottom of the device to this

ground plane.

Where the highest output voltage ripple occurs at the highest

input voltage.

TABLE 2. RECOMMENDED CAPACITORS

CAPACITOR

VALUE

ESR/mΩ

VENDOR PART #

COMMENTS

Use wide and short traces for the high current paths. The

input capacitor should be placed as close as possible to the

IC pins as well as the inductor and output capacitor. Use a

common ground node to minimize the effects of ground

noise.

10µF

<50

TDK

Ceramic

C2012X5R0J106M

INPUT CAPACITOR SELECTION

Because of the nature of the buck converter having a

pulsating input current, a low ESR input capacitor is required

for best input voltage filtering and minimizing the

interference with other circuits caused by high input voltage

spikes.

FN9196.0

December 21, 2005

ISL6455, ISL6455A

Quad Flat No-Lead Plas tic Package (QFN)

Micro Lead Frame Plas tic Package (MLFP)

L24.4x4B

24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VGGD-2 ISSUE C)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

0.80

0.90

0.20 REF

0.18

2.19

0.23

0.30

2.49

5, 8

4.00 BSC

3.75 BSC

2.34

7, 8

4.00 BSC

3.75 BSC

2.34

7, 8

0.50 BSC

0.25

0.30

0.40

0.50

0.15

0.60

Rev. 0 10/03

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9196.0

December 21, 2005

P r i n t e r F r i e n d l y V e r s i o n

IS L6 4 55A

0 .6 A P W M Re gu l at o r a n d D u al 0 .3 A L DO s an d Re se t

D a t a s h e e t s ,

R e l a t e d D o c s

& S i m u l a t i o n s

D e s c r i p t i o n

K ey

F e a t u r e s

P a r a m e t r i c

D a t a

A p p l i c a t i o n

D i a g r a m s

R e l a t e d

D e v i c e s

Or d er in g I nf o r m at io n

De s ig n - In

P r i c e

Pa r t N o.

S t a t u s Te m p.

P a c k a g e

M SL US $

A ct i v e

E v a l B o a r d

N/ A

I SL 6 4 55 A EVA L 1 Z

IS L 645 5A I RZ

A ct i v e

I n d

2 4 L d Q F N

1 . 8 1

24 Ld QF N T+ R

IS L6455AI RZ -T5K

I SL 6 4 5 5 AI R Z-TK

T h e p r ic e li st e d i s t h e m an uf a ct ur e r 's sugg ested r et ail pr i ce f or q uant it i es bet w ee n 1 00 a n d

9 9 9 un its . Ho we v e r, pri c es i n to da y' s ma rk et a re fl u i d a n d m ay ch an ge w i th o ut n o t ice .

MS L = M o i s t u r e S e n s i t i v i t y L e v e l - p e r I P C / J E D E C J - S T D - 0 2 0

SMD = S t a n d a r d M i c r o c i r c u i t D r a w i n g

D esc rip ti on

T h e I S L 6 4 5 5 i s a h i g h l y i n t e g r a t e d t r i p l e o u t p u t r e g u l a t o r w h i c h p r o v i d e s a s i n g l e c h i p s o l u t i o n f o r

F P G A s a n d w i r e l e s s c h i p s e t p o w e r m a n a g e m e n t . T h e d e v i c e i n t e g r a t e s a h i g h e f f i c i e n c y

s y n c h r o n o u s b u c k r e g u l a t o r ( a d j u s t a b l e ) w i t h t w o u l t r a l o w n o i s e L D O r e g u l a t o r s ( a d j u s t a b l e ) .

E i t h e r t h e I S L 6 4 5 5 o r I S L 6 4 5 5 A c a n b e s e l e c t e d b a s e d o n w h e t h e r 3 . 3 V ± 1 0 % o r 5 V ± 1 0 % i s

r e q u i r e d a s a n i n p u t v o l t a g e .

T h e s y n c h r o n o u s c u r r e n t m o d e c o n t r o l P W M r e g u l a t o r w i t h i n t e g r a t e d N - a n d P - c h a n n e l p o w e r

M O S F E T p r o v i d e s a d j u s t a b l e v o l t a g e s b a s e d o n e x t e r n a l r e s i s t o r s e t t i n g . S y n c h r o n o u s r e c t i f i c a t i o n

w i t h i n t e r n a l M O S F E T s i s u s e d t o a c h i e v e h i g h e r e f f i c i e n c y a n d r e d u c e d n u m b e r o f e x t e r n a l

c o m p o n e n t s . O p e r a t i n g f r e q u e n c y i s t y p i c a l l y 7 5 0 k H z a l l o w i n g t h e u s e o f s m a l l e r i n d u c t o r a n d

c a p a c i t o r v a l u e s . T h e d e v i c e c a n b e s y n c h r o n i z e d t o a n e x t e r n a l c l o c k s i g n a l i n t h e r a n g e o f 5 0 0 k H z

t o 1 M H z . T h e P G _ P W M o u t p u t i n d i c a t e s l o s s o f r e g u l a t i o n o n P W M o u t p u t .

T h e I S L 6 4 5 5 a l s o h a s t w o L D O a d j u s t a b l e r e g u l a t o r s u s i n g i n t e r n a l P M O S t r a n s i s t o r s a s p a s s

d e v i c e s . L D O 2 f e a t u r e s u l t r a l o w n o i s e t y p i c a l l y b e l o w 3 0 µ V R M S t o a i d V C O s t a b i l i t y . T h e E N _ L D O

p i n c o n t r o l s L D O 1 a n d L D O 2 o u t p u t s . T h e I S L 6 4 5 5 a l s o i n t e g r a t e s a RE S E T f u n c t i o n , w h i c h

e l i m i n a t e s t h e n e e d f o r a d d i t i o n a l R E S E T I C r e q u i r e d i n W L A N a n d o t h e r a p p l i c a t i o n s . T h e I C

a s s e r t s a RE S E T s i g n a l w h e n e v e r t h e V s u p p l y v o l t a g e d r o p s b e l o w a p r e s e t t h r e s h o l d , k e e p i n g

I N

i t a s s e r t e d f o r a t l e a s t 2 5 m s a f t e r V h a s r i s e n a b o v e t h e r e s e t t h r e s h o l d . T h e P G _ L D O o u t p u t

I N

i n d i c a t e s l o s s o f r e g u l a t i o n o n e i t h e r o f t h e t w o L D O o u t p u t s . O t h e r f e a t u r e s i n c l u d e o v e r c u r r e n t

p r o t e c t i o n a n d t h e r m a l s h u t d o w n f o r a l l t h e t h r e e o u t p u t s .

H i g h i n t e g r a t i o n a n d t h e t h i n Q u a d F l a t N o - l e a d ( Q F N ) p a c k a g e m a k e s I S L 6 4 5 5 a n i d e a l c h o i c e f o r

p o w e r i n g F P G A s a n d s m a l l f o r m f a c t o r w i r e l e s s c a r d s s u c h a s P C M C I A , m i n i - P C I a n d C a r d b u s - 3 2 .

K ey Fe a t u r e s

F u l l y i n t e g r a t e d s y n c h r o n o u s b u c k r e g u l a t o r + d u a l L D O

P W M o u t p u t v o l t a g e a d j u s t a b l e .

0 .8 V to 2.5 V wit h IS L 6 4 55 (V = 3. 3V)

I N

0 .8 V to 3. 3V w it h IS L6 455 A ( V = 5. 0V)

I N

H i g h o u t p u t c u r r e n t 6 0 0 m A

D u a l L D O a d j u s t a b l e o p t i o n s

L D O1 , 1 . 2V t o V -0 .3 V (3. 3 Vma x) 3 00 mA

I N

L D O2 , 1 . 2V t o V -0 .3 V (3. 3 Vma x) 3 00 mA

I N

U l t r a - c o m p a c t D C / D C c o n v e r t e r d e s i g n

S t a b l e w i t h s m a l l c e r a m i c o u t p u t c a p a c i t o r s a n d n o l o a d

H i g h c o n v e r s i o n e f f i c i e n c y

L o w s h u t d o w n s u p p l y c u r r e n t

L o w d r o p o u t v o l t a g e f o r L D O s

L D O 1 1 5 0 m V ( t y p i c a l ) a t 3 0 0 m A

L D O 2 1 5 0 m V ( t y p i c a l ) a t 3 0 0 m A

L o w o u t p u t v o l t a g e n o i s e

< 3 0 µVR MS (ty pi ca l ) f o r L D O 2 (V CO su ppl y)

P G_ LDO an d P G_ P W M ( P WM a nd L DO) o ut pu ts

E x t e n s i v e c i r c u i t p r o t e c t i o n a n d m o n i t o r i n g f e a t u r e s

PWM o ve rv o lta g e p r ot ec t io n

O v e r c u r r e n t p r o t e c t i o n

S h u t d o w n

T h e r m a l s h u t d o w n

I n t e g r a t e d RE S E T o u t p u t f o r m i c r o p r o c e s s o r r e s e t

P r o v e n r e f e r e n c e d e s i g n f o r t o t a l W L A N s y s t e m s o l u t i o n

Q F N p a c k a g e

C o m p l i a n t t o J E D E C P U B 9 5 M O - 2 2 0 Q F N - Q u a d F l a t N o L e a d s - P r o d u c t O u t l i n e

N e a r C h i p - S c a l e p a c k a g e f o o t p r i n t I m p r o v e s P C B e f f i c i e n c y a n d i s t h i n n e r i n P r o f i l e

P b - f r e e p l u s a n n e a l a v a i l a b l e ( R o H S c o m p l i a n t )

Re la t ed Do cu m e n ta t io n

A p p l i c a t i o n N o t e ( s ) :

I n t e r s i l I n t e g r a t e d F E T D C / D C C o n v e r t e r s

I n t e r s i l I n t e g r a t e d F E T D C / D C C o n v e r t e r s ( S i m p l i f i e d C h i n e s e )

D a t a s h e e t ( s ) :

T r i p l e O u t p u t R e g u l a t o r w i t h S i n g l e S y n c h r o n o u s B u c k a n d D u a l L D O

E v a l u a t i o n B o a r d ( s ) :

I S L 6 4 5 5 E V A L 1 Z : 6 0 0 m A S y n c h r o n o u s B u c k R e g u l a t o r w i t h I n t e g r a t e d M O S F E T s

i - S i m :

G e t t i n g S t a r t e d w i t h i S i m a n d i S i m : P E

I S L 6 4 5 5 A i S i m

J a v a ™ P l u g - i n S e t u p I n s t r u c t i o n s f o r W i n d o w s ® 2 0 0 0 S y s t e m s

P a r a m e t r i c D a t a

( m in) ( V )

(ma x) (V)

4 . 5

5 . 5

I N

OU T

( m in) ( V )

(ma x) (V)

OU T

3 . 3

(ma x) (A)

OU T

I q (µA )

2 5 0 0

. 7 5

9 3

S witc hin g F re que nc y ( M Hz )

P ea k E f f i cien cy ( %)

P O R

A pp licat ion B loc k D iag ram s

D V D R e c o r d e r

D i g i t a l P r o j e c t o r

F i n g e r p r i n t B i o m e t r i c s

I PT V Se t- T o p Bo x

To x i c G a s Mo n it o r

Ap pli cat io n s

W L A N c a r d s

P C M C I A , C a r d b u s 3 2 , M i n i P C I c a r d s

C o m p a c t f l a s h c a r d s

H a n d - h e l d i n s t r u m e n t s

R e l a te d D e v i ce s

P a r a m e t r i c T a b l e

E L 7 5 3 0

E L 7 5 3 1

E L 7 5 3 2

E L 7 5 3 4

E L 7 5 3 6

E L 7 5 5 4

E L 7 5 6 6

M o n o l i t h i c 6 0 0 m A S t e p - D o w n R e g u l a t o r w i t h L o w Q u i e s c e n t C u r r e n t

M o n o l i t h i c 1 A S t e p - D o w n R e g u l a t o r w i t h L o w Q u i e s c e n t C u r r e n t

M o n o l i t h i c 2 A S t e p - D o w n R e g u l a t o r

M o n o l i t h i c 6 0 0 m A S t e p - D o w n R e g u l a t o r

M o n o l i t h i c 1 A S t e p - D o w n R e g u l a t o r

M o n o l i t h i c 4 A D C / D C S t e p - D o w n R e g u l a t o r

M o n o l i t h i c 6 A D C / D C S t e p - D o w n R e g u l a t o r

1 . 2 A L o w Q u i e s c e n t C u r r e n t 1 . 6 M H z H i g h E f f i c i e n c y S y n c h r o n o u s B u c k

R e g u l a t o r

I S L 6 2 7 3

I S L 6 4 1 0

I S L 6 4 1 0 A

I S L 6 4 1 2

I S L 6 4 1 3

I S L 6 4 1 6

I S L 6 4 5 5

S i n g l e S y n c h r o n o u s B u c k R e g u l a t o r w i t h I n t e g r a t e d F E T f o r W L A N C h i p s e t s

T r i p l e O u t p u t , L o w - N o i s e L D O R e g u l a t o r w i t h I n t e g r a t e d R e s e t C i r c u i t

T r i p l e O u t p u t R e g u l a t o r w i t h S i n g l e S y n c h r o n o u s B u c k a n d D u a l L D O

T r i p l e O u t p u t , L o w - N o i s e L D O R e g u l a t o r w i t h I n t e g r a t e d R e s e t C i r c u i t

0 . 6 A P W M R e g u l a t o r a n d D u a l 0 . 3 A L D O s a n d R e s e t

1 . 5 A L o w Q u i e s c e n t C u r r e n t 1 . 6 M H z H i g h E f f i c i e n c y S y n c h r o n o u s B u c k

R e g u l a t o r

I S L 8 0 0 9

I S L 8 0 1 0

I S L 8 0 1 1

I S L 8 5 0 2

I S L 8 5 4 0

I S L 8 5 6 0

M o n o l i t h i c 6 0 0 m A S t e p - D o w n R e g u l a t o r w i t h L o w Q u i e s c e n t C u r r e n t

1 . 2 A I n t e g r a t e d F E T s , H i g h E f f i c i e n c y S y n c h r o n o u s B u c k R e g u l a t o r

2 . 5 A S y n c h r o n o u s B u c k R e g u l a t o r w i t h I n t e g r a t e d M O S F E T s

D C / D C P o w e r S w i t c h i n g R e g u l a t o r

6 0 0 m A L o w Q u i e s c e n t C u r r e n t 1 . 6 M H z H i g h E f f i c i e n c y S y n c h r o n o u s B u c k

R e g u l a t o r

I S L 9 1 0 5

I S L 9 7 5 3 6

M o n o l i t h i c 1 A S t e p - D o w n R e g u l a t o r w i t h L o w Q u i e s c e n t C u r r e n t

ISL6455IRZ-TK [ROCHESTER]

相关型号：

ISL6504

ISL6504A

ISL6504ACB

ISL6504ACB-T

ISL6504ACBN

ISL6504ACBN-T

ISL6504ACBNZ

ISL6504ACBNZ-T

ISL6504ACBZ

ISL6504ACBZ

ISL6504ACBZ-T

ISL6504ACR