ISL6405EEBZ [RENESAS]
SWITCHING CONTROLLER, 240kHz SWITCHING FREQ-MAX, PDSO28, LEAD FREE, PLASTIC, SOIC-28;型号: | ISL6405EEBZ |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | SWITCHING CONTROLLER, 240kHz SWITCHING FREQ-MAX, PDSO28, LEAD FREE, PLASTIC, SOIC-28 开关 光电二极管 |
文件: | 总14页 (文件大小:674K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATASHEET
ISL6405
FN9026
Rev 2.00
Jul 2004
Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for
Advanced Satellite Set-Top Box Designs
The ISL6405 is a highly integrated voltage regulator and
interface IC, specifically designed for supplying power and
control signals from advanced satellite set-top box (STB)
Features
• Single Chip Power solution
- True Dual Operation for 2-Tuner/2-Dish Applications
- Both Outputs May be Enabled Simultaneously at
Maximum Power
- Integrated DC-DC Converter and I C Interface
modules to the low noise blocks (LNBs) of two antenna
ports. The device is composed of two independent
current-mode boost PWMs and two low-noise linear
regulators along with the circuitry required for 22kHz tone
2
2
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with > 92% Efficiency
- Selectable 13V or 18V Outputs
generation, modulation and I C device interface. The device
makes the total LNB supply design simple, efficient and
compact with low external component count.
- Digital Cable Length Compensation (1V)
Two independent current-mode boost converters provide the
linear regulators with input voltages that are set to the final
output voltages, plus typically 1.2V to insure minimum power
dissipation across each linear regulator. This maintains
constant voltage drops across each linear pass element
while permitting adequate voltage range for tone injection.
2
• I C Compatible Interface for Remote Device Control
- Registered Slave Address 0001 00XX
- Full 3.3V/5V Operation up to 400kHz
• External Pins to Select 13V/18V Options
- Available with QFN Package Only
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqCTM (EUTELSAT) Encoding
The final regulated output voltages are available at two
output terminals to support simultaneous operation of two
antenna ports for dual tuners. The outputs for each PWM are
set to 13V or 18V by independent voltage select commands
• Internal Over-Temperature Protection and Diagnostics
2
• Internal Overload and Overtemp Flags (Visible on I C)
2
(VSEL1, VSEL2) through the I C bus. Additionally, to
• LNB Short-Circuit Protection and Diagnostics
compensate for the voltage drop in the coaxial cable, the
selected voltage may be increased by 1V with the line length
compensation (LLC) feature. All the functions on this IC are
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
2
controlled via the I C bus by writing 8 bits on System
Register (SR, 8 bits). The same register can be read back,
and two bits will report the diagnostic status. Separate enable
commands sent on the I C bus provide independent standby
mode control for each PWM and linear combination, disabling
the output into shutdown mode.
- Near Chip-Scale Package Footprint
• Pb-free Packaging Available
- Designated with “Z” Suffix (Refer to Note Below)
2
Applications
Each output channel is capable of providing 750mA of
continuous current. The overcurrent limit can be digitally
programmed. The SEL18V pin with QFN package allows the
13V to 18V transition with an external pin, over-riding the I C
input.
• LNB Power Supply and Control for Satellite Set-Top Box
References
• Tech Brief 389 (TB389) - “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”; Available
on the Intersil website, www.intersil.com
2
Ordering Information
o
PART #
TEMP. RANGE ( C) PACKAGE
PKG. DWG. #
28 Ld EPSOIC M28.3B
28 Ld EPSOIC M28.3B
ISL6405EEB
-20 to 85
-20 to 85
ISL6405EEBZ
(Note 1)
(Pb-free)
ISL6405ER
-20 to 85
-20 to 85
32 Ld 5x5 QFN L32.5x5
ISL6405ERZ
(Note 1)
32 Ld 5x5 QFN L32.5x5
(Pb-free)
NOTES:
1. Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination
finish, which is compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J Std-020B.
2. Tape and Reel available. Add “-T” suffix for Tape and Reel Packing Option.
FN9026 Rev 2.00
Jul 2004
Page 1 of 14
ISL6405
ISL6405 (EPSOIC)
TOP VIEW
VSW2
COMP2
FB2
1
2
3
4
5
6
7
8
9
28 VCC
27 CPVOUT
26 CPSWIN
25 CPSWOUT
24 TCAP2
23 DSQIN2
22 VO2
GATE2
PGND 2
CS2
ISL6405EEB
SGND
BYPASS
PGND1
21 AGND
20
VO1
GATE1 10
CS1 11
19 DSQIN1
18 TCAP1
17 SCL
FB1 12
COMP1 13
VSW1 14
16 ADDR
15 SDA
ISL6405 (QFN)
TOP VIEW
32 31 30 29 28 27 26 25
PGND2
CS2
CPSWOUT
TCAP2
DSQIN2
VO2
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
SGND
SEL18V1
SEL18V2
BYP
ISL6405ER
AGND
VO1
PGND1
GATE1
DSQIN1
TCAP1
9
10 11 12 13 14 15 16
FN9026 Rev 2.00
Jul 2004
Page 2 of 14
Block Diagram
15
16
17
OLF1
DCL
OLF2
DCL
OVERCURRENT
PROTECTION
LOGIC SCHEME 2
OVERCURRENT
PROTECTION
LOGIC SCHEME 1
COUNTER
COUNTER
PWM
LOGIC
PWM
LOGIC
OC1
OC2
GATE2
PGND2
GATE1
10
Q
S
Q
S
4
5
CLK2
CLK1
SDA
ADDR
SCL
ISEL1
EN1
ISEL2
PGND1
9
OLF
-
ILIM2
EN2
ENT2
DCL
CS
AMP
2
I C
CS2
ENT1
OTF
INTERFACE
6
-
ILIM1
CS
AMP
SLOPE
COMPENSATION
LLC1 VSEL1
CLK1
VSEL2 LLC2
CLK2
CS1
11
OSC.
220kHz
SLOPE
BAND GAP
REF VOLTAGE
COMP2
FB2
COMPENSATION
2
3
BGV
COMP1
13
BGV
-
10 &
-
WAVE SHAPING
REF
VOLTAGE
ADJ2
REF
VOLTAGE
ADJ1
FB1
12
VREF2
22kHz
TONE
VREF1
TONE
INJ
CKT 2
TONE
INJ
CKT 1
VSW2
VO2
1
VSW1
14
22
VO1
20
+
-
+
-
ENT2
ON CHIP
VCC
LINEAR
28
7
CPVOUT
CPSWIN
27
26
UVLO
POR
SOFT-START
ENT1
SGND
INT 5V
CHARGE PUMP
THERMAL
SHUTDOWN
SOFT-START
EN1/EN2
OTF
CPSWOUT
8
21
18
19
23
24
25
Typical Application Schematic
VIN = 8V TO 14V
+
+
C3
C14
L1
L2
D1
C4
+
C1
C2
D2
C20
C6
+
C10
C11
24
8
28
7
VCC
TCAP2
BYPASS
GATE2
CS2
Q1
R1
SGND
GATE1
CS1
10
11
4
Q2
6
5
2
9
PGND1
COMP1
PGND2
COMP2
R3
13
C12
C13
R3
R2
3
1
R4
12
14
FB1
FB2
VSW1
VSW2
22
17
15
26
25
27
20
19
23
16
18
21
VO1
VO2
SCL
C7
C5
DSQIN1
DSQIN2
ADDR
TCAP1
AGND
SDA
VO2
13V/18V
SCL
CPSWIN
CPSWOUT
CPVOUT
C17
SDA
VO1
13V/18V
C8
C15
C16
ISL6405EEB
C9
ISL6405
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Thermal Resistance (Typical, Notes 3, 4)
( C/W)
( C/W)
CC
Logic Input Voltage Range (SDA, SCL, ENT) . . . . . . . . -0.5V to 7V
JA
JC
EPSOIC Package (Notes 3, 4). . . . . . .
QFN Package (Notes 3, 4). . . . . . . . . .
29
34
4
6
o
Maximum Junction Temperature (Note 5) . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -40 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
o
(SOIC - Lead Tips Only)
Operating Temperature Range . . . . . . . . . . . . . . . . . -20 C to 85 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
3. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
4. For , the "case temp" location is the center of the exposed metal pad on the package underside.
JC
o
5. The device junction temperature should be kept below 150 C. Thermal shut-down circuitry turns off the device if junction temperature exceeds
o
+150 C typically.
o
o
o
Electrical Specifications
V
= 12V, T = -20 C to +85 C, unless otherwise noted. Typical values are at T = 25 C. EN1 = EN2 = H,
CC A A
LLC1 = LLC2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, Iout = 12mA, unless otherwise noted.
See software description section for I C access to the system.
2
PARAMETER
Operating Supply Voltage Range
Standby Supply Current
Supply Current
SYMBOL
TEST CONDITIONS
MIN
TYP
12
MAX
14
UNITS
V
8
-
EN1 = EN2 = L
1.5
4.0
3.0
8.0
mA
I
EN1 = EN2 = LLC1 = LLC2 = VSEL1 =
VSEL2 = ENT1 = ENT2 = H, No Load
-
mA
IN
UNDER VOLTAGE LOCKOUT
Start Threshold
7.5
7.0
350
-
-
7.95
7.55
500
V
V
Stop Threshold
Start to Stop Hysteresis
SOFT START
400
mV
COMP Rise Time (Note 6)
Output Voltage (Note 7)
(Note 7)
-
512
13.0
14.0
18.0
19.0
13.0
14.0
18.0
19.0
4.0
-
Cycles
V
V
V
V
V
V
V
V
V
VSEL1 = L, LLC1 = L
VSEL1 = L, LLC1 = H
VSEL1 = H, LLC1 = L
VSEL1 = H, LLC1 = H
VSEL2 = L, LLC2 = L
VSEL2 = L, LLC2 = H
VSEL2 = H, LLC2 = L
VSEL2 = H, LLC2 = H
12.74
13.72
17.64
18.62
12.74
13.72
17.64
18.62
-
13.26
14.28
18.36
19.38
13.26
14.28
18.36
19.38
40.0
60.0
80
O1
O1
O1
O1
O2
O2
O2
O2
V
V
V
V
V
V
V
Line Regulation
DV
O1,
DV
V
V
= 8V to 14V; V , V = 13V
O1 O2
mV
mV
mV
mV
mA
mA
ms
ms
IN
IN
O2
= 8V to 14V; V , V = 18V
O1 O2
-
4.0
Load Regulation
DV
DV
I
I
= 12mA to 350mA
-
50
O1,
O
O
O2
= 12mA to 750mA (Note 8)
-
100
-
200
Dynamic Output Current Limiting
I
DCL = L, ISEL1/2 = L
425
775
-
550
MAX
DCL = L, ISEL1/2 = H (Note 8)
DCL = L, Output Shorted (Note 8)
850
900
20
950
Dynamic Overload Protection Off Time
Dynamic Overload Protection On Time
TOFF
TON
-
-
-
FN9026 Rev 2.00
Jul 2004
Page 5 of 14
ISL6405
o
o
o
Electrical Specifications
V
= 12V, T = -20 C to +85 C, unless otherwise noted. Typical values are at T = 25 C. EN1 = EN2 = H,
CC A A
LLC1 = LLC2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, Iout = 12mA, unless otherwise noted.
See software description section for I C access to the system. (Continued)
2
PARAMETER
22kHz TONE SECTION
Tone Frequency
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
f
ENT1/2 = H
ENT1/2 = H
ENT1/2 = H
ENT1/2 = H
20.0
500
40
22.0
680
50
24.0
800
60
kHz
mV
%
tone
Tone Amplitude
V
tone
Tone Duty Cycle
dc
tone
Tone Rise or Fall Time
LINEAR REGULATOR
Drop-out Voltage
T , T
5
8
14
s
r
f
Iout = 750mA (Note 8)
-
1.2
-
V
DSQIN PIN
DSQIN pin logic Low
DSQIN pin Logic HIGH
DSQIN pin Input Current
CURRENT SENSE
-
3.0
-
-
-
1.5V
V
V
-
-
1
A
Pulse by Pulse Current Limit (max Vin)
Input Bias Current
150
-
200
700
400
250
-
mV
nA
I
BIAS
Over Current Threshold
ERROR AMPLIFIER
Open Loop Voltage Gain
Gain Bandwidth Product
PWM
Static current mode, DCL = H
325
500
mV
A
(Note 8)
(Note 8)
70
10
88
-
-
-
dB
OL
MHz
GBP
Maximum Duty Cycle
Minimum Pulse Width
OSCILLATOR
90
-
93
20
-
-
%
(Note 8)
ns
Oscillator Frequency
Thermal Shutdown
f
Fixed at (10)(f
)
tone
200
220
240
kHz
o
Temperature Shutdown Threshold
Temperature Shutdown Hysteresis
(Note 8)
(Note 8)
-
-
150
20
-
-
NOTES:
6. Internal Digital Soft-start
2
7. VO1 for LNB1, VO2 for LNB2. Voltage programming signals VSEL1, VSEL2, LLC1, and LLC2 are implemented via the I C bus.
IO1 = IO2 = 350mA/750mA.
8. Guaranteed by Design
FN9026 Rev 2.00
Jul 2004
Page 6 of 14
ISL6405
dedicated pin (DSQIN1/2) that allows immediate DiSEqC
data encoding separately for each LNB. (Please see Note 1
at the end of this section.) All the functions of this IC are
Functional Pin Description
SYMBOL
FUNCTION
2
2
SDA
Bidirectional data from/to I C bus.
controlled via the I C bus by writing to the system registers
2
(SR1, SR2). The same registers can be read back, and two
bits will report the diagnostic status. The internal oscillator
operates the converters at ten times the tone frequency. The
device offers full I C compatible functionality, 3.3V or 5V, and
up to 400kHz operation.
SCL
Clock from I C bus.
VSW1, 2
PGND1, 2
Input of the linear post-regulator.
2
Dedicated ground for the output gate driver of
respective PWM.
CS1, 2
Current sense input; connect Rsc at this pin for
desired over current value for respective PWM.
2
If the Tone Enable (ENT1/2) bit is set LOW through I C, then
the DSQIN1/2 terminal activates the internal tone signal,
modulating the dc output with a 0.3V, 22kHz, symmetrical
waveform. The presence of this signal usually gives the LNB
information about the band to be received.
SGND
Small signal ground for the IC.
Analog ground for the IC.
AGND
TCAP1, 2
Capacitor for setting rise and fall time of the output
of LNB A and LNB B respectively. Use this
capacitor value 1µF or higher.
Burst coding of the 22kHz tone can be accomplished due to
the fast response of the DSQIN1/2 input and rapid tone
response. This allows implementation of the DiSEqC
(EUTELSAT) protocols.
BYPASS
Bypass capacitor for internal 5V.
DSQIN1, 2
When HIGH enables internal 22kHz modulation for
LNB A and LNA B respectively, Use this pin for
tone enable function for LNB A and LNB B.
When the ENT1/2 bit is set HIGH, a continuous 22kHz tone is
generated regardless of the DSQIN1/2 pin logic status for the
corresponding regulator channel (LNB-A or LNB-B). The
ENT1/2 bit must be set LOW when the DSQIN1 and/or
DSQIN2 pin is used for DiSEqC encoding.
VCC
Main power supply to the chip.
GATE1, 2
These are the device outputs of PWM A and
PWM B respectively. These high current driver
outputs are capable of driving the gate of a power
FET. These outputs are actively held low when
Vcc is below the UVLO threshold.
Linear Regulator
The output linear regulator will sink and source current. This
feature allows full modulation capability into capacitive loads
as high as 0.25F. In order to minimize the power dissipation,
the output voltage of the internal step-up converter is adjusted
to allow the linear regulator to work at minimum dropout.
VO1, 2
ADDR
Output voltage of LNB A and LNB B respectively.
Address pin to select two different addresses per
voltage level at this pin.
COMP1, 2
FB1, 2
Error amp outputs used for compensation.
Feedback pins for respective PWMs
Charge pump connections.
When the device is put in the shutdown mode (EN1,
EN2 = LOW), both PWM power blocks are disabled. (i.e. when
EN1 = 0, PWM1 is disabled, and when EN2 = 0, PWM2 is
disabled).
CPVOUT,
CPSWIN,
CPSWOUT
SEL18V1, 2
When connected HIGH, this pin will change the
output of the respective PWM to 18V. Only
available on the QFN package option.
When the regulator blocks are active (EN1, EN2 = HIGH), the
output can be logic controlled to be 13V or 18V (typical) by
mean of the VSEL bit (Voltage Select) for remote controlling of
non-DiSEqC LNBs. Additionally, it is possible to increment by
1V (typical) the selected voltage value to compensate for the
excess voltage drop along the coaxial cable (LLC1/2 bit HIGH).
Functional Description
The ISL6405 dual output voltage regulator makes an ideal
choice for advanced satellite set-top box and personal video
recorder applications. Both supply and control voltage outputs
for two low-noise blocks (LNBs) are available simultaneously in
any output configuration. The device utilizes built-in DC/DC
step-converters that, from a single supply source ranging from
8V to 14V, generate the voltages that enable the linear post-
regulators to work with a minimum of dissipated power. An
undervoltage lockout circuit disables the circuit when VCC
drops below a fixed threshold (7.5V typ).
Output Timing
The programmed output voltage rise and fall times can be set
by an external capacitor. The output rise and fall times will be
approximately 3400 times the TCAP value. For the
recommended range of 0.47F to 2.2F, the rise and fall time
would be 1.6ms to 7.6ms. Using a 0.47F capacitor insures the
PWM stays below its overcurrent threshold when charging a
120F VSW filter cap during the worst case 13V to 19V
transition. A typical value of 1.0F is recommended. This
feature only affects the turn-on and programmed voltage rise
and fall times.
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone of
22kHz in accordance with DiSEqC (EUTELSAT) standards.
No further adjustment is required. The 22kHz oscillator can
2
Current Limiting
be controlled either by the I C interface (ENT1/2 bit) or by a
FN9026 Rev 2.00
Jul 2004
Page 7 of 14
ISL6405
TABLE 1.
SEL18V (1, 2)
High
The current limiting block has two thresholds that can be
selected by the ISEL bit of the SR and can work either
statically (simple current clamp) or dynamically. The lower
threshold is between 425mA and 530mA (ISEL = L), while the
higher threshold is between 775mA and 925mA (ISEL = H).
When the DCL (Dynamic Current Limiting) bit is set to LOW,
the over current protection circuit works dynamically: as soon
as an overload is detected, the output is shutdown for a time
2
I C BITS
O/P VOLTAGE
13V
14V
18V
19V
High
2
I C Bus Interface for ISL6405
(Refer to Philips I C Specification, Rev. 2.1)
2
t
, typically 900ms. Simultaneously the OLF bit of the
OFF
Data transmission from main microprocessor to the ISL6405 and
vice versa takes place through the two wire I C bus interface,
System Register is set to HIGH. After this time has elapsed,
the output is resumed for a time t = 20ms. During t , the
device output will be current limited to 425mA or 775mA,
depending on the ISEL bits. At the end of t , if the overload is
still detected, the protection circuit will cycle again through
2
ON ON
consisting of the two lines SDA and SCL. Both SDA and SCL are
bidirectional lines, connected to a positive supply voltage via a pull
up resistor. (Pull up resistors to positive supply voltage must be
externally connected). When the bus is free, both lines are HIGH.
The output stages of ISL6405 will have an open drain/open
collector in order to perform the wired-AND function. Data on the
ON
t
and t . At the end of a full t
in which no overload is
OFF
ON
ON
detected, normal operation is resumed and the OLF bit is reset
to LOW. Typical t + t time is 920ms as determined by an
internal timer. This dynamic operation can greatly reduce the
power dissipation in a short circuit condition, still ensuring
excellent power-on start-up in most conditions.
2
ON OFF
I C bus can be transferred up to 100Kbps in the standard-mode
or up to 400Kbps in the fast-mode. The level of logic “0” and logic
“1” is dependent of associated value of V
as per electrical
DD
specification table. One clock pulse is generated for each data bit
transferred.
However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up
when the dynamic protection is chosen. This can be solved by
initiating any power start-up in static mode (DCL = HIGH) and
then switching to the dynamic mode (DCL = LOW) after a
chosen amount of time. When in static mode, the OLF1/2 bit
goes HIGH when the current clamp limit is reached and returns
LOW when the overload condition is cleared. The OLF1/2 bit
will be LOW at the end of initial power-on soft-start.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line can
only change when the clock signal on the SCL line is LOW.
Refer to Figure 1.
SDA
Thermal Protection
This IC is protected against overheating. When the junction
temperature exceeds 150°C (typical), the step-up converter
and the linear regulator are shut off and the OTF bit of the SR
is set HIGH. Normal operation is resumed and the OTF bit is
reset LOW when the junction is cooled down to 135°C (typical).
SCL
DATA LINE CHANGE
STABLE
OF DATA
DATA VALID ALLOWED
FIGURE 1. DATA VALIDITY
In over temperature conditions, the OTF Flag goes HIGH and
2
START and STOP Conditions
the I C data will be cleared. The user may need to monitor the
2
I C enable bits and OTF flag continuously and enable the chip,
As shown in Figure 2, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
2
if I C data is cleared. OTF conditions may also make the OLF
flags go HIGH, when high capacitive loads are present or self-
heating conditions occur at higher loads.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent before
each START condition.
External Output Voltage Selection
2
The output voltage can be selected by the I C bus.
Additionally, the QFN package offers two pins (SEL18V1,
SEL18V2) for independent 13V/18V output voltage selection.
When using these pins, the I C bits should be initialized to 13V
SDA
SCL
2
status.
S
P
TABLE 1.
START
CONDITION
STOP
CONDITION
2
I C BITS
13V
SEL18V (1, 2)
Low
O/P VOLTAGE
FIGURE 2. START AND STOP WAVEFORMS
13V
14V
14V
Low
Byte Format
FN9026 Rev 2.00
Jul 2004
Page 8 of 14
ISL6405
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge
bit. Data is transferred with the most significant bit first (MSB).
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (Figure 3). The
peripheral that acknowledges has to pull down (LOW) the SDA
line during the acknowledge clock pulse, so that the SDA line
is stable LOW during this clock pulse. (Of course, set-up and
hold times must also be taken into account.)
This approach, though, is less protected from error and
decreases the noise immunity.
ISL6405 Software Description
Interface Protocol
The interface protocol is comprised of the following, as shown
below in Table 2:
The peripheral which has been addressed has to generate an
acknowledge after the reception of each byte, otherwise the
SDA line remains at the HIGH level during the ninth clock pulse
time. In this case, the master transmitter can generate the
STOP information in order to abort the transfer. The ISL6405
will not generate the acknowledge if the POWER OK signal
from the UVLO is LOW.
• A start condition (S)
• A chip address byte (MSB on left; the LSB bit determines
2
read (1) or write (0) transmission) (the assigned I C slave
address for the ISL6405 is 0001 00XX)
• A sequence of data (1 byte + Acknowledge)
• A stop condition (P)
SCL
8
2
1
9
TABLE 2. INTERFACE PROTOCOL
SDA
S
0
0
0
1
0
0
0 R/W ACK Data (8 bits) ACK P
MSB
System Register Format
START
ACKNOWLEDGE
FROM SLAVE
• R, W = Read and Write bit
• R = Read-only bit
2
FIGURE 3. ACKNOWLEDGE ON THE I C BUS
All bits reset to 0 at Power-On
TABLE 3. SYSTEM REGISTER 1 (SR1)
R, W
SR1
R, W
DCL
R, W
R, W
R, W
LLC1
R, W
R, W
EN1
R
ISEL1
ENT1
VSEL1
OLF1
TABLE 4. SYSTEM REGISTER 2 (SR2)
R, W
SR2
R, W
R, W
R, W
LLC2
R, W
R, W
EN2
R
R
ISEL2
ENT2
VSEL2
OTF
OLF2
FN9026 Rev 2.00
Jul 2004
Page 9 of 14
ISL6405
2
Transmitted Data (I C bus WRITE mode)
When the R/W bit in the chip is set to 0, the main
microprocessor as shown below. The spare bits of SR1/SR2
can be used for other functions.
microprocessor can write on the system registers (SR1/SR2)
2
of the ISL6405 via I C bus. These will be written by the
TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION
SR
0
DCL
ISEL1
ENT1
LLC1 VSEL1
EN1
1
OLF1
FUNCTION
0
0
0
1
1
0
0
1
0
1
SR1 is selected
0
1
Vout1 = 13V, Vboost1 = 13V + Vdrop
Vout1 = 18V, Vboost1 = 18V + Vdrop
Vout1 = 14V, Vboost1 = 14V + Vdrop
Vout1 = 19V, Vboost1 = 19V + Vdrop
22kHz tone is controlled by DSQIN1 pin
22kHz tone is ON, DSQIN1 is disabled
Iout1 = 425mA max.
0
1
0
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
Iout1 = 775mA max.
0
1
0
1
Dynamic current limit NOT selected
Dynamic current limit selected
PWM and Linear for channel 1 disabled
FUNCTION
0
1
0
X
X
X
X
X
0
SR
1
ISEL2
ENT2
LLC2 VSEL2
EN2
OTF
X
X
X
X
X
X
X
X
X
X
OLF2
X
SR2 is selected
1
0
0
1
1
0
1
0
1
1
1
1
1
X
Vout2 = 13V, Vboost2 = 13V + Vdrop
Vout2 = 18V, Vboost2 = 18V + Vdrop
Vout2 = 14V, Vboost2 = 14V + Vdrop
Vout2 = 19V, Vboost2 = 19V + Vdrop
22kHz tone is controlled by DSQIN2 pin
22kHz tone is ON, DSQIN2 is disabled
Iout2 = 425mA max.
1
X
1
X
1
X
1
0
1
X
1
X
1
0
1
X
X
1
X
Iout2 = 775mA max.
1
X
X
X
0
X
PWM and Linear for channel 2 disabled
FN9026 Rev 2.00
Jul 2004
Page 10 of 14
ISL6405
2
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I C commands and the
Received Data (I C bus READ MODE)
2
The ISL6405 can provide to the master a copy of the system
register information via the I C bus in read mode. The read
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6405 issues a byte on the SDA data bus line (MSB
transmitted first).
2
system register SR1 and SR2 are initialized to all zeros, thus
keeping the power blocks disabled. Once the Vcc rises above
2
UVLO, the POWER OK signal given to the I C interface block
2
will be HIGH, the I C interface becomes operative and the SRs
can be configured by the main microprocessor. About 400mV
of hysteresis is provided in the UVLO threshold to avoid false
2
At the ninth clock bit the MCU master can:
triggering of the Power-On reset circuit. (I C comes up with EN
= 0; EN goes HIGH at the same time as (or later than) all other
I C data for that PWM becomes valid).
• Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6405.
2
ADDRESS Pin
• Not acknowledge, stopping the read mode communication.
While the whole register is read back by the microprocessor,
only the two read-only bits, OLF and OTF, convey diagnostic
information about the ISL6405.
2
Connecting this pin to GND the chip I C interface address is
0001000, but, it is possible to choose between two different
addresses simply by setting this pin at one of the two fixed
voltage levels as shown in Table 8.
After selection of SR1/SR2
?
TABLE 6. ADDRESS PIN CHARACTERISTICS
2
Power–On I C Interface Reset
V
MINIMUM
TYPICAL
MAXIMUM
ADDR
2
The I C interface built into the ISL6405 is automatically reset
at power-on. The I C interface block will receive a Power OK
V
-1
0V
-
2V
ADDR
2
“0001000”
logic signal from the UVLO circuit. This signal will go HIGH
V
-2
2.7V
-
5V
ADDR
“0001001”
TABLE 7. READING SYSTEM REGISTERS
DCL
ISEL1/2
ENT1/2
LLC1/2
VSEL1/1
EN1/2
OTF2
OLF1/2
FUNCTION
T 130°C, normal operation
J
These bits are read as they were after the last write operation.
0
1
T > 150°C, power blocks disabled
J
0
1
I
I
< I
> I
, normal operation
OUT
OUT
MAX
, overload protection triggered
MAX
FN9026 Rev 2.00
Jul 2004
Page 11 of 14
ISL6405
2
I C Electrical Characteristics
2
TABLE 8. I C SPECIFICATIONS
PARAMETER
TEST CONDITION
MINIMUM
TYPICAL
MAXIMUM
Input Logic High, VIH
SDA, SCL
0.7 x V
0.3 x V
DD
Input Logic Low, VIL
SDA, SCL
SDA, SCL;
DD
Input Logic Current, IIL
10A
0.4V < V < 4.5V
IN
SCL Clock Frequency
0
100kHz
400kHz
© Copyright Intersil Americas LLC 2003-2004. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9026 Rev 2.00
Jul 2004
Page 12 of 14
ISL6405
Small Outline Exposed Pad Plastic Packages (EPSOIC)
M28.3B
N
28 LEAD WIDE BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
-B-
SYMBOL
MIN
NOMINAL
MAX
0.099
0.005
0.019
0.0125
0.711
0.299
NOTES
A
A1
B
0.091
0.001
0.014
0.0091
0.701
0.292
-
-
1
2
3
-
-
TOP VIEW
-
9
L
C
D
E
-
-
-
3
SEATING PLANE
A
-
4
-A-
D
o
h x 45
e
0.050 BSC
-
H
h
0.400
0.010
0.024
-
-
0.410
0.016
0.040
-
-C-
5
e
B
A1
L
-
6
C
0.10(0.004)
N
P
28
7
0.25(0.010) M
SIDE VIEW
C
A M B S
0°
5°
8°
-
0.180
0.156
0.214
0.190
0.218
0.194
11
11
P1
Rev. 0 5/02
1
2
3
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
P1
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
N
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: INCH.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count body size.
FN9026 Rev 2.00
Jul 2004
Page 13 of 14
ISL6405
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.18
2.95
2.95
0.23
0.30
3.25
3.25
5,8
D
5.00 BSC
-
D1
D2
E
4.75 BSC
9
3.10
7,8
5.00 BSC
-
E1
E2
e
4.75 BSC
9
3.10
7,8
0.50 BSC
-
k
0.25
0.30
-
-
-
-
L
0.40
0.50
0.15
8
L1
N
-
32
8
8
-
10
2
Nd
Ne
P
3
8
-
3
0.60
12
9
-
-
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FN9026 Rev 2.00
Jul 2004
Page 14 of 14
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