ISL6266AHRZ [RENESAS]
DUAL SWITCHING CONTROLLER, 600kHz SWITCHING FREQ-MAX, PQCC48, 7 X 7 MM, ROHS COMPLIANT, PLASTIC, QFN-48;型号: | ISL6266AHRZ |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | DUAL SWITCHING CONTROLLER, 600kHz SWITCHING FREQ-MAX, PQCC48, 7 X 7 MM, ROHS COMPLIANT, PLASTIC, QFN-48 开关 输出元件 |
文件: | 总31页 (文件大小:1403K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATASHEET
ISL6266, ISL6266A
Two-phase Core Controllers (Montevina, IMVP-6+)
FN6398
Rev 4.00
August 25, 2015
The ISL6266 and ISL6266A are two-phase buck converter
regulators implementing Intel® IMVP-6 protocol with
embedded gate drivers. Both converters use interleaved
channels to double the output voltage ripple frequency and
thereby reduce output voltage ripple amplitude with fewer
components, lower component cost, reduced power
dissipation, and smaller real estate area.
Features
• Precision Two/One-phase CORE Voltage Regulator
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• Internal Gate Driver with 2A Driving Capability
• Dynamic Phase Adding/Dropping
3
The ISL6266A utilizes the patented R Technology™,
• Microprocessor Voltage Identification Input
- 7-Bit VID Input
Intersil’s Robust Ripple Regulator modulator. Compared with
3
traditional multiphase buck regulators, the R Technology™
- 0.300V to 1.500V in 12.5mV Steps
- Support VID Change On-the-Fly
3
has the fastest transient response. This is due to the R
modulator commanding variable switching frequency during
load transient events.
• Multiple Current Sensing Schemes Supported
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
Intel Mobile Voltage Positioning (IMVP) is a smart voltage
regulation technology, which effectively reduces power
dissipation in Intel Pentium processors. To boost battery life,
the ISL6266A supports DPRSLRVR (deeper sleep),
DPRSTP# and PSI# functions, which maximizes efficiency
by enabling different modes of operation. In active mode
(heavy load), the regulator commands the two phase
continuous conduction mode (CCM) operation. When PSI#
is asserted in active mode (medium load), the ISL6266A
operates in one-phase CCM. When the CPU enters deeper
sleep mode, the ISL6266A enables diode emulation to
maximize efficiency.
• CPU Power Monitor
• Thermal Monitor
• User Programmable Switching Frequency
• Differential Remote CPU Die Voltage Sensing
• Static and Dynamic Current Sharing
• Support All Ceramic Output with Coupled Inductor
(ISL6266)
• Overvoltage, Undervoltage and Overcurrent Protection
• Pb-Free (RoHS Compliant)
For better system power management, the ISL6266A
provides a CPU power monitor output. The analog output at
the power monitor pin can be fed into an A/D converter to
report instantaneous or average CPU power.
Ordering Information
TEMP.
RANGE
(°C)
A 7-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the core output voltage from 0.300V to 1.500V.
Over-temperature, the ISL6266A achieves a 0.5% system
accuracy of core output voltage.
PART NUMBER
(Note)
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6266HRZ
(No longer
available or
supported)
ISL6266 HRZ -10 to +100 48 Ld 7x7 QFN L48.7x7
A unity-gain differential amplifier is provided for remote CPU
die sensing. This allows the voltage on the CPU die to be
accurately measured and regulated per Intel IMVP-6+
specifications. Current sensing can be realized using either
lossless inductor DCR sensing or discrete resistor sensing.
A single NTC thermistor network thermally compensates the
gain and the time constant of the DCR variations.
ISL6266HRZ-T* ISL6266 HRZ -10 to +100 48 Ld 7x7 QFN L48.7x7
(No longer
available or
supported)
ISL6266AIRZ
ISL6266A IRZ -40 to +100 48 Ld 7x7 QFN L48.7x7
ISL6266AIRZ-T* ISL6266A IRZ -40 to +100 48 Ld 7x7 QFN L48.7x7
*Please refer to TB347 for details on reel specifications.
The ISL6266 also includes all the functions for IMVP-6+
core power delivery. In addition, it has been optimized for
use with coupled-inductor solutions. More information on the
differences between ISL6266 and ISL6266A can be found in
the “Electrical Specifications” on page 3 and the “ISL6266
Features” on page 21.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN6398 Rev 4.00
August 25, 2015
Page 1 of 31
ISL6266, ISL6266A
Pinout
ISL6266, ISL6266A
(48 LD 7x7 QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
PGOOD
PSI#
BOOT1
UGATE1
PHASE1
PGND1
3
PMON
RBIAS
VR_TT#
NTC
4
5
32 LGATE1
6
31
30
29
28
27
PVCC
GND PAD
(BOTTOM)
7
SOFT
OCSET
VW
LGATE2
PGND2
PHASE2
8
9
COMP
UGATE2
10
FB 11
FB2
26 BOOT2
NC
25
12
13 14 15 16 17 18 19 20 21 22 23 24
FN6398 Rev 4.00
August 25, 2015
Page 2 of 31
ISL6266, ISL6266A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
DD
Thermal Resistance (Typical)
°C/W
JA
°C/W
JC
4.5
Battery Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
IN
QFN Package (Notes 1, 2). . . . . . . . . .
29
Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +33V
Boot to Phase Voltage (BOOT to PHASE). . . . . . -0.3V to +7V (DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V (<10ns)
Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . . PHASE -0.3V (DC) to BOOT
. . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage (LGATE) . . . . . . . . . . . -0.3V (DC) to (VDD + 0.3V)
. . . . . . . . . . . . . .-2.5V (<20ns Pulse Width, 5µJ) to (VDD + 0.3V)
All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . -0.3V to +7V
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 25V
IN
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . -40°C to +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications
V
= 5V, T = -40°C to +100°C, unless otherwise specified.
DD A
MIN
MAX
PARAMETER
INPUT POWER SUPPLY
+5V Supply Current
SYMBOL
TEST CONDITIONS
(Note 4)
TYP
(Note 4) UNITS
I
VR_ON = 3.3V
5.1
5.7
1
mA
µA
µA
µA
V
VDD
VR_ON = 0V
+3.3V Supply Current
I
No load on CLK_EN#
1
3V3
Battery Supply Current at VIN pin
POR (Power-On Reset) Threshold
I
VR_ON = 0V, V = 25V
IN
1
VIN
POR
V
V
Rising
Falling
4.35
4.15
4.5
r
DD
DD
POR
4.0
V
f
SYSTEM AND REFERENCES
System Accuracy ( ISL6266AHRZ)
%Error
No load, closed loop, active mode,
= 0°C to +100°C, VID = 0.75V to 1.5V
(V
)
T
-0.5
-8
0.5
8
%
CC_CORE
A
VID = 0.5V to 0.7375V
VID = 0.3V to 0.4875V
mV
mV
-15
15
System Accuracy (ISL6266AIRZ)
%Error
No load, closed loop, active mode,
VID = 0.75V to 1.5V
(V
)
-0.8
-10
0.8
10
%
mV
mV
V
cc_core
VID = 0.5V to 0.7375V
VID = 0.3V to 0.4875V
-18
18
RBIAS Voltage
R
R
= 147k
RBIAS
1.45
1.188
1.47
1.2
1.49
1.212
RBIAS
Boot Voltage
V
V
BOOT
Output Voltage Range
V
V
VID = [0000000]
VID = [1100000]
VID = [1111111]
1.5
V
CC_CORE
(max)
0.3
0
V
V
CC_CORE
(min)
VID Off State
FN6398 Rev 4.00
August 25, 2015
Page 3 of 31
ISL6266, ISL6266A
Electrical Specifications
V
= 5V, T = -40°C to +100°C, unless otherwise specified. (Continued)
DD A
MIN
MAX
PARAMETER
CHANNEL FREQUENCY
Nominal Channel Frequency
SYMBOL
TEST CONDITIONS
(Note 4)
TYP
(Note 4) UNITS
f
ISL6266, 2 channel operation
ISL6266A, 2 channel operation
410
280
100
440
300
470
320
600
kHz
kHz
kHz
SW
Adjustment Range
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain
-0.25
0.25
mV
dB
A
(Note 3)
90
18
5
V0
Error Amp Gain-Bandwidth Product
Error Amp Slew Rate
FB Input Current
GBW
SR
C
C
= 20pF (Note 3)
= 20pF (Note 3)
MHz
V/µs
nA
L
L
I
10
150
2
IN(FB)
ISEN
Imbalance Voltage
mV
nA
Input Bias Current
20
SOFT-START CURRENT
Soft-Start Current
I
-47
±180
-47
-42
±205
-42
-37
±230
-37
µA
µA
µA
µA
µA
SS
Soft Geyserville Current
Soft Deeper Sleep Entry Current
Soft Deeper Sleep Exit Current
Soft Deeper Sleep Exit Current
I
|SOFT - REF| > 100mV
DPRSLPVR = 3.3V
DPRSLPVR = 3.3V
DPRSLPVR = 0V
GV
I
C4
I
I
37
42
47
C4EA
C4EB
180
205
230
GATE DRIVER DRIVING CAPABILITY
UGATE Source Resistance
UGATE Source Current
R
500mA Source Current (Note 3)
1
2
1.5
1.5
1.5
0.9
A
SRC(UGATE)
I
V
= 2.5V (Note 3)
SRC(UGATE)
UGATE_PHASE
500mA Sink Current (Note 3)
= 2.5V (Note 3)
UGATE Sink Resistance
UGATE Sink Current
R
1
A
SNK(UGATE)
I
V
2
SNK(UGATE)
UGATE_PHASE
500mA Source Current (Note 3)
= 2.5V (Note 3)
LGATE Source Resistance
LGATE Source Current
R
1
A
SRC(LGATE)
I
V
2
SRC(LGATE)
LGATE
500mA Sink Current (Note 3)
V = 2.5V (Note 3)
LGATE
LGATE Sink Resistance
LGATE Sink Current
R
0.5
4
A
SNK(LGATE)
I
SNK(LGATE)
UGATE to PHASE Resistance
R
1
k
p(UGATE)
GATE DRIVER SWITCHING TIMING (refer to “ISL6266, ISL6266A Gate Driver Timing Diagram” on page 6)
UGATE Rise Time
t
PV
PV
PV
PV
= 5V, 3nF Load (Note 3)
= 5V, 3nF Load (Note 3)
= 5V, 3nF Load (Note 3)
= 5V, 3nF Load
8.0
8.0
8.0
4.0
30
ns
ns
ns
ns
ns
RU
CC
CC
CC
CC
LGATE Rise Time
t
RL
UGATE Fall Time
t
FU
LGATE Fall Time
t
FL
UGATE Turn-on Propagation Delay
t
T
= -10°C to +100°C
20
18
44
44
PDHU
ISL6266AHRZ PV
A
= 5V, Outputs Unloaded
= 5V, Outputs Unloaded
CC
CC
t
PV
30
ns
PDHU
ISL6266AIRZ
FN6398 Rev 4.00
August 25, 2015
Page 4 of 31
ISL6266, ISL6266A
Electrical Specifications
V
= 5V, T = -40°C to +100°C, unless otherwise specified. (Continued)
DD A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
= -10°C to +100°C
A
(Note 4)
TYP
(Note 4) UNITS
LGATE Turn-on Propagation Delay
t
T
7
15
30
30
ns
PDHL
ISL6266AHRZ PV
= 5V, Outputs Unloaded
CC
t
PV
= 5V, Outputs Unloaded
5
15
ns
PDHL
ISL6266AIRZ
CC
BOOTSTRAP DIODE
Forward Voltage
Leakage
V
V
= 5V, Forward Bias Current = 2mA
0.43
0.58
0.72
1
V
DDP
= 16V
µA
R
POWER GOOD and PROTECTION MONITOR
PGOOD Low Voltage
V
I
= 4mA
= 3.3V
GOOD
0.26
0.4
1
V
OL
PGOOD
PGOOD Leakage Current
PGOOD Delay
I
P
-1
6.3
µA
ms
mV
V
OH
t
CLK_EN# Low to PGOOD High
7.6
195
1.7
10
8.9
pgd
Overvoltage Threshold
Severe Overvoltage Threshold
OCSET Reference Current
OC Threshold Offset
O
V
V
rising above setpoint >1ms
rising above setpoint >0.5µs
155
1.675
9.8
235
1.725
10.2
3.5
VH
O
O
O
VHS
I(R
) = 10µA
BIAS
µA
mV
mV
mV
DROOP rising above OCSET >120µs
-3.5
Current Imbalance Threshold
Difference between ISEN1 and ISEN2 >1ms
9
Undervoltage Threshold
(VDIFF-SOFT)
UV
V
falling below setpoint for >1ms
O
-360
-300
-240
1
f
LOGIC INPUTS
VR_ON, DPRSLPVR Input Low
VR_ON, DPRSLPVR Input High
Leakage Current of VR_ON
V
V
V
IL(3.3V)
IH(3.3V)
IL(3.3V)
IH(3.3V)
V
2.3
-1
I
Logic input is low
0
0
µA
µA
µA
µA
V
I
Logic input is high at 3.3V
DPRSLPVR input is low
DPRSLPVR input is high at 3.3V
1
Leakage Current of DPRSLPVR
I
-1
0
IL_DPRSLP(3.3V)
I
0.45
1
IH_DPRSLP(3.3V)
DAC(VID0-VID6), PSI# and
DPRSTP# Input Low
V
0.3
IL(1V)
IH(1V)
IL(1V)
DAC(VID0-VID6), PSI# and
DPRSTP# Input High
V
0.7
-1
V
Leakage Current of DAC
(VID0-VID6), PSI# and DPRSTP#
I
Logic input is low
0
µA
µA
I
Logic input is high at 1V
0.45
1
IH(1V)
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
V(NTC) falling
I = 20mA
53
60
1.2
6.5
67
1.22
9
µA
V
Over-Temperature Threshold
VR_TT# Low Output Resistance
POWER MONITOR
1.18
R
TT
PMON Output Voltage Range
V
VSEN = 1.2V, Droop - V = 80mV
1.638
0.308
2.8
1.680
0.350
3.0
1.722
0.392
V
V
V
pmon
O
VSEN = 1V, Droop - V = 20mV
O
PMON Maximum Voltage
V
pmonmax
FN6398 Rev 4.00
August 25, 2015
Page 5 of 31
ISL6266, ISL6266A
Electrical Specifications
V
= 5V, T = -40°C to +100°C, unless otherwise specified. (Continued)
DD A
MIN
MAX
PARAMETER
PMON Sourcing Current
PMON Sinking Current
SYMBOL
TEST CONDITIONS
VSEN = 1V, Droop - V = 50mV
(Note 4)
TYP
(Note 4) UNITS
I
I
2
2
mA
mA
sc_pmon
sk_pmon
O
VSEN = 1V, Droop - V = 50mV
O
Maximum Current Sinking Capability
Refer to Figure 29
PMON/
PMON/
PMON/
A
250
180
100
PMON Impedance
When PMON is within its sourcing/sinking
current range (Note 3)
7
CLK_EN# OUTPUT LEVELS
CLK_EN# High Output Voltage
CLK_EN# Low Output Voltage
NOTES:
V
3V3 = 3.3V, I = -4mA
2.9
3.1
V
V
OH
V
I
EN# = 4mA
CLK_
0.26
0.4
OL
3. Limits established by characterization and are not production tested.
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
ISL6266, ISL6266A Gate Driver Timing Diagram
PWM
t
PDHU
t
FU
t
RU
1V
UGATE
LGATE
1V
t
RL
t
FL
t
PDHL
FN6398 Rev 4.00
August 25, 2015
Page 6 of 31
ISL6266, ISL6266A
Functional Pin Description
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
PGOOD
PSI#
BOOT1
UGATE1
PHASE1
PGND1
3
PMON
RBIAS
VR_TT#
NTC
4
5
32 LGATE1
6
31
30
29
PVCC
GND PAD
(BOTTOM)
7
SOFT
OCSET
VW
LGATE2
PGND2
8
9
28 PHASE2
UGATE2
COMP
10
27
26 BOOT2
NC
FB 11
FB2
12
25
13 14 15 16 17 18 19 20 21 22 23 24
FN6398 Rev 4.00
August 25, 2015
Page 7 of 31
ISL6266, ISL6266A
PGOOD - Power good open-drain output. Connect externally
with 680 to VCCP or 1.9k to 3.3V.
BOOT2 - This pin is the upper gate driver supply voltage for
Phase 2. An internal boot strap diode is connected to the
PVCC pin.
PSI# - Current indicator input. When asserted low, indicates a
reduced load-current condition and initiates single-phase
operation.
UGATE2 - Upper MOSFET gate signal for Phase 2.
PHASE2 - The phase node of Phase 2. Connect this pin to the
PMON - Analog output. PMON is proportional to the product of
source of the Channel 2 upper MOSFET.
Vsen and droop voltage.
PGND2 - The return path of the lower gate driver for Phase 2.
LGATE2 - Lower-side MOSFET gate signal for Phase 2.
PVCC - 5V power supply for gate drivers.
RBIAS - 147k resistor to VSS sets internal current reference.
VR_TT# - Thermal overload output indicator with open-drain
output. Over-temperature pull-down resistance is 10.
LGATE1 - Lower-side MOSFET gate signal for Phase 1.
PGND1 - The return path of the lower gate driver for Phase 1.
NTC - Thermistor input to VRTT# circuit and a 60µA current
source is connected internally to this pin.
SOFT - A capacitor from this pin to GND sets the maximum
slew rate of the output voltage. SOFT is the non-inverting input
of the error amplifier.
PHASE1 - The phase node of phase 1. Connect this pin to the
source of the Channel 1 upper MOSFET.
UGATE1 - Upper MOSFET gate signal for Phase 1.
OCSET - Overcurrent set input. A resistor from this pin to VO
sets DROOP voltage limit for OC trip. A 10µA current source is
connected internally to this pin.
BOOT1 - This pin is the upper-gate-driver supply voltage for
Phase 1. An internal boot strap diode is connected to the
PVCC pin.
VW - A resistor from this pin to COMP programs the switching
frequency (for example, 6.45k 400kHz).
VID0, VID1, VID2, VID3, VID4, VID5, VID6 - VID input with
VID0 is the least significant bit (LSB) and VID6 is the most
significant bit (MSB).
COMP - This pin is the output of the error amplifier.
FB - This pin is the inverting input of error amplifier.
VR_ON - Digital enable input. A logic high signal on this pin
enables the regulator.
FB2 - There is a switch between FB2 pin and the FB pin. The
switch is closed in single-phase operation and is opened in two
phase operation. The components connecting to FB2 are to
adjust the compensation in single phase operation to achieve
optimum performance.
DPRSLPVR - Deeper sleep enable signal. A logic high signal
on this pin indicates the micro-processor is in deeper-sleep
mode and also indicates a slow C4 entry or exit rate with 41µA
discharging or charging the SOFT capacitor.
VDIFF - This pin is the output of the differential amplifier.
VSEN - Remote core voltage sense input.
DPRSTP# - Deeper sleep slow wake up signal. A logic low
signal on this pin indicates the micro-processor is in
deeper-sleep mode.
RTN - Remote core voltage sense return.
CLK_EN# - Digital output for system clock. Goes active 10µs
DROOP - Output of the droop amplifier. The voltage level on
after V
is within 10% of Boot voltage.
CORE
this pin is the sum of V and the droop voltage.
O
3V3 - 3.3V supply voltage for CLK_EN#.
DFB - Inverting input to droop amplifier.
VO - An input to the IC that reports the local output voltage.
VSUM - This pin is connected to the summation junction of
channel current sensing.
VIN - Battery supply voltage. It is used for input voltage feed
forward to improve input line transient performance.
VSS - Signal ground. Connect to local controller ground.
VDD - 5V control power supply.
ISEN2 - Individual current sharing sensing for Channel 2.
ISEN1 - Individual current sharing sensing for Channel 1.
N/C - Not connected. Grounding this pin to signal ground in the
practical layout.
FN6398 Rev 4.00
August 25, 2015
Page 8 of 31
ISL6266, ISL6266A
Functional Block Diagram
6µA
54µA
PVCC
PVCC
PVCC
PVCC
VDD
PVCC
1.24V
PVCC
1.2V
VIN
DRIVER
LOGIC
DRIVER
LOGIC
VIN
ULTRASONIC
TIMER
FLT
FLT
ISEN2
CURRENT
BALANCE
ISEN1
GND
VW
VSOFT
VIN
VSOFT
VIN
I_BALF
MODULATOR
MODULATOR
OC
OC
3V3
CH2
CH1
PGOOD
Vw
PGOOD
MONITOR
AND LOGIC
CLK_EN#
CH1
CH2
COMP
FB2
Vw
SINGLE
PHASE
PHASE
SEQUENCER
VO
PHASE
CONTROL
LOGIC
E/A
-
VIN
P
FLT
GOOD
FB
SINGLE
PHASE
SOFT
PMON
VDIFF
FAULT AND
PGOOD
LOGIC
VSOFT
OC
VO
SOFT
-
SINGLE
PHASE
1
-
1
-
0.5
DACOUT
RTN
VSEN
VO
VO
DROOP
MODE
CONTROL
10µA
RBIAS
DAC
-
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6266, ISL6266A
FN6398 Rev 4.00
August 25, 2015
Page 9 of 31
ISL6266, ISL6266A
Typical Performance Curves
1.16
1.14
1.12
1.10
1.08
1.06
1.04
100
90
V
V
= 8.0V
IN
80
70
60
50
40
30
20
10
0
V
= 8.0V
IN
V
= 12.6V
V
= 19.0V
IN
IN
V
= 12.6V
IN
= 19.0V
IN
0
5
10
15
20
25
(A)
30
35
40
45
50
0
10
20
30
40
50
I
I
(A)
OUT
OUT
FIGURE 2. ACTIVE MODE EFFICIENCY, 2-PHASE, CCM,
PSI# = HIGH, VID = 1.15V
FIGURE 3. ACTIVE MODE LOAD LINE, 2-PHASE, CCM,
PSI# = HIGH, VID = 1.15V
100
90
1.01
V
= 8.0V
IN
V
= 12.6V
1.00
0.99
0.98
0.97
0.96
0.95
0.94
IN
80
70
60
50
40
30
20
10
0
V
= 8.0V
IN
V
= 12.6V
IN
V
= 19.0V
IN
V
= 19.0V
IN
0
5
10
15
20
25
0
5
10
15
20
25
I
(A)
I
(A)
OUT
OUT
FIGURE 4. ACTIVE MODE EFFICIENCY, 1-PHASE, CCM,
PSI# = LOW, VID = 1.00V (ISL6266 ONLY)
FIGURE 5. ACTIVE MODE LOAD LINE, 1-PHASE, CCM,
PSI# = LOW, VID = 1.00V (ISL6266 ONLY)
0.765
0.764
0.763
100
90
80
V
= 12.6V
IN
70
0.762
0.761
0.760
0.759
0.758
0.757
V
= 8.0V
IN
60
50
40
30
20
10
0
V
= 19.0V
IN
V
= 12.6V
IN
V
= 19.0V
IN
V
= 8.0V
IN
0
1
2
3
0.1
1.0
(A)
10.0
I
(A)
I
OUT
OUT
FIGURE 6. DEEPER SLEEP MODE EFFICIENCY
FIGURE 7. DEEPER SLEEP MODE LOAD LINE
FN6398 Rev 4.00
August 25, 2015
Page 10 of 31
ISL6266, ISL6266A
Typical Performance Curves (Continued)
VR_ON
V
OUT
V
OUT
V
SOFT
VR_ON
V
SOFT
C
= 15nF
SOFT
C
= 15nF
SOFT
FIGURE 8. SOFT-START WAVEFORM SHOWING SLEW RATE
OF 2.5mV/µs AT VID = 1V, I = 0A
FIGURE 9. SOFT-START WAVEFORM SHOWING SLEW RATE
OF 2.5mV/µs AT VID = 1.4375V, I = 0A
LOAD
LOAD
CLK_EN#
V
IN
IMVP-6_PWRGD
I
IN
V
@ 1.15V
OUT
V
OUT
FIGURE 10. SOFT-START WAVEFORM SHOWING CLK_EN#
AND IMVP-6 PGOOD
FIGURE 11. 8V TO 20V INPUT LINE TRANSIENT RESPONSE,
= 240µF
C
IN
VR_ON
DPRSTP#
VID6
V
OUT
DPRSLPVR
I
IN
V
OUT
FIGURE 12. NRUSH CURRENT AT START-UP, V = 14.6V,
IN
FIGURE 13. SLOW C4 EXIT WITH DELAY OF DPRSLPVR,
FROM VID1000000 (0.7V) TO 0110000 (0.9V)
VID = 1.4375V, I
= 5A
LOAD
FN6398 Rev 4.00
August 25, 2015
Page 11 of 31
ISL6266, ISL6266A
Typical Performance Curves (Continued)
V
OUT
V
OUT
FIGURE 14. LOAD STEP-UP RESPONSE AT THE CPU
SOCKET MPGA479, 35A LOAD STEP @
1000A/µs, 2-PHASE CCM
FIGURE 15. LOAD DUMP RESPONSE AT THE CPU SOCKET
MPGA479, 35A LOAD STEP @ 1000A/µs,
2-PHASE CCM
VID3
VID3
V
V
OUT
OUT
PHASE1
PHASE2
PHASE1
PHASE2
FIGURE 16. VID3 CHANGE OF 010X000 FROM 1V TO 1.1V
WITH DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
FIGURE 17. VID3 CHANGE OF 010X000 FROM 1.1V TO 1V
WITH DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
PSI#
PSI#
V
V
OUT
OUT
PHASE1
PHASE2
PHASE1
PHASE2
FIGURE 18. 2-CCM TO 1-CCM UPON PSI# ASSERTION WITH
DPRSLPVR = 0, DPRSTP# = 1
FIGURE 19. 1-CCM TO 2-CCM UPON PSI# DEASSERTION
WITH DPRSLPVR = 0, DPRSTP# = 1
FN6398 Rev 4.00
August 25, 2015
Page 12 of 31
ISL6266, ISL6266A
Typical Performance Curves (Continued)
DPRSLPVR
DPRSLPVR/PSI
V
OUT
V
OUT
PHASE1
PHASE2
PHASE1
PHASE2
FIGURE 20. C4 ENTRY WITH VID CHANGE 0011X00 FROM
1.2V TO 1.15V, I = 2A, TRANSITION OF
FIGURE 21. VID3 CHANGE OF 010X000 FROM 1V TO 1.1V
WITH DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
LOAD
2-CCM TO 1-DCM, PSI# TOGGLE FROM 1 TO 0
WITH DPRSLPVR FROM 0 TO 1
V
DPRSLPVR
OUT
V
OUT
IMVP-6_PWRGD
PHASE1
PHASE2
I
OUT
FIGURE 22. C4 ENTRY WITH VID CHANGE OF 011X011 FROM
FIGURE 23. OVERCURRENT PROTECTION
0.8625V TO 0.7625V, I
1-DCM
= 3A, 1-CCM TO
LOAD
VID3
IMVP-6_PWRGD
V
OUT
V
OUT
PMON UNFILTERED
PMON FILTERED
PHASE1
FIGURE 25. VID TRANSITION FROM 1V TO 1.10V I
= 24A,
LOAD
FIGURE 24. 1.7V OVERVOLTAGE PROTECTION SHOWS
OUTPUT VOLTAGE PULLED TO 0.9V AND PWM
TRI-STATE
EXTERNAL FILTER 40k AND 100pF AT PMON
FN6398 Rev 4.00
August 25, 2015
Page 13 of 31
ISL6266, ISL6266A
Typical Performance Curves (Continued)
V
OUT
V
OUT
PMON UNFILTERED
PMON FILTERED
PMON UNFILTERED
PMON FILTERED
FIGURE 27. VID = 1.15V, LOAD APPLICATION FROM
0A TO 36A WITH INTEL VTT TOOL, 1kHz RATE,
50% DUTY CYCLE, TR = 35
FIGURE 26. VID = 1.15V, LOAD TRANSIENT OF 0A TO 36A
WITH INTEL VTT TOOL, 1kHz RATE, 50% DUTY
CYCLE, TR = 35
V
OUT
PMON UNFILTERED
PMON FILTERED
FIGURE 28. VID = 1.15V, LOAD RELEASE FROM 36A TO 0A WITH INTEL VTT TOOL, 1kHz RATE, 50% DUTY CYCLE, TR = 35
1.8
0.8
VID = 1.15V, I
= 15A
OUT
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
7
19V, 1.15V, 40A
19V, 1.15V, 20A
VID = 1.15V, I
OUT
= 10A
19V, 1.15V, 30A
180
19V, 1.15V, 10A
19V, 1.15V, 5A
VID = 1.15V, I
OUT
= 5A
VID = 1.15V, I
= 2.5A
OUT
0
1
2
3
4
5
6
7
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
CURRENT SINKING (mA)
CURRENT SOURCING (mA)
FIGURE 29. POWER MONITOR CURRENT SOURCING
CAPABILITY
FIGURE 30. POWER MONITOR CURRENT SINKING
CAPABILITY
FN6398 Rev 4.00
August 25, 2015
Page 14 of 31
ISL6266, ISL6266A
Simplified Coupled Inductor Application Circuit for DCR Current Sensing
+5V
V
+3.3V
IN
R
12
3V3
VDD
PVCC VIN
V
RBIAS
IN
NTC
ISL6266
C
7
R
C
13
8
VR_TT#
VR_TT#
SOFT
UGATE1
BOOT1
C
6
VID<0:6>
DPRSTP#
VIDs
PHASE1
R
8
DPRSTP#
VSUM
LGATE1
PGND1
DPRSLPVR
PSI#
DPRSLPVR
PSI#
ISEN1
ISEN1
PMON
CLK_ENABLE#
CLK_EN#
VR_ON
C
VO'
R
L
L
V
IN
VR_ON
C
PGOOD
VSEN
8
IMVP-6_PWRGD
R
10
V
O
REMOTE
SENSE
UGATE2
BOOT2
RTN
L
O
R
2
C
C
O
5
VDIFF
PHASE2
R
C
3
3
R
11
C
R
L
L
R
7
LGATE2
PGND2
FB2
FB
VO'
R
9
C
C
R
1
2
1
VSUM
COMP
ISEN2
VSUM
ISEN2
R
VSUM
FSET
VW
OCSET
GND DFB
DROOP VO
C
9
R
5
R
NTC
N
C
CS
R
6
NETWORK
C
4
R
4
VO'
FIGURE 31. ISL6266 BASED TWO-PHASE COUPLED INDUCTOR DESIGN WITH DCR SENSING
FN6398 Rev 4.00
August 25, 2015
Page 15 of 31
ISL6266, ISL6266A
Simplified Application Circuit for DCR Current Sensing
+5V
V
IN
+3.3V
R
12
3V3
VDD
PVCC VIN
V
RBIAS
IN
NTC
ISL6266A
C
7
R
C
13
8
VR_TT#
VR_TT#
SOFT
UGATE1
BOOT1
L
O
C
6
VID<0:6>
DPRSTP#
VIDs
PHASE1
R
10
DPRSTP#
C
R
L
L
LGATE1
PGND2
ISEN1
DPRSLPVR
PSI#
VO'
DPRSLPVR
PSI#
R
8
V
O
VSUM
ISEN1
PMON
C
O
CLK_ENABLE#
CLK_EN#
VR_ON
V
IN
VR_ON
C
PGOOD
VSEN
8
IMVP-6_PWRGD
REMOTE
SENSE
UGATE2
BOOT2
L
RTN
O
R
2
C
5
VDIFF
PHASE2
R
C
3
3
R
11
C
R
L
L
R
7
LGATE2
PGND2
FB2
FB
ISEN2
VO'
R
9
C
C
R
1
2
1
VSUM
COMP
ISEN2
VSUM
R
VSUM
FSET
VW
OCSET
GND DFB
DROOP VO
C
9
R
5
R
C
N
CS
R
6
NTC
NETWORK
C
4
R
4
VO'
FIGURE 32. ISL6266A BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING
FN6398 Rev 4.00
August 25, 2015
Page 16 of 31
ISL6266, ISL6266A
Simplified Application Circuit for Resistive Current Sensing
+5V
V
IN
+3.3V
R
11
3V3
VDD
PVCC VIN
V
RBIAS
IN
ISL6266A
NTC
C
7
R
C
12
9
VR_TT#
VR_TT#
SOFT
UGATE1
BOOT1
L
R
S
C
6
VID<0:6>
DPRSTP#
VIDs
PHASE1
R
10
DPRSTP#
C
R
L
L
LGATE1
PGND2
ISEN2
DPRSLPVR
PSI#
VO'
DPRSLPVR
PSI#
R
8
V
O
VSUM
ISEN1
PMON
C
O
CLK_ENABLE#
CLK_EN#
VR_ON
V
IN
VR_ON
C
8
PGOOD
VSEN
IMVP-6_PWRGD
REMOTE
SENSE
UGATE2
BOOT2
L
RTN
R
S
R
2
C
5
VDIFF
PHASE2
C
R
3
3
R
11
C
R
L
L
R
7
LGATE2
PGND2
FB2
FB
ISEN2
VO'
R
9
C
C
R
1
2
1
VSUM
COMP
ISEN2
VSUM
R
VSUM
FSET
VW
OCSET
GND DFB
DROOP VO
C
9
R
5
C
HF
R
6
C
4
R
4
VO'
FIGURE 33. ISL6266A BASED TWO-PHASE BUCK CONVERTER WITH RESISTIVE CURRENT SENSING
FN6398 Rev 4.00
August 25, 2015
Page 17 of 31
ISL6266, ISL6266A
Theory of Operation
V
DD
The ISL6266A is a two-phase regulator implementing Intel®
IMVP-6 protocol and includes embedded gate drivers for
reduced system cost and board area. The regulator provides
optimum steady-state and transient performance for
microprocessor core applications up to 50A. System efficiency
is enhanced by idling one phase at low-current and
implementing automatic DCM-mode operation.
10mV/µs
2.8mV/µs
VR_ON
100µs
VBOOT
VID COMMANDED
VOLTAGE
SOFT AND VO
90%
3
The heart of the ISL6266A is R Technology™, Intersil’s
Robust Ripple Regulator modulator. The R modulator
13 SWITCHING CYCLES
3
CLK_EN#
combines the best features of fixed frequency PWM and
hysteretic PWM while eliminating many of their shortcomings.
The ISL6266A modulator internally synthesizes an analog of
the inductor ripple current and uses hysteretic comparators on
those signals to establish PWM pulse widths. Operating on
these large-amplitude, noise-free synthesized signals allows
the ISL6266A to achieve lower output ripple and lower phase
jitter than either conventional hysteretic or fixed frequency
PWM controllers. Unlike conventional hysteretic converters,
the ISL6266A has an error amplifier that allows the controller to
maintain a 0.5% voltage regulation accuracy throughout the
VID range from 0.75V to 1.5V.
~7ms
IMVP-6 PGOOD
FIGURE 34. SOFT-START WAVEFORMS USING A 15nF SOFT
CAPACITOR
Static Operation
After the start sequence, the output voltage will be regulated to
the value set by the VID inputs shown in Table 1. The entire
VID table is presented in the intel IMVP-6 specification. The
ISL6266A will control the no-load output voltage to an accuracy
of ±0.5% over the range of 0.75V to 1.5V.
TABLE 1. TRUNCATED VID TABLE FOR INTEL IMVP-6+
SPECIFICATION
The hysteresis window voltage is relative to the error amplifier
output such that load current transients results in increased
switching frequency, which gives the R regulator a faster
3
VOUT
VID6 VID5 VID4 VID3 VID2 VID1 VID0
(V)
1.5000
1.4875
1.4375
1.2875
1.15
response than conventional fixed frequency PWM controllers.
Transient load current is inherently shared between active
phases due to the use of a common hysteretic window voltage.
Individual average phase voltages are monitored and
controlled to equally share the static current among the active
phases.
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
1
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
1
1
0
1
1
0
1
Start-Up Timing
With the controller's VDD voltage above the POR threshold,
the start-up sequence begins when VR_ON exceeds the 3.3V
logic HIGH threshold. Approximately 100µs later, SOFT and
VOUT begin ramping to the boot voltage of 1.2V. At start-up,
the regulator always operates in a 2-phase CCM mode
regardless of control signal assertion levels. During this
interval, the SOFT capacitor is charged by 41µA current
source. If the SOFT capacitor is selected to be 20nF, the SOFT
ramp will be at 2mV/µs for a soft-start time of 600µs. Once
VOUT is within 10% of the boot voltage for 13 PWM cycles
(43µs for frequency = 300kHz), then CLK_EN# is pulled LOW
and the SOFT capacitor is charged/discharged by
0.8375
0.7625
0.3000
0.0000
A fully-differential amplifier implements core voltage sensing
for precise voltage control at the microprocessor die. The
inputs to the amplifier are the VSEN and RTN pins.
As the load current increases from zero, the output voltage will
droop from the VID table value by an amount proportional to
current to achieve the IMVP-6+ load line. The ISL6266A
provides options for current to be measured using either
resistors in series with the channel inductors as shown in the
application circuit of Figure 33, or using the intrinsic series
resistance of the inductors as shown in the application circuit of
Figure 32. In both cases, signals representing the inductor
currents are summed at VSUM, which is the non-inverting
input to the DROOP amplifier shown in the block diagram of
Figure 1. The voltage at the DROOP pin minus the output
voltage, VO´, is a high-bandwidth analog of the total inductor
approximately 200µA. Therefore, VOUT slews at 10mV/µs to
the voltage set by the VID pins. Approximately 7ms later,
PGOOD is asserted HIGH. Typical start-up timing is shown in
Figure 34.
FN6398 Rev 4.00
August 25, 2015
Page 18 of 31
ISL6266, ISL6266A
current. This voltage is used as an input to a differential
amplifier to achieve the IMVP-6+ load line, and also as the
input to the overcurrent protection circuit.
idled. This configuration will minimize switching losses, while
still maintaining transient response capability. At the lowest
current levels, the controller automatically configures the
system to operate in single-phase automatic-DCM mode, thus
achieving the highest possible efficiency. In this mode of
operation, the lower MOSFET will be configured to
automatically detect and prevent discharge current flowing
from the output capacitor through the inductors, and the
switching frequency will be proportionately reduced, thus
greatly reducing both conduction and switching losses.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus maintaining the load-line
accuracy.
In addition to monitoring the total current (used for DROOP
and overcurrent protection), the individual channel average
currents are also monitored and used for balancing the load
between channels. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channel to cause
the voltages presented at the ISEN pins to be equal.
3
Smooth mode transitions are facilitated by the R
Technology™, which correctly maintains the internally
synthesized ripple currents throughout mode transitions. The
controller is thus able to deliver the appropriate current to the
load throughout mode transitions. The controller contains
embedded mode-transition algorithms that maintain
voltage-regulation for all control signal input sequences and
durations.
The ISL6266A controller can be configured for two-channel
operation, with the channels operating 180° apart. The channel
PWM frequency is determined by the value of R
FSET
connected to pin VW as shown in Figures 32 and 33. Input and
output ripple frequencies will be the channel PWM frequency
multiplied by the number of active channels.
While the ISL6266A will respond according to the logic states
shown in Table 2, it can deviate from the commanded state
during sleep state exit. If the core voltage is directed by the
CPU to make a VID change that causes excessive output
capacitor inrush current when going from 1-phase DCM to 1-
phase CCM, the controller will automatically add Phase 2 until
the VID transition is complete. This is beneficial for designs
High Efficiency Operation Mode
The ISL6266A has several operating modes to optimize
efficiency. The controller's operational modes are designed to
work in conjunction with the Intel IMVP-6+ control signals to
maintain the optimal system configuration for all IMVP-6+
conditions. These operating modes are established by the
IMVP-6+ control signal inputs PSI#, DPRSLPVR, and
DPRSTP# as shown in Table 2. At high current levels, the
system will operate with both phases fully active, responding
rapidly to transients and delivering maximum power to the
load. At reduced load-current levels, one of the phases may be
that have very large C
values.
OUT
The controller contains internal counters that prevent spurious
control signal glitches from resulting in unwanted mode
transitions. Control signals of less than two switching periods
do not result in phase-idling.
TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL6266 AND ISL6266A
DPRSTP# PSI# ISL6266 ISL6266A VID SLEW RATE
1-phase CCM 1-phase diode emulation fast
DPRSLPVR
CPU MODE
awake
awake
awake
awake
sleep
0
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
2-phase CCM
1-phase CCM
2-phase CCM
2-phase CCM
fast
fast
0
1-phase diode emulation
2-phase CCM
0
fast
1
1-phase diode emulation 1-phase diode emulation
1-phase diode emulation 1-phase diode emulation
slow (Note 5)
slow (Note 5)
slow
1
sleep
1
1
1-phase CCM
2-phase CCM
1-phase diode emulation
2-phase CCM
awake
awake
slow
NOTE:
5. The negative VID slew rate when DPRSTP# = 0 and DPRSLPVR = 1 is limited to no faster than the slow slew rate. However, slower slew rates
can be seen. To conserve power, the ISL6266A will tri-state UGATE and LGATE and let the load gradually pull the core voltage back into
regulation.
FN6398 Rev 4.00
August 25, 2015
Page 19 of 31
ISL6266, ISL6266A
While transitioning to single-phase operation, the controller
smoothly transitions current from the idling-phase to the active-
phase, and detects the idling-phase zero-current condition.
During transitions into automatic-DCM or forced-CCM mode, the
timing is carefully adjusted to eliminate output voltage excursions.
When a phase is added, the current balance between phases is
quickly restored.
The ISL6266A can be configured to operate as a single phase
regulator using the same layout as a two phase design to
accommodate lower power CPUs. To accomplish this, the
designer must connect ISEN1 and ISEN2 to VCC_PRM
(reference AN1376 for signal names). Channel 2 components
can be removed as well as current balance circuitry. The
ISL6266A will power-up and regulate in DCM or CCM based
on the state of PSI#, as outlined in Table 2. The OCP threshold
will also change based on the state of PSI#, as outlined in
“Protection” on page 20.
When commanded into 1-phase CCM operation according to
Table 2, both MOSFETs of Phase 2 will be off. The controller
will thus eliminate switching losses associated with the
unneeded channel.
Dynamic Operation
V
AND V
SOFT
OUT
Figure 35 shows that the ISL6266A responds to changes in
VID command voltage by slewing to new voltages with a dV/dt
set by the SOFT capacitor and by the state of DPRSLPVR.
10mV/µs
-2.5mV/µs
With C
= 15nF and DPRSLPVR HIGH, the output voltage
SOFT
will move at ±2.8mV/µs for large changes in voltage. For
DPRSLPVR LOW, the large signal dV/dt will be ±10mV/µs. As
the output voltage approaches the VID command value, the
dV/dt moderates to prevent overshoot.
2.5mV/µs
DPRSLPVR
Keeping DPRSLPVR HIGH for voltage transitions into and out
of Deeper Sleep will result in low dV/dt output voltage changes
with resulting minimized audio noise. For fastest recovery from
Deeper Sleep to Active mode, holding DPRSLPVR LOW
results in maximum dV/dt. Therefore, the ISL6266A is IMVP-6+
compliant for DPRSTP# and DPRSLPVR logic.
VID#
FIGURE 35. DEEPER SLEEP TRANSITION SHOWING
DPRSLPVR'S EFFECT ON EXIT SLEW RATE
3
Intersil's R Technology™ has intrinsic voltage feedforward. As
When commanded to single-phase DCM mode, both
MOSFETs associated with Phase 2 are off, and the ISL6266A
turns off the lower MOSFET of Channel 1 whenever the
Channel 1 current decays to zero. As load is further reduced,
the Phase 1 channel switching frequency decreases to
maintain high efficiency. The operation of the inactive for 1-
phase DCM and 1-phase CCM described previously refers to
the ISL6266A only. See “ISL6266 Features” on page 21 for
information on the ISL6266.
a result, high-speed input voltage steps do not result in
significant output voltage perturbations. In response to load
current step increases, the ISL6266A will transiently raise the
switching frequency so that response time is decreased and
current is shared by two channels.
Protection
The ISL6266A provides overcurrent, overvoltage, undervoltage
protection and over-temperature protection, as shown in Table
3.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6266, ISL6266A
FAULT DURATION PRIOR
TO PROTECTION
PROTECTION ACTIONS
FAULT RESET
Overcurrent fault
120µs
<2µs
PWM1, PWM2 three-state, PGOOD latched low
PWM1, PWM2 three-state, PGOOD latched low
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
Way-Overcurrent fault
Overvoltage fault (1.7V)
Immediately
Low-sideMOSFETonuntilV <0.85V, then PWM VDD toggle
CORE
three-state, PGOOD latched low (0V to 1.7V always)
PWM1, PWM2 three-state, PGOOD latched low
PWM1, PWM2 three-state, PGOOD latched low
Overvoltage fault (+200mV)
1ms
1ms
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
Undervoltage fault
(-300mV)
Current imbalance fault
(7.5mV)
1ms
PWM1, PWM2 three-state, PGOOD latched low
VR_TT# goes low
VR_ON toggle or VDD toggle
N/A
Over-temperature fault
(NTC <1.18V)
Immediately
FN6398 Rev 4.00
August 25, 2015
Page 20 of 31
ISL6266, ISL6266A
Overcurrent protection is tied to the voltage droop, which is
determined by the resistors selected as described in
throttling to the system oversight processor. No other action is
taken within the ISL6266A in response to NTC pin voltage.
“Component Selection and Application” on page 22. After the
load-line is set, the OCSET resistor can be selected to detect
overcurrent at any level of droop voltage. An overcurrent fault
will occur when the load current exceeds the overcurrent
setpoint voltage while the regulator is in a 2-phase mode.
While the regulator is in a 1-phase mode of operation, the
overcurrent setpoint is automatically reduced to 50% of two-
phase overcurrent level, and the fast-trip way-overcurrent set
point is reduced to 66%. For overcurrents less than 2.5 times
the OCSET level, the over-load condition must exist for 120µs
in order to trip the OC fault latch. This is shown in Figure 25.
Power Monitor
The power monitor signal is an analog output. Its magnitude is
proportional to the product of V
difference between V
voltage droop value, equal to load current multiplied by the
load line impedance (for example 2.1m). The output voltage
of the PMON pin in two-phase design is given by Equation 1:
and the voltage
CCSENSE
and V which is the programmed
droop
O,
(EQ. 1)
V
= V
V
– V 17.5
DROOP O
PMON
CCSENSE
Equation 1 can be expressed in terms of load current as seen
in Equation 2:
For over-loads exceeding 2.5 times the set level, the PWM
outputs will immediately shut off and PGOOD goes low to
maximize protection due to hard shorts.
(EQ. 2)
V
= V
I
2.1m 17.5
PMON
CCSENSE CORE
The power consumed by the CPU can be calculated by
Equation 3:
In addition, excessive phase imbalance (for example, due to
gate driver failure) will be detected in two-phase operation and
the controller will be shut-down 1ms after detection of the
excessive phase current imbalance. The phase imbalance is
detected by the voltage on the ISEN pins if the difference is
greater than 9mV.
(EQ. 3)
P
= V
17.5 0.0021 WATT
PMON
CPU
where 0.0021 is the typical load line slope. The power monitor
load regulation is approximately 7. Within its sourcing/sinking
current capability range, when the power monitor loading
changes to 1mA, the output of the power monitor will change to
7mV. The 7 impedance is associated with the layout and
package resistance of PMON inside the IC. In practical
applications, compared to the load resistance on the PMON
pin, 7 output impedance contributes no significant error.
Undervoltage protection is independent of the overcurrent limit.
If the output voltage is less than the VID set value by 300mV or
more, a fault will latch after 1ms in that condition, turning the
PWM outputs off and pulling PGOOD to ground. Note that
most practical core regulators will have the overcurrent set to
trip before the -300mV undervoltage limit.
There are two levels of overvoltage protection and response.
ISL6266 Features
The ISL6266 incorporates all the features previously listed for
the ISL6266A. However, the sleep state logic is slightly altered
(see Table 2). In addition to those differences, the ISL6266 has
been optimized to work with coupled-inductor solutions. Due to
mutual magnetic fields between the individual phase windings
of the coupled-inductor, the effective per-phase inductance
equals the leakage inductance of the transformer. This can be
very low (e.g. 90nH), which allows for faster channel current
slew rates and, consequently, an all-ceramic output capacitor
bank can be utilized. Additionally, the current ripple is lower
than would be produced with two discrete inductors of
equivalent value to the coupled-inductor leakage. This
improves coupled-inductor efficiency over discrete inductor
solutions for the same transient response.
1. For output voltage exceeding the set value by +200mV for
1ms, a fault is declared. All of the above faults have the
same action taken: PGOOD is latched low and the upper
and lower power MOSFETs are turned off so that inductor
current will decay through the MOSFET(s) body diode(s).
This condition can be reset by bringing VR_ON low or by
bringing VDD below 4V. When these inputs are returned to
their high operating levels, a soft-start will occur.
2. The second level of overvoltage protection behaves
differently (see Figure 26). If the output exceeds 1.7V, an
OV fault is immediately declared, PGOOD is latched low
and the low-side MOSFETs are turned on. The low-side
MOSFETs will remain on until the output voltage is pulled
down below about 0.85V, at which time all MOSFETs are
turned off. If the output again rises above 1.7V, the
protection process is repeated. This offers the maximum
amount of protection against a shorted high-side MOSFET
while preventing output ringing below ground. The 1.7V OV
is not reset with VR_ON, but requires that VDD be lowered
to reset. The 1.7V OV detector is active at all times that the
controller is enabled including after one of the other faults
occurs so that the processor is protected against high-side
MOSFET leakage while the MOSFETs are commanded off.
In single phase operation, the active channel inductor will
continue to build a mutual field in the inactive channel inductor.
This field must be dissipated every cycle to maintain inductor volt-
second balance. The ISL6266 continues to turn on the lower
MOSFET for the inactive channel to deplete the induced field with
minimum power loss.
The ISL6266A has a thermal throttling feature. If the voltage on
the NTC pin goes below the 1.2V over-temperature threshold,
the VR_TT# pin is pulled low indicating the need for thermal
FN6398 Rev 4.00
August 25, 2015
Page 21 of 31
ISL6266, ISL6266A
The IMVP-6+ specification dictates the critical timing
associated with regulating the output voltage. The symbol,
SLEWRATE, as given in the IMVP-6+ specification will
Component Selection and Application
Soft-Start and Mode Change Slew Rates
The ISL6266A uses two slew rates for various modes of
operation. The first is a slow slew rate used to reduce in-rush
current during start-up. It is also used to reduce audible noise
when entering or exiting Deeper Sleep Mode. A faster slew rate is
used to exit out of Deeper Sleep and to enhance system
performance by achieving active mode regulation more quickly.
Note that the SOFT capacitor current is bidirectional. The current
is flowing into the SOFT capacitor when the output voltage is
commanded to rise and out of the SOFT capacitor when the
output voltage is commanded to fall.
determine the choice of the SOFT capacitor (C
Equation 4.
) by
SOFT
I
GV
(EQ. 4)
-----------------------------------
C
=
SOFT
SLEWRATE
Using a SLEWRATE of 10mV/µs and the typical I
value
GV
given in the “Electrical Specifications” table on page 4 of
205µA, C is as shown in Equation 5.
SOFT
= 205A 10mV 1s
(EQ. 5)
C
SOFT
A choice of 0.015µF would guarantee a SLEWRATE of
10mV/µs is met for the minimum I value given in the
Figure 36 illustrates how the two slew rates are determined by
commanding one of two current sources into or out of the
SOFT pin. The capacitor from the SOFT pin to ground holds
the voltage commanded by the two current sources. The
voltage is fed into the non-inverting input of the error amplifier
and sets the regulated system voltage. Depending on the state
of the system (Start-Up or Active mode) and the state of the
DPRSLPVR pin, one of the two currents shown in Figure 36
will be used to charge or discharge this capacitor, thereby
controlling the slew rate of the newly commanded voltage.
These currents can be found under “SOFT-START CURRENT”
on page 4 of the “Electrical Specifications” table.
GV
“Electrical Specifications” table on page 4. This choice of
will then control the start-up slewrate as well. One
C
SOFT
should expect the output voltage to slew to the boot value of
1.2V at a rate given by Equation 6.
I
dV
41A
SS
(EQ. 6)
-------
-------------------
----------------------
= 2.8mV s
=
=
dt
C
0.015F
SOFT
Selecting RBIAS
To properly bias the ISL6266A, a reference current is
established by placing a 147k, 1% tolerance resistor from the
RBIAS pin to ground. This will provide a highly accurate 10µA
current source from which the OCSET reference current can
be derived.
ISL6266, ISL6266A
Care should be taken in layout that the resistor is placed very
close to the RBIAS pin and that a good quality signal ground is
connected to the opposite side of the RBIAS resistor. Do not
connect any other components to this pin as this would
negatively impact performance. Capacitance on this pin would
create instabilities and should be avoided.
I
SS
I
ERROR
AMPLIFIER
2
+
SOFT
Start-Up Operation - CLK_EN# and PGOOD
+
The ISL6266A provides a 3.3V logic output pin for CLK_EN#.
The 3V3 pin allows for a system 3.3V source to be connected
to separated circuitry inside the ISL6266A, solely devoted to
the CLK_EN# function. The output is a 3.3V CMOS signal with
4mA sourcing and sinking capability. This implementation
removes the need for an external pull-up resistor on this pin,
thereby removing a leakage path from the 3.3V supply to
ground when the logic state is low. The lack of superfluous
current leakage paths serves to prolong battery life. For noise
immunity, the 3.3V supply should be decoupled to digital
ground rather than to analog ground.
V
REF
C
SOFT
FIGURE 36. SOFT PIN CURRENT SOURCES FOR FAST AND
SLOW SLEW RATES
The first current, labeled I , is given in the “Electrical
SS
Specifications” table on page 4 as 42µA. This current is used
during soft-start. The second current (I ) sums with I to get
the larger of the two currents, labeled I
Specifications” table on page 4. This total current is typically
205µA with a minimum of 180µA.
2
SS
in the “Electrical
GV
As mentioned in “Theory of Operation” on page 18, CLK_EN#
is logic level high at start-up until approximately 43µs after the
V
is in regulation at the Boot level. Afterwards,
CC_CORE
CLK_EN# transitions low, triggering an internal timer for the
IMVP6_PWRGD signal. When the timer reaches 6.8ms,
IMVP-6_PWRGD will toggle high.
FN6398 Rev 4.00
August 25, 2015
Page 22 of 31
ISL6266, ISL6266A
ISEN1
ISEN2
ISEN2
ISEN1
10µA
R
OCSET
OCSET
VO'
I
PHASE1
Vdcr
1
-
-
L
1
OC
+
+
VSUM
DFB
DCR
VSUM
RS
+
VSUM
C
DROOP
L1
INTERNAL TO
ISL6266
R
RO1
L1
-
R
SERIES
Cn
DROOP
+
1
ISEN1
VO'
+
I
-
PHASE2
R
+
drp2
L
2
V
OUT
DCR
-
R
PAR
+
+
-
RS
Vdcr
2
1
R
R
L2
O2
VSUM
VSEN
82nF
R
RTN
NTC
C
BULK
C
L2
ISEN2
R
drp1
VO'
VDIFF
VO'
VO'
10
R
0.018µF
ESR
opn1
TO V
OUT
0.018µF
V
CC_SENSE
TO PROCESSOR
SOCKET KELVIN
CONNECTIONS
V
R
SS_SENSE
OPN2
FIGURE 37. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
resistors provide voltage feedback in the event that the system
is powered up without a processor installed. These resistors
typically range from 20 to 100.
Static Mode of Operation - Processor Die Sensing
Die sensing is the ability of the controller to regulate the core
output voltage at a remotely sensed point. This allows the
voltage regulator to compensate for various resistive drops in
the power path and ensure that the voltage seen at the CPU
die is the correct level independent of load current.
Setting the Switching Frequency - FSET
3
The R modulator scheme is not a fixed frequency PWM
architecture. The switching frequency can increase during the
application of a load to improve transient performance.
The VSEN and RTN pins of the ISL6266A are connected to
Kelvin sense leads at the die of the processor through the
processor socket. These signal names are V
and
It also varies slightly due to changes in input and output
voltage and output current, but this variation is normally less
than 10% in continuous conduction mode.
CC_SENSE
respectively. This allows the voltage regulator to
V
SS_SENSE
tightly control the processor voltage at the die, independent of
layout inconsistencies and voltage drops. This Kelvin sense
technique provides for extremely tight load line regulation.
See Figure 32. The resistor connected between the VW and
COMP pins of the ISL6266A adjusts the switching window, and
These traces should be treated as noise sensitive traces. For
optimum load line regulation performance, the traces
therefore adjusts the switching frequency. The R
resistor
FSET
that sets up the switching frequency of the converter operating
connecting these two pins to the Kelvin sense leads of the
processor must be laid out away from rapidly rising/falling
voltage nodes (switching nodes) and other noisy traces. To
achieve optimum performance, place common mode and
differential mode RC filters to analog ground on VSEN and
RTN as shown in Figure 37. The filter resistors should be 10
so that they do not interact with the 50k input resistance of
the differential amplifier. The filter resistor may be inserted
in CCM can be determined using Equation 7, where R
in k and the switching frequency is in kHz.
is
FSET
–1.1202
F
kHz
SW
----------------------------
(EQ. 7)
R
k =
FSET
2232
Equation 7 is only a rough estimate of actual frequency. It
should be used to choose an R value in the vicinity of the
FSET
desired switching frequency. Empirical fine tuning may be
necessary to achieve the actual frequency target. In addition,
droop amplifier gain may slightly affect the switching frequency.
Equation 7 is derived using the droop gain seen on the
ISL6266AEVAL1Z REV A evaluation board.
between V
and the VSEN pin. Another option is to
CC_SENSE
place to the filter resistor between Vcc_sense and VSEN pin
and between V and RTN pin. The need for RC filters
SS_SENSE
really depends on the actual board layout and noise
environment.
Intersil recommends the use of the R
and R
OPN2
OPN1
and ground as shown in Figure 37. These
connected to V
OUT
FN6398 Rev 4.00
August 25, 2015
Page 23 of 31
ISL6266, ISL6266A
For 300kHz operation, R
is suggested to be 9.53kIn
system temperature rise. T represents the lower temperature
2
FSET
discontinuous conduction mode (DCM), the ISL6266A runs in
period stretching mode. The switching frequency is dependent
on the load current level. In general, lighter loads will produce
lower switching frequencies. Therefore, switching loss is
greatly reduced for light load operation, which conserves
battery power in portable applications.
point at which the VR_TT# goes high from low because the
system temperature decreases to acceptable levels.
VR_TT#
LOGIC_1
Voltage Regulator Thermal Throttling
lntel® IMVP-6+ technology supports thermal throttling of the
processor to prevent catastrophic thermal damage to the
voltage regulator. The ISL6266A features a thermal monitor
that senses the voltage change across an externally placed
negative temperature coefficient (NTC) thermistor.
LOGIC_0
T
T
T (°C)
1
2
FIGURE 39. TEMPERATURE HYSTERESIS OF VR_TT#
Proper selection and placement of the NTC thermistor allows
for detection of a designated temperature rise by the system.
Usually, the NTC thermistor's resistance can be approximated
by Equation 8.
Figure 38 shows the thermal throttling feature with hysteresis.
At low temperature, SW1 is on and SW2 connects to the 1.2V
side. The total current going into NTC pin is 60µA. The voltage
on the NTC pin is higher than the threshold voltage of 1.2V and
the comparator output is low. VR_TT# is pulled high by the
external resistor.
1
1
------------------- -----------------------
b
–
T + 273 To + 273
(EQ. 8)
R
T = R
e
NTCTo
NTC
T is the temperature of the NTC thermistor and b is a
parameter constant depending on the thermistor material. T is
the reference temperature in which the approximation is
o
derived. The most common temperature for T is +25°C. For
o
example, there are commercial NTC thermistor products with b
54µA
6µA
= 2750k, b = 2600k, b = 4500k or b = 4250k.
From the operation principle of the VR_TT# circuit explained,
the NTC resistor satisfies Equations 9 through 13:
1.2V
VR_TT#
SW1
NTC
--------------
(EQ. 9)
R
T + R
=
= 20k
-
NTC
1
S
60A
+
NTC
+
V
R
NTC
1.24V
54A
-
---------------
R
T + R
=
= 22.96k
(EQ. 10)
NTC
2
S
SW2
1.24V
R
s
From Equation 9 and Equation 10, Equation 11 can be derived:
1.20V
INTERNAL TO
ISL6266
(EQ. 11)
R
T – R
T = 2.96k
NTC 1
NTC
2
Using Equation 8 into Equation 11, the required nominal NTC
resistor value can be obtained by Equation 12:
FIGURE 38. CIRCUITRY ASSOCIATED WITH THE THERMAL
THROTTLING FEATURE IN ISL6266
1
-----------------------
o
b
T
+ 273
2.96k e
-----------------------------------------------------------------------------
(EQ. 12)
R
=
When the temperature increases, the NTC resistor value
decreases, thus reducing the voltage on the NTC pin. When
the voltage decreases to a level lower than 1.2V, the
NTCTo
1
1
-----------------------
2
-----------------------
1
b
b
T
+ 273
T + 273
e
–e
comparator output changes polarity and turns SW1 off and
connects SW2 to 1.24V. This pulls VR_TT# low and sends the
signal to start thermal throttle. There is a 6µA current reduction
on the NTC pin and 20mV voltage increase on the threshold
voltage of the comparator in this state. The VR_TT# signal will
be used to change the CPU operation and decrease the power
consumption. Temperature will decrease over time and the
NTC thermistor voltage will go up. When the NTC pin voltage
achieves 1.24V, the comparator output will resume its original
state. This temperature hysteresis feature of VR_TT# is
For those cases where the constant b is not accurate enough
to approximate the resistor value, the manufacturer provides
the resistor ratio information at different temperatures. The
nominal NTC resistor value may be expressed in another way
shown in Equation 13.
2.96k
-----------------------------------------------------------------------
=
(EQ. 13)
R
NTCTo
R
–
T
NTC
R
T
NTC
1
2
illustrated in Figure 39. T represents the higher temperature
1
point at which the VR_TT# goes from low to high due to the
FN6398 Rev 4.00
August 25, 2015
Page 24 of 31
ISL6266, ISL6266A
where R
is the normalized NTC resistance to its nominal
The closest standard resistor to this result is 4.42kThe NTC
resistance at T is given by Equation 18.
NTCT
value. Most data sheets of the NTC thermistor give the
normalized resistor value based on its value at +25°C.
2
(EQ. 18)
R
= 2.96k + R
= 18.16k
NTC_T1
NTC_T2
Once the NTC thermistor resistor is determined, the series
resistor can be derived by Equation 14:
Therefore, the NTC branch is designed to have a 470k NTC
and 4.42k resistor in series. The part number of the NTC
thermistor is ERTJ0EV474J in an 0402 package. The NTC
thermistor should be placed in the spot that provides the best
indication of the voltage regulator circuit temperature.
1.2V
60A
--------------
R
=
– R
T1 = 20k – R
NTC NTC_T
(EQ. 14)
S
1
Once R
NTCTo
and R is designed, the actual NTC resistance at
s
T and the actual T temperature can be found in Equations 15
2
2
Static Mode of Operation - Static Droop Using DCR
Sensing
and 16:
R
= 2.96k + R
(EQ. 15)
(EQ. 16)
NTC_T
NTC_T
1
2
1
As previously mentioned, the ISL6266A has a differential
amplifier that provides precision voltage monitoring at the
processor die for both single-phase and two-phase operation.
This enables the ISL6266A to achieve an accurate load line in
accordance with the IMVP-6+ specification.
-----------------------------------------------------------------------------------
T
=
– 273
2_actual
R
NTC_T
-------------------------
NTCTo
1
b
2
--
ln
+ 1 273 + To
R
For example, if using Equations 12, 13 and 14 to design a
thermal throttling circuit with the temperature hysteresis
DESIGN EXAMPLE
The process of compensation for DCR resistance variation to
achieve the desired load line droop has several steps and may
be iterative.
+100°C to +105°C, since T = +105°C and T = +100°C, and if
1
2
we use a Panasonic NTC with b = 4700, Equation 12 gives the
required NTC nominal resistance as R = 459k.
NTC_To
A two-phase solution using DCR sensing is shown in Figure 37.
There are two resistors connecting to the terminals of inductor of
each phase. These are labeled RS and RO. These resistors are
used to obtain the DC voltage drop across each inductor. The DC
current flowing through each inductor will create a DC voltage
drop across the real winding resistance (DCR). This voltage is
proportional to the average inductor current by Ohm’s Law. When
this voltage is summed with the other channel’s DC voltage, the
total DC load current can be derived.
In fact, the data sheet gives the resistor ratio value at +100°C
to +105°C, which is 0.03956 and 0.03322 respectively. The b
value 4700k in the Panasonic data sheet only covers to
+85°C. Therefore, using Equation 13 is more accurate for
+100°C design, the required NTC nominal resistance at +25°C
is 467k. The closest NTC resistor value from the
manufacturer is 467k. The series resistance is given by
Equation 17 as follows:
R
= 20k – R
= 20k – 15.65k = 4.35k
S
NTC_105C
R
is typically 1 to 10. This resistor is used to tie the
O
(EQ. 17)
outputs of all channels together and thus create a summed
average of the local CORE voltage output. R is determined
S
10µA
OCSET
-
OC
RS
2
+
--------
=
RS
EQV
VSUM
+
VSUM
DROOP
DFB
INTERNAL TO
ISL6266
-
+
-
DCR
2
-------------
Vdcr
= I
OUT
DROOP
+
EQV
+
VN
-
1
-
+
+
Cn
+
-
1
R
+ R
R
series par
ntc
--------------------------------------------------------------
Rn =
R
+ R
+ R
series par
ntc
VO'
VDIFF
RTN VSEN
VO'
RO
--------
=
RO
EQV
2
FIGURE 40. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING
FN6398 Rev 4.00
August 25, 2015
Page 25 of 31
ISL6266, ISL6266A
through an understanding of both the DC and transient load
currents. This value will be covered in the next section.
However, it is important to keep in mind that the outputs of
The non-inverting droop amplifier circuit has the gain
K
expressed as Equation 25:
droopamp
R
drp2
(EQ. 25)
---------------
k
= 1 +
droopamp
each of these R resistors are tied together to create the
R
S
drp1
VSUM voltage node. With both the outputs of R and R tied
O
S
G
is the desired gain of Vn over I
•DCR/2.
OUT
together, the simplified model for the droop circuit can be
derived. This is presented in Figure 40.
1target
Therefore, the temperature characteristics of gain of Vn is
described by Equation 26.
Figure 40 shows the simplified model of the droop circuitry.
Essentially, one resistor can replace the R resistors of each
phase and one R resistor can replace the R resistors of
G
1target
------------------------------------------------------
G T =
(EQ. 26)
O
1
1 + 0.00393*(T-25)
S
S
each phase. The total DCR drop due to load current can be
replaced by a DC source, the value of which is given by
Equation 19:
For the G
= 0.76:
1target
R
R
R
= 10k with b = 4300,
ntc
= 2610, and
series
= 11k
I
DCR
par
OUT
(EQ. 19)
--------------------------------
=
V
DCR_EQU
2
RS
EQV
= 1825 generates a desired G1, close to the feature
specified in Equation 26.
For the convenience of analysis, the NTC network comprised
of R , R and R , given in Figure 37, is labeled as a
ntc series par
The actual G1 at +25°C is 0.769. A design file is available to
generate the proper values of R , R
single resistor R in Figure 40.
N
, R , and RS
ntc series par
EQV
for values of the NTC thermistor and G1 that differ from the
example provided here.
The first step in droop load line compensation is to adjust R ,
N
RO
and RS
such that sufficient droop voltage exists
EQV
EQV
even at light loads between the VSUM and VO' nodes. As a
rule of thumb, we start with the voltage drop across the R
The individual resistors from each phase to the VSUM node,
N
labeled R and R in Figure 37, are then given by
S1
S2
network, Vn, to be 0.5x to 0.8x V
. This ratio provides
DCR_EQU
Equation 27.
for a fairly reasonable amount of light load signal from which to
arrive at droop.
(EQ. 27)
Rs = 2 RS
EQV
The resultant NTC network resistor value is dependent on the
temperature and given by Equation 20.
So, R = 3650. Once we know the attenuation of the R and
S
S
R
network, we can then determine the droop amplifier gain
N
required to achieve the load line. Setting R
= 1k_1%, then
R
+ R R
ntc par
drp1
series
(EQ. 20)
--------------------------------------------------------------
R T =
n
R
can be found using Equation 28.
R
+ R
+ R
ntc par
drp2
series
2 R
droop
-----------------------------------------------
(EQ. 28)
R
=
– 1 R
drp2
drp1
DCR G125C
For simplicity, the gain of Vn to the V
DCR_EQU
is defined by
G1, also dependent on the temperature of the NTC thermistor.
Droop Impedance (R
) = 0.0021 (V/A) as per the Intel
droop
=
R T
n
IMVP-6+ specification. Using DCR = 0.0008 typical for a
0.36µH inductor, R = 1k and the attenuation gain
-------------------------------------------
G T
(EQ. 21)
(EQ. 22)
1
R T + RS
n
EQV
drp1
is then given by Equation 29:
(G1) = 0.77, R
drp2
DCRT = DCR
1 + 0.00393*(T-25)
25C
2 R
droop
--------------------------------------
(EQ. 29)
R
=
– 1 1k 5.82k
drp2
0.0008 0.769
Therefore, the output of the droop amplifier divided by the total
load current can be expressed as shown in Equation 23, where
Note, we choose to ignore the R resistors because they do
O
not add significant error.
R
is the realized load line slope and 0.00393 is the
droop
temperature coefficient of the copper.
These designed values in R network are very sensitive to the
n
DCR
25
layout and coupling factor of the NTC to the inductor. As only
one NTC is required in this application, this NTC should be
placed as close to the Channel 1 inductor as possible and PCB
traces sensing the inductor voltage should route directly to the
inductor pads.
-------------------
1 + 0.00393*(T-25) k
droopamp
R
= G T
droop
1
2
(EQ. 23)
How to achieve the droop value independent of the inductor
temperature is expressed by Equation 24.
G T 1 + 0.00393*(T-25) G
(EQ. 24)
Due to layout parasitics, small adjustments may be necessary
to accurately achieve the full load droop voltage. This can be
easily accomplished by allowing the system to achieve thermal
1
1target
equilibrium at full load, and then adjusting R
appropriate load line slope.
to obtain the
drp2
FN6398 Rev 4.00
August 25, 2015
Page 26 of 31
ISL6266, ISL6266A
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the output
voltage will deviate from the initial voltage reading. A good
compensation can limit the drift to 2mV. If the output voltage is
decreasing with temperature increase, the ratio between the
NTC thermistor value and the rest of the resistor divider
network has to be increased. The user is strongly encouraged
to use the evaluation board values and layout to minimize
engineering time.
period of time to settle to its final value, which could be
problematic if a load dump were to occur during this time. This
situation would cause the output voltage to rise above the no
load setpoint of the converter and could potentially damage the
CPU.
The L/DCR time constant of the inductor must be matched to
the R *C time constant as shown in Equation 31.
n
n
R
RS
EQV
L
n
-------------
----------------------------------
=
C
n
(EQ. 31)
(EQ. 32)
DCR
R + RS
n EQV
The 2.1mV/A load line should be adjusted by R
drp2
based on
Solving for C we now have Equation 32.
n
maximum current. The droop gain might vary slightly between
small steps (e.g. 10A). For example, if the max current is 40A
and the load line 2.1mthe user load the converter to 40A
and look for 84mV of droop. If the droop voltage is less than
84mV (e.g. 80mV) the new value will be calculated by Equation
30:
L
-------------
DCR
----------------------------------
=
C
n
R
RS
n
EQV
----------------------------------
+ RS
R
n
EQV
Note, R was neglected. As long as the inductor time constant
O
84mV
80mV
matches the C , R and R time constants as given previously,
(EQ. 30)
n
n
s
---------------
R
=
R
+ R
– R
drp2 drp1
drp2 new
drp1
-
the transient performance will be optimum. As in the static
droop case, this process may require a slight adjustment to
correct for layout inconsistencies. For the example of
For the best accuracy, the effective resistance on the DFB and
VSUM pins should be identical so that the bias current of the
droop amplifier does not cause an offset voltage. In the
L = 0.36µH with 0.8m DCR, C is calculated in Equation 33.
n
0.36H
-------------------
previous example, the resistance on the DFB pin is R
in
drp1
0.0008
---------------------------------------------------------------------
C
=
330nF
(EQ. 33)
n
parallel with R
, that is, 1k in parallel with 5.82k or 853.
parallel5.823K, 1.825K
drp2
The resistance on the VSUM pin is R in parallel with RS
n
EQV
The value of this capacitor is selected to be 330nF. As the
inductors tend to have 20% to 30% tolerances, this capacitor
generally will be tuned on the board by examining the transient
voltage. If the output voltage transient has an initial dip lower
than the voltage required by the load line and slowly increases
back to steady state, the capacitor is too small and vice versa.
It is better to have the capacitor value a little bigger to cover the
tolerance of the inductor to prevent the output voltage from
going lower than the spec. This capacitor needs to be a high
grade capacitor like X7R with low tolerance. There is another
consideration in order to achieve better time constant match
mentioned previously. The NPO/COG (class-I) capacitors have
only 5% tolerance and very good thermal characteristics.
However, these capacitors are only available in small
or 5.87k in parallel with 1.825k, which equals 1392. The
mismatch in the effective resistances is 1404 - 53 = 551. The
mismatch cannot be larger than 600. To reduce the
mismatch, multiply both R
and R
by the appropriate
drp1
drp2
factor. The appropriate factor in this example is
1404/853 = 1.65. In summary, the predicted load line with the
designed droop network parameters based on the Intersil
design tool is shown in Figure 41.
2.25
2.20
2.15
2.10
2.05
capacitance values. In order to use such capacitors, the
resistors and thermistors surrounding the droop voltage
sensing and droop amplifier has to be resized up to 10x larger
to reduce the capacitance by 10x. Careful attention must be
paid in balancing the impedance of droop amplifier in this case.
0
20
40
60
80
100
INDUCTOR TEMPERATURE (°C)
Dynamic Mode of Operation - Compensation
Parameters
FIGURE 41. LOAD LINE PERFORMANCE WITH NTC
THERMAL COMPENSATION
Considering the voltage regulator as a black box with a voltage
source controlled by VID and a series impedance, in order to
achieve the 2.1mV/A load line, the impedance needs to be
2.1m. The compensation design has to target the output
impedance of the converter to be 2.1m. There is a
mathematical calculation file available to the user. The power
stage parameters such as L and Cs are needed as the input to
calculate the compensation component values. Attention must
Dynamic Mode of Operation - Dynamic Droop Using
DCR Sensing
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage could
sag excessively upon load application and potentially create a
system failure. The output voltage could also take a long
FN6398 Rev 4.00
August 25, 2015
Page 27 of 31
ISL6266, ISL6266A
be paid to the input resistor to the FB pin. Too high of a resistor
will cause an error to the output voltage regulation because of
bias current flowing in the FB pin. It is better to keep this
resistor below 3k when using this file.
Droop Using Discrete Resistor Sensing -
Static/Dynamic Mode of Operation
Figure 42 shows the equivalent circuit of a discrete current
sense approach. Figure 33 shows a more detailed schematic
of this approach. Droop is solved the same way as the DCR
sensing approach with a few slight modifications.
Static Mode of Operation - Current Balance Using
DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL6266A by measuring the
voltages present on the ISEN pins and adjusting the duty cycle
First, because there is no NTC required for thermal
compensation, the R resistor network in the previous section
n
of each phase until they match. R and C around each
is not required. Second, because there is no time constant
L
L
inductor, or around each discrete current resistor, are used to
create a rather large time constant such that the ISEN voltages
have minimal ripple voltage and represent the DC current
flowing through each channel's inductor. For optimum
matching required, the C component is not matched to the
n
L/DCR time constant. This component does indeed provide
noise immunity and therefore is populated with a 39pF
capacitor.
performance, R is chosen to be 10k and C is selected to be
0.22µF. When discrete resistor sensing is used, a capacitor
L
L
The R values in the previous section, R = 1.5k_1%, are
sufficient for this approach.
S
S
most likely needs to be placed in parallel with R to properly
L
compensate the current balance circuit.
Now the input to the droop amplifier is essentially the V
voltage. This voltage is given by Equation 34.
rsense
ISL6266A uses an RC filter to sense the average voltage on
phase node and forces the average voltage on the phase node
to be equal for current balance. Even though the ISL6266A
forces the ISEN voltages to be almost equal, the inductor
currents will not be exactly equal. Using DCR current sensing
as an example, two errors have to be added to find the total
current imbalance.
R
sense
2
-------------------
Vrsense
=
I
(EQ. 34)
EQV
OUT
The gain of the droop amplifier, K
for the ratio of the R
Equation 35.
, must be adjusted
droopamp
to droop impedance, R
by using
droop
sense
R
droop
--------------------------------
K
=
(EQ. 35)
1. Mismatch of DCR: If the DCR has a 5% tolerance, the
resistors could mismatch by 10% worst case. If each phase
is carrying 20A, the phase currents mismatch by 20A*10%
= 2A.
droopamp
R
2
sense
Solving for the R
drp2
value, R = 0.0021(V/A) as per the Intel
droop
IMVP-6+ specification, R
Equation 36 is obtained:
= 0.001 and R
– 1 R = 3.2k
drp1
= 1k,
2. Mismatch of phase voltages/offset voltage of ISEN pins:
The phase voltages are within 2mV of each other by the
current balance circuit. The error current that results is
given by 2mV/DCR. If DCR = 1m then the error is 2A.
sense
drp1
R
= K
(EQ. 36)
drp2
droopamp
In the previous example, the two errors add to 4A. For the two
phase DC/DC, the currents would be 22A in one phase and
18A in the other phase. In the previous analysis, the current
balance can be calculated with 2A/20A = 10%. This is the
worst case calculation. For example, the actual tolerance of
two 10% DCRs is 10%*(2) = 7%.
Because these values are extremely sensitive to layout, some
tweaking may be required to adjust the full load droop. This is
fairly easy and can be accomplished by allowing the system to
achieve thermal equilibrium at full load, and then adjusting
R
to obtain the desired droop value.
drp2
Fault Protection - Overcurrent Fault Setting
There are provisions to correct the current imbalance due to
layout or to purposely divert current to certain phase for better
thermal management. The Customer can put a resistor in
parallel with the current sensing capacitor on the phase of
interest in order to purposely increase the current in that
phase.
As previously described, the overcurrent protection of the
ISL6266A is related to the droop voltage. Previously the droop
voltage was calculated as I
*R
, where R is the
Load droop
droop
load line slope specified as 0.0021 (V/A) in the Intel IMVP-6+
specification. Knowing this relationship, the overcurrent
protection threshold can be programmed as an equivalent
droop voltage droop. Knowing the voltage droop level allows
If the PC board trace resistance from the inductor to the
microprocessor are significantly different between two phases,
the current will not be balanced perfectly. Intersil has a
proprietary method to achieve the perfect current sharing in
cases of severely imbalanced layouts.
the user to program the appropriate drop across the R
OC
resistor. This voltage drop will be referred to as V . Once the
OC
droop voltage is greater than V , the PWM drives will turn off
OC
and PGOOD will go low.
When choosing the current sense resistor, both the tolerance
of the resistance and the TCR are important. Also, the current
sense resistor’s combined tolerance at a wide temperature
range should be calculated.
The selection of R
OC
overcurrent trip level, I , of 55A, and knowing from the Intel
OC
is given in Equation 37. Assuming an
FN6398 Rev 4.00
August 25, 2015
Page 28 of 31
ISL6266, ISL6266A
10µA
OCSET
+Voc -Roc
VSUM
-
OC
RS
2
+
--------
RS
=
EQV
VSUM
DFB
+
DROOP
INTERNAL TO
ISL6266A
-
+
-
DROOP
Rsense
-----------------------
+
-
Vrsense
= I
OUT
+
-
EQV
1
1
2
+
+
VN
Cn
+
-
VO'
RO
2
VDIFF
RTN VSEN
--------
RO
=
EQV
VO'
FIGURE 42. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DISCRETE RESISTOR SENSING
specification of the load line slope, R
is calculated by Equation 37.
= 0.0021 (V/A), R
Note, if the droop load line slope is not -0.0021 (V/A) in the
application, the overcurrent setpoint will differ from predicted.
In addition, due to the saturation limitations of the DROOP
amplifier, there is a maximum way-overcurrent (WOC) set point
for each VID code. The maximum OC set point that will ensure
WOC can be reached is expressed in Equation 38:
droop
OC
I
R
droop
55 0.0021
------------------------------
–6
OC
----------------------------------
R
=
=
= 11.5k
(EQ. 37)
OC
10A
10 10
1.75 – VID
-------------------------------------
I
=
(EQ. 38)
OC
2.5 R
DROOP
The WOC limitation is only problematic at very high VID
settings (~1.350V and above).
FN6398 Rev 4.00
August 25, 2015
Page 29 of 31
ISL6266, ISL6266A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
August 25, 2015
FN6398.4
Updated Ordering Information table on page 1.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing L48.7X7 to the latest revision.
-Revision 4 to Revision 5 changes - Corrected Note 4 from: "Dimension b applies to.." to: "Dimension
applies to.." and enclosed Notes #'s 4, 5 and 6 in a triangle.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2006-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6398 Rev 4.00
August 25, 2015
Page 30 of 31
ISL6266, ISL6266A
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 4/10
4X
5.5
7.00
A
44X
6
0.50
B
PIN #1 INDEX AREA
37
48
6
1
36
PIN 1
INDEX AREA
4. 30 ± 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40± 0 . 1
TOP VIEW
4
0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
C
C
0.10
0 . 90 ± 0 . 1
BASE PLANE
( 6 . 80 TYP )
4 . 30 )
SEATING PLANE
0.08 C
(
SIDE VIEW
( 44X 0 . 5 )
0 . 2 REF
5
C
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6398 Rev 4.00
August 25, 2015
Page 31 of 31
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