ISL6267EVAL1Z_技术文档

Multiphase PWM Regulator for AMD Fusion™ Mobile

CPUs

ISL6267

Features

The ISL6267 is designed to be completely compliant with AMD

Fusion™ specifications. The ISL6267 controls two Voltage

Regulators (VRs) with three integrated gate drivers. The first VR

can be configured as 3-, 2-, or 1-phase VR, while the second

output can be configured as 2- or 1-phase VR, providing

maximum flexibility. The two VRs share the serial control bus to

communicate with the CPU and achieve lower cost and smaller

board area compared with two-chip solutions.

• Supports AMD SVI 1.0 Serial Data Bus Interface

• Dual Output Controller with Integrated Drivers

- Core VR Configurable 3-, 2-, 1-Phase with Two Integrated

Drivers

- Northbridge VR Configurable 2- or 1-Phase with One

Integrated Driver

• Precision Voltage Regulation

- 0.5% System Accuracy Over-Temperature

- 0V to 1.55V in 12.5mV Steps

The PWM modulator of ISL6267 is based on Intersil’s R3 (Robust

Ripple Regulator) Technology™. Compared with the traditional

multi-phase buck regulator, the R3 modulator commands

variable switching frequency during load transients, achieving

faster transient response. With the same modulator, it naturally

goes into pulse frequency modulation in light load conditions,

which achieves higher light load efficiency and extends battery

life.

- Enhanced Load Line Accuracy

• Supports Multiple Current Sensing Methods

- Lossless Inductor DCR Current Sensing

- Precision Resistor Current Sensing

• Programmable 1-, 2- or 3-Phase for the Core Output and 1-

or 2-Phase for the Northbridge Output

The ISL6267 has several other key features. Both outputs

support DCR current sensing with a single NTC thermistor for

DCR temperature compensation or accurate resistor current

sensing. Both outputs come with remote voltage sense,

adjustable switching frequency, current monitor, OC

protection, independent power-good indicators, temperature

monitors, and a common thermal alert.

• Adaptive Body Diode Conduction Time Reduction

• Superior Noise Immunity and Transient Response

• Output Current Monitor and Thermal Monitor

• Differential Remote Voltage Sensing

• High Efficiency Across Entire Load Range

• Programmable +VID Offset for Both Core and NB

• Programmable Switching Frequency for Both Outputs

• Excellent Dynamic Current Balance Between Phases

• OCP/WOC, OVP, PGOOD, and Thermal Monitor

• Small Footprint 48 Ld 6x6 TQFN Package

• Pb-Free (RoHS Compliant)

Applications

• AMD Fusion CPU/GPU Core Power

• Notebook Computers

Core Performance on ISL6267EVAL1Z

100

90

1.12

1.10

1.08

1.06

80

V

= 8V

IN

70

60

50

40

30

20

10

0

V

= 12V

IN

V

= 8V

IN

V

= 19V

IN

1.04

1.02

1.00

0.98

0.96

V

= 12V

IN

V

= 19V

IN

V

CORE = 1.1V

OUT

V

CORE = 1.1V

OUT

5

0

5

10 15 20 25 30 35 40 45 50 55

(A)

0

10 15 20 25 30 35 40 45 50 55

I

OUT

I

(A)

OUT

FIGURE 2. V

vs LOAD

FIGURE 1. EFFICIENCY vs LOAD

OUT

FN7801.0

January 31, 2011

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL6267

Simplified Application Circuit For High Power CPU Core

VIN

BOOT_NB

UG1_NB

VNB

ISEN1_NB

PH1_NB

ISEN2_NB

LG1_NB

NB_PH1

VNB1

VNB2

ISUMN_NB

ISUMP_NB

VW_NB

PWM2_NB

NTC_NB

NB_PH2

VNB2

COMP_NB

FB_NB

FB2_NB

PROG1

PROG2

VSEN_NB

RTN_NB

Thermal Indicator

VR_HOT

NTC

VNB_SENSE

ISL6267

VIN

PWROK

SVD

µP

SVC

PWM3

VW

VO3

PH3

COMP

VIN

BOOT2

FB

UG2

PH2

VSEN

VCORE

VCORE_SENSE

RTN

LG2

PH2

VO2

VIN

ISEN3

ISEN2

BOOT1

UG1

ISEN1

ISUMN

VO1

VO2

VO3

PH1

LG1

PH1

VO1

ISUMP

FIGURE 3. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING

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2

ISL6267

Simplified Application Circuit For AMD Torpedo Platform

NTC_NB

ISEN1_NB

VIN

BOOT_NB

UG1_NB

ISEN2_NB

ISUMN_NB

VNB1

VNB2

VNB

PH1_NB

LG1_NB

ISUMP_NB

NB_PH1

VIN

VNB1

VW_NB

COMP_NB

PWM2_NB

FB_NB

NB_PH2

VNB2

FB2_NB

VSEN_NB

RTN_NB

NTC

VNB_SENSE

Thermal Indicator

VR_HOT

ISL6267

PROG1

PROG2

PWROK

SVD

µP

SVC

PWM3

+5V

VW

VIN

BOOT2

COMP

UG2

PH2

VCORE

FB

ISEN3/FB2

LG2

PH2

VO2

VSEN

RTN

VCORE_SENSE

VIN

BOOT1

UG1

PH1

LG1

ISEN2

ISEN1

PH1

VO1

ISUMN

ISUMP

VO2

FIGURE 4. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING

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FN7801.0

3

ISL6267

Simplified Application Circuit For Low Power CPU Core And NB

+5V

ISEN2_NB

OPEN

ISEN1_NB

ISUMN_NB

VIN

BOOT_NB

UG1_NB

VNB1

VNB

PH1_NB

LG1_NB

ISUMP_NB

NB_PH1

VNB1

NTC_NB

VW_NB

optional

OPEN

PWM2_NB

COMP_NB

FB_NB

PROG1

PROG2

VSEN_NB

RTN_NB

VNB_SENSE

NTC

Thermal Indicator

VR_HOT

PWROK

SVD

µP

ISL6267

SVC

PWM3

+5V

BOOT2

OPEN

ISEN1

ISEN2

UG2

PH2

OPEN

+5V

ISEN3

VW

LG2

OPEN

optional

PGND2

BOOT1

UG1

COMP

VIN

FB

VCORE

VSEN

PH1

LG1

VCORE_SENSE

VO1

RTN

PH1

VO1

ISUMN

ISUMP

FIGURE 5. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING

January 31, 2011

FN7801.0

4

ISL6267

Simplified Application Circuit Showing Resistor Sensing

+5V

ISEN2_NB

OPEN

ISEN1_NB

ISUMN_NB

VIN

BOOT_NB

UG1_NB

NB_N

VNB

PH1_NB

LG1_NB

ISUMP_NB

NB_N

NB_P

NTC_NB

VW_NB

optional

OPEN

PWM2_NB

COMP_NB

FB_NB

PROG1

PROG2

VSEN_NB

RTN_NB

VNB_SENSE

NTC

Thermal Indicator

VR_HOT

PWROK

SVD

µP

ISL6267

SVC

PWM3

+5V

BOOT2

OPEN

ISEN1

ISEN2

UG2

PH2

OPEN

+5V

ISEN3

VW

OPEN

LG2

optional

PGND2

BOOT1

UG1

COMP

VIN

FB

VCORE

VSEN

PH1

LG1

VCORE_SENSE

VON

RTN

VON

VOP

ISUMN

ISUMP

FIGURE 6. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING

January 31, 2011

FN7801.0

5

ISL6267

Block Diagram

SVD

SERIAL

PROG1

PROG2

VCORE

VNB

SVC

VID

A/D

INTERFACE

BOOT_NB

UG_NB

PWROK

NORTHBRIDGE

CONTROLLER AND DRIVER

DAC1

DAC2

(SIMILAR ARCHITECTURE TO

CORE SECTION)

PH_NB

SLEEP

MODE

(PSI_L)

LG_NB

D/A

PWM2_NB

VDD

ISEN1

PHASE

IBAL

PROG1

PROG2

OFFSET

VOLTAGE

CURRENT

ISEN2

BALANCE

ISEN3/FB2

PWM3

NTC_NB

NTC

T_MONITOR

BOOT2

UG2

TEMP

MONITOR

DRIVER

VR_HOT

PH2

VW

DAC1

DRIVER

+

LG2

RTN

S

+

MODULATOR

BOOT1

UG1

E/A

FB

-

PH1

COMP

VCCP

LG1

DRIVER

+

ISUMP

ISUMN

OC AND WOC

CURRENT

SENSE

PROTECTION

-

PGOOD

OV

PROTECTION

VSEN

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FN7801.0

6

ISL6267

Pin Configuration

ISL6267

(48 LD QFN)

TOP VIEW

43

48 47 46 45 44

42 41 40 39 38 37

PWM2_NB

BOOT2

UG2

1

36

35

34

33

32

31

30

29

28

27

26

25

FB2_NB

FB_NB

COMP_NB

VW_NB

2

3

4

5

6

7

8

9

PH2

LG2

PGOOD_NB

SVD

GND PAD

(BOTTOM)

VCCP

PWM3

LG1

PWROK

SVC

PH1

ENABLE

PGOOD 10

UG1

BOOT1

PROG1

11

12

VR_HOT

NTC

3 7

Pin Descriptions

PIN NUMBER

SYMBOL

DESCRIPTION

1

FB2_NB

The components connecting to FB2_NB are used to adjust the compensation in 1-phase mode to achieve

optimum performance.

2

3

4

FB_NB

COMP_NB

VW_NB

Output voltage feedback to the inverting input of the Northbridge controller error amplifier.

Northbridge VR error amplifier output.

Window voltage set pin used to set the switching frequency for the Northbridge controller. A resistor from

this pin to COMP_NB programs the switching frequency (8kΩ gives approximately 300kHz).

5

PGOOD_NB

Open-drain output to indicate the Northbridge portion of the IC is ready to supply regulated voltage. Pull-

up externally to VCCP or 3.3V.

6

7

SVD

Serial VID data bi-directional signal from the CPU processor master device to the VR.

2

PWROK

System power good input. When this pin is high, the SVI interface is active and the I C protocol is running.

While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This pin must

be low prior to the ISL6267 PGOOD output going high per the AMD SVI Controller Guidelines.

8

9

SVC

Serial VID clock input from the CPU processor master device.

Enable input. A high level logic on this pin enables both VRs.

ENABLE

PGOOD

10

Open-drain output to indicate the Core portion of the IC is ready to supply regulated voltage. Pull up

externally to VCCP or 3.3V.

11

12

13

VR_HOT

NTC

Thermal overload open drain output indicator active LOW.

Thermistor input to VR_HOT circuit to monitor Core VR temperature.

VW

Window voltage set pin used to set the switching frequency for the Core controller. A resistor from this

pin to COMP programs the switching frequency (8kΩ gives approximately 300kHz).

14

15

COMP

FB

Error amplifier output.

Output voltage feedback to the inverting input of the Core controller error amplifier.

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FN7801.0

7

ISL6267

Pin Descriptions(Continued)

PIN NUMBER

SYMBOL

DESCRIPTION

16

ISEN3/FB2

When the Core VR of ISL6267 is configured in 3-phase mode, this pin is ISEN3. ISEN3 is the individual

current sensing for Channel 3. When the Core VR of ISL6267 is configured in 2-phase mode, this pin is

FB2. There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode and is off

in 1-phase mode. The components connecting to FB2 are used to adjust the compensation in 1-phase

mode to achieve optimum performance.

17

ISEN2

Individual current sensing for Channel 2 of the Core VR. When ISEN2 is pulled to 5V VDD, the controller

disables Channel 2, and the Core VR runs in single-phase mode.

18

19

20

ISEN1

VSEN

RTN

Individual current sensing for Channel 1 of the Core output.

Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die.

Output voltage sense return pin for the Core controller. Connect to the -sense pin of the microprocessor

die.

21

22

23

24

25

26

ISUMN

ISUMP

VDD

Inverting input of the transconductance amplifier for current monitor and load line of Core output.

Non-inverting input of the transconductance amplifier for current monitor and load line of Core output.

5V bias power.

VIN

Battery supply voltage, used for feed-forward.

PROG1

BOOT1

Program pin for setting output voltage offset for Core VR.

Connect an MLCC capacitor across the BOOT1 and the phase (PH1) pin. The boot capacitor is charged

through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each time the PH1 pin

drops below VCCP minus the voltage dropped across the internal boot diode.

27

28

UG1

PH1

Output of the Phase 1 high-side MOSFET gate driver of the Core VR. Connect the UG1 pin to the gate of

the Phase 1 high-side MOSFET.

Current return path for the Phase 1 high-side MOSFET gate driver of VR1. Connect the PH1 pin to the node

consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of

Phase 1.

29

30

31

32

33

LG1

PWM3

VCCP

LG2

Output of the Phase 1 low-side MOSFET gate driver of the Core VR. Connect the LG1 pin to the gate of the

Phase 1 low-side MOSFET.

PWM output for Channel 3 of the Core VR. When PWM3 is pulled to 5V VDD, the controller disables Phase

3 and runs in 2-phase mode.

Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at least 1µF

of capacitance to GND. A high quality, X7R dielectric MLCC capacitor is recommended.

Output of the Phase 2 low-side MOSFET gate driver of VR1. Connect the LG2 pin to the gate of the

Phase 2 low-side MOSFET.

PH2

Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the PH2 pin to

the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor

of Phase 2.

34

35

UG2

Output of the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the UG2 pin to the gate of

the Phase 2 high-side MOSFET.

BOOT2

Connect an MLCC capacitor across the BOOT2 and PH2 pins. The boot capacitor is charged through an

internal boot diode connected from the VCCP pin to the BOOT2 pin, each time the PH2 pin drops below

VCCP minus the voltage dropped across the internal boot diode.

36

37

PWM2_NB

LG1_NB

PWM output for Channel 2 of the Northbridge VR.

Output of the low-side MOSFET gate driver of the Northbridge VR. Connect the LG1_NB pin to the gate of

the low-side MOSFET of VR2.

38

39

PH1_NB

UG1_NB

Current return path for the high-side MOSFET gate driver of the Northbridge VR. Connect the PH1_NB pin

to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output

inductor of the Northbridge VR.

Output of the high-side MOSFET gate driver of the Northbridge VR. Connect the UG1_NB pin to the gate

of the high-side MOSFET.

January 31, 2011

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8

ISL6267

Pin Descriptions(Continued)

PIN NUMBER

SYMBOL

DESCRIPTION

40

BOOT1_NB

Connect an MLCC capacitor across the BOOT1_NB and the PH1_NB pins. The boot capacitor is charged

through an internal boot diode connected from the VCCP pin to the BOOT1_NB pin, each time the

PH1_NB pin drops below VCCP minus the voltage dropped across the internal boot diode.

41

42

43

44

PROG2

NTC_NB

Program pin for setting output voltage offset for Northbridge VR.

Thermistor input to VR_HOT circuit to monitor Northbridge VR temperature.

Inverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR.

ISUMN_NB

ISUMP_NB

Non-inverting input of the transconductance amplifier for current monitor and load line of the

Northbridge VR.

45

46

47

48

RTN_NB

VSEN_NB

ISEN2_NB

Output voltage sense return pin for the Northbridge controller. Connect to the -sense pin of the

microprocessor die.

Output voltage sense pin for the Northbridge controller. Connect to the +sense pin of the microprocessor

die.

Individual current sensing for Channel 2 of the Northbridge VR. When ISEN2 is pulled to 5V VDD, the

controller will disable Channel 2 and the Northbridge VR will run single-phase.

ISEN1_NB

Individual current sensing for Channel 1 of the Northbridge VR.

GND (Bottom Pad)

Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.

Ordering Information

PART NUMBER

PART

TEMP.

RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

(Notes 1, 2, 3)

MARKING

ISL6267HRZ

ISL6267 HRZ

Evaluation Board

-10 to +100

48 Ld 6x6 QFN

L48.6x6B

ISL6267EVAL1Z

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6267. For more information on MSL please see tech brief TB363.

January 31, 2011

9

FN7801.0

ISL6267

Table of Contents

Core Performance On ISL6267EVAL1Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Simplified Application Circuit For High Power CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Simplified Application Circuit For AMD Torpedo Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Simplified Application Circuit For Low Power CPU Core And NB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Simplified Application Circuit Showing Resistor Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Gate Driver Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Multiphase R3™ Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Start-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Serial VID Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Pre-PWROK Metal VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

VFIX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

SVI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

VID-on-the-Fly Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

SVI WIRE Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

SVI Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

VR Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Voltage Regulation and Load Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Differential Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Dynamic Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

FB2 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Adaptive Body Diode Conduction Time Reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Inductor DCR Current-Sensing Network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Load Line Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

NTC Thermal Monitors and VR_HOT Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

January 31, 2011

10

FN7801.0

ISL6267

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V

Battery Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V

IN

Thermal Resistance (Typical)

48 Ld QFN Package (Notes 4, 5) . . . . . . . .

θ

_JA(°C/W)

28

θ

_JC(°C/W)

DD

1

Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V

Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)

Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)

UGATE Voltage (UGATE) . . . . . . . . . .PHASE - 0.3V (DC) to BOOTPHASE - 5V

. . . . . . . . . . . . . . . . . (<20ns Pulse Width, 10µJ) to BOOT LGATE Voltage

. . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)

Open Drain Outputs, PGOOD, VR_HOT. . . . . . . . . . . . . . . . . . . -0.3V to +7V

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

DD

Battery Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 25V

IN

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Operating Conditions: V = 5V, T = -10°C to +100°C, f = 300kHz, unless otherwise noted.

DD

A

SW

Boldface limits apply over the operating temperature range, -10°C to +100°C.

MIN

MAX

PARAMETER

INPUT POWER SUPPLY

+5V Supply Current

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

9

(Note 6)

UNITS

I

ENABLE = 1V

ENABLE = 0V

ENABLE = 1V

10.5

1

mA

µA

kΩ

VDD

Battery Supply Current

I

1

VIN

V

Input Resistance

R

550

IN

VIN

POWER-ON-RESET THRESHOLDS

VDD POR Threshold

VDD_POR

V

rising

4.35

4.15

4.00

3.30

4.5

V

r

DD

falling

4.00

2.8

f

VIN POR Threshold

VIN_POR

rising

4.35

r

IN

VIN_POR

falling

f

SYSTEM AND REFERENCES

System Accuracy

HRZ %Error

(V

No load; closed loop, active mode range

VID = 0.75V to 1.55V

)

-0.5

-8

+0.5

+8

%

mV

V

CC_CORE

VID = 0.50V to 0.7375V

VID = 0.25V to 0.4875V

VID = [0000000]

-15

+15

Maximum Output Voltage

Minimum Output Voltage

CHANNEL FREQUENCY

Nominal Channel Frequency

Adjustment Range

V

1.55

0.0

CC_CORE(max)

V

VID = [1111111]

V

CC_CORE(min)

f

280

200

300

320

500

kHz

SW(nom)

AMPLIFIERS

Current-Sense Amplifier Input Offset

Error Amp DC Gain

I

= 0A

-0.15

+0.15

mV

dB

FB

A

90

18

v0

GBW

Error Amp Gain-Bandwidth Product

C = 20pF

MHz

L

January 31, 2011

FN7801.0

11

ISL6267

Electrical Specifications Operating Conditions: V = 5V, T = -10°C to +100°C, f = 300kHz, unless otherwise noted.

DD

A

SW

Boldface limits apply over the operating temperature range, -10°C to +100°C. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

(Note 6)

UNITS

ISEN

Imbalance Voltage

Input Bias Current

Maximum of ISENs - Minimum of ISENs

1

mV

nA

20

POWER-GOOD AND PROTECTION MONITORS

PGOOD Low Voltage

V

I

= 4mA

PGOOD

0.26

460

0.4

1

V

OL

PGOOD Leakage Current

PGOOD Delay

I

PGOOD = 3.3V

-1

µA

µs

OH

t

PGD

GATE DRIVER

UGATE Pull-Up Resistance

UGATE Source Current

UGATE Sink Resistance

UGATE Sink Current

R

200mA Source Current

UGATE - PHASE = 2.5V

1.0

2.0

1.0

2.0

1.0

2.0

0.5

4.0

23

1.5

0.9

Ω

A

UGPU

I

UGSRC

R

250mA Sink Current

Ω

A

UGPD

I

UGATE - PHASE = 2.5V

UGSNK

LGATE Pull-Up Resistance

LGATE Source Current

LGATE Sink Resistance

LGATE Sink Current

R

250mA Source Current

LGATE - VSSP = 2.5V

Ω

A

LGPU

I

LGSRC

R

250mA Sink Current

Ω

A

LGPD

I

LGATE - VSSP = 2.5V

LGSNK

UGATE to LGATE Deadtime

LGATE to UGATE Deadtime

BOOTSTRAP DIODE

t

UGATE falling to LGATE rising, no load

LGATE falling to UGATE rising, no load

ns

UGFLGR

LGFUGR

t

28

Forward Voltage

V

PVCC = 5V, I = 2mA

F

0.58

0.2

V

F

Reverse Leakage

I

V

= 25V

R

µA

R

PROTECTION

Overvoltage Threshold

Severe Overvoltage Threshold

Undervoltage Threshold

Current Imbalance Threshold

Core OCP Current Threshold

OV

VSEN rising above setpoint for >1ms

V rising above threshold > 0.5µs

O

200

260

270

1.800

330

9

330

400

mV

V

H

OV

HS

OV

VSEN falls below setpoint for >1ms

One ISEN above another ISEN for >1.2ms

3-Phase CCM, 2-Phase CCM, 1-Phase

3-Phase DE

mV

μA

H

50

16

24

50

24

60

70

24

36

70

36

20

2-Phase DE

30

Northbridge OCP Current Threshold

2-Phase CCM, 1-Phase

2-Phase DE

60

30

LOGIC THRESHOLDS

ENABLE Input Low

V

0.3

1.0

V

IL

ENABLE Input High

PWM

V

0.7

3.5

IH

PWM Output Low

V

Sinking 5mA

Sourcing 5mA

PWM = 2.5V

V

0L

PWM Output High

V

0H

PWM Tri-State Leakage

THERMAL MONITOR

NTC Source Current

NTC_NB Source Current

Thermal Monitor Trip Voltage

Thermal Monitor Reset Voltage

2

µA

NTC = 1.3V

57

67

µA

V

NTC_NB = 1.3V

Falling Threshold

Rising Threshold

0.87

0.91

0.88

0.92

0.89

0.93

V

January 31, 2011

FN7801.0

12

ISL6267

Electrical Specifications Operating Conditions: V = 5V, T = -10°C to +100°C, f = 300kHz, unless otherwise noted.

DD

A

SW

Boldface limits apply over the operating temperature range, -10°C to +100°C. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

(Note 6)

UNITS

INPUTS

ENABLE Leakage Current

I

EN = 0V

EN = 1V

-1

0

18

µA

ENABLE

36

10

µA

Slew Rate (for VID Change)

Soft-Start Slew Rate

SR

5

7.5

mV/µs

SSR

1.25

1.875

2.5

SVI INTERFACE

PWROK, SVC, SVD Input Logic High

PWROK, SVC, SVD Input Logic Low

SVC, SVD Leakage

V

0.798

-

V

IH

V

-

0.57

1

IL

EN = 0V, SVC and SVD = 0V

EN = 5V, SVC and SVD = 1.8V

µA

1

NOTE:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

Gate Driver Timing Diagram

PWM

t

LGFUGR

t

FU

t

RU

1V

UGATE

LGATE

1V

t

RL

t

FL

t

UGFLGR

January 31, 2011

FN7801.0

13

ISL6267

phase. If VR1 is in 1-phase mode, the master clock signal will be

distributed to Phase 1 only and be the Clock1 signal.

Theory of Operation

Multiphase R ™ Modulator

3

VW

The ISL6267 is a multiphase regulator implementing two voltage

regulators, VDD and VDDNB, on one chip controlled by AMD’s™

SVI1™ protocol. VDD can be programmed for 1-, 2- or 3-phase

operation. VDDNB can be configured for 1- or 2-phase operation.

HYSTERETIC

VCRM

WINDOW

COMP

3

Both regulators use the Intersil patented R ™ (Robust Ripple

MASTER

CLOCK

3

Regulator) modulator. The R ™ modulator combines the best

features of fixed frequency PWM and hysteretic PWM while

eliminating many of their shortcomings. Figure 7 conceptually

shows the multiphase R ™ modulator circuit, and Figure 8 shows

CLOCK1

PWM1

3

the operation principles.

MASTER CLOCK CIRCUIT

MASTER

VW

CLOCK2

PWM2

CLOCK

CLOCK1

CLOCK2

CLOCK3

COMP

VCRM

MASTER

CLOCK

PHASE

SEQUENCER

GMVO

CRM

CLOCK3

SLAVE CIRCUIT 1

PWM3

L1

I_L1

PHASE1

CLOCK1

PWM1

VO

S

R

VW

Q

VW

CO

VCRS1

GM

CRS1

VCRS2

VCRS3 VCRS1

SLAVE CIRCUIT 2

L2

I_L2

3

PHASE2

CLOCK2

PWM2

S

FIGURE 8. R ™ MODULATOR OPERATION PRINCIPLES IN

STEADY STATE

VW

Q

R

Each slave circuit has its own ripple capacitor C , whose voltage

rs

VCRS2

GM

mimics the inductor ripple current. A g amplifier converts the

m

CRS2

inductor voltage into a current source to charge and discharge

C . The slave circuit turns on its PWM pulse upon receiving the

SLAVE CIRCUIT 3

rs

L3

I_L3

PHASE3

clock signal, and the current source charges C . When C

CLOCK3

PWM3

S

rs

VW

Q

R

voltage V hits VW, the slave circuit turns off the PWM pulse,

Crs

and the current source discharges C .

rs

VCRS3

GM

Since the controller works with V , which are large amplitude

crs

CRS3

and noise-free synthesized signals, it achieves lower phase jitter

than conventional hysteretic mode and fixed PWM mode

controllers. Unlike conventional hysteretic mode converters, the

error amplifier allows the ISL6267 to maintain a 0.5% output

voltage accuracy.

3

FIGURE 7. R ™ MODULATOR CIRCUIT

A current source flows from the VW pin to the COMP pin, creating

a voltage window set by the resistor between the two pins. This

voltage window is called “VW window” in the following

discussion.

Figure 9 shows the operation principles during load insertion

response. The COMP voltage rises during load insertion,

generating the master clock signal more quickly, so the PWM

pulses turn on earlier, increasing the effective switching

frequency. This allows for higher control loop bandwidth than

conventional fixed frequency PWM controllers. The VW voltage

rises as the COMP voltage rises, making the PWM pulses wider.

During load release response, the COMP voltage falls. It takes

the master clock circuit longer to generate the next master clock

signal so the PWM pulse is held off until needed. The VW voltage

falls as the COMP voltage falls, reducing the current PWM pulse

width. This kind of behavior gives the ISL6267 excellent response

speed.

Inside the IC, the modulator uses the master clock circuit to

generate the clocks for the slave circuits. The modulator

discharges the ripple capacitor C with a current source equal

rm

to g V , where g is a gain factor. C voltage V

m o rm CRM

is a

m

sawtooth waveform traversing between the VW and COMP

voltages. It resets to VW when it hits COMP, and generates a

one-shot master clock signal. A phase sequencer distributes the

master clock signal to the slave circuits. If V is in 3-phase

DD

mode, the master clock signal is distributed to the three phases,

and the Clock 1~3 signals will be 120° out-of-phase. If VR1 is in

2-phase mode, the master clock signal is distributed to Phases 1

and 2, and the Clock1 and Clock2 signals will be 180° out-of-

The fact that all the phases share the same VW window voltage

also ensures excellent dynamic current balance among phases.

January 31, 2011

FN7801.0

14

ISL6267

VW

P H A S E

COMP

V_CRM

U G A TE

LG A TE

MASTER

CLOCK

CLOCK1

PWM1

IL

CLOCK2

PWM2

FIGURE 10. DIODE EMULATION

CLOCK3

PWM3

CCM/DCM

BOUNDARY

VW

V_CRS

VW

IL

VCRS1

VCRS3

VCRS2

LIGHT DCM

VW

V_CRS

3

FIGURE 9. R ™ MODULATOR OPERATION PRINCIPLES IN LOAD

INSERTION RESPONSE

IL

Diode Emulation and Period Stretching

DEEP DCM

VW

The ISL6267 can operate in diode emulation (DE) mode to

improve light-load efficiency. In DE mode, the low-side MOSFET

conducts when the current is flowing from source to drain and

does not allow reverse current, thus emulating a diode. As Figure

10 shows, when LGATE is on, the low-side MOSFET carries current,

creating negative voltage on the phase node due to the voltage

drop across the ON-resistance. The ISL6267 monitors the current

by monitoring the phase node voltage. It turns off LGATE when the

phase node voltage reaches zero to prevent the inductor current

from reversing the direction and creating unnecessary power loss.

V_CRS

IL

FIGURE 11. PERIOD STRETCHING

Start-up Timing

With the controller's V and V voltages above their POR

DD IN

If the load current is light enough, as Figure 10 shows, the

inductor current reaches and stays at zero before the next phase

node pulse, and the regulator is in discontinuous conduction

mode (DCM). If the load current is heavy enough, the inductor

current will never reaches 0A, and the regulator is in CCM,

although the controller is in DE mode.

threshold, the start-up sequence begins when ENABLE exceeds the

logic high threshold. Figure 12 shows the typical start-up timing of

VR1 and VR2. The ISL6267 uses digital soft-start to ramp-up DAC

to the voltage programmed by the Metal VID. PGOOD is asserted

high and low at the end of the ramp up. Similar results occur if

ENABLE is tied to V , with the soft-start sequence starting

DD

Figure 11 shows the operation principle in diode emulation mode

at light load. The load gets incrementally lighter in the three cases

from top to bottom. The PWM on-time is determined by the VW

window size and therefore is the same, making the inductor

current triangle the same in the three cases. The ISL6267 clamps

800µs after V crosses the POR threshold.

DD

the ripple capacitor voltage V

in DE mode to make it mimic the

CRS

inductor current. It takes the COMP voltage longer to hit V

,

CRS

naturally stretching the switching period. The inductor current

triangles move farther apart such that the inductor current

average value is equal to the load current. The reduced switching

frequency helps increase light-load efficiency.

January 31, 2011

FN7801.0

15

ISL6267

Hysteresis between the rising and the falling thresholds assure

VDD

the ISL6267 does not inadvertently turn off unless the bias

voltage drops substantially (see “Electrical Specifications” on

page 11).

SLEW RATE

1.875mV/µs

ENABLE

MetalVID

VID COMMAND

VOLTAGE

800µs

Serial VID Interface

DAC

The on-board Serial VID Interface (SVI) circuitry allows the

processor to directly control the Core and Northbridge voltage

reference levels within the ISL6267. The SVC and SVD states are

decoded according to the PWROK inputs as described in the

following sections. The ISL6267 uses a digital-to-analog

converter (DAC) to generate a reference voltage based on the

decoded SVI value. See Figure 13 for a simple SVI interface

timing diagram.

PGOOD

PWROK

VIN

FIGURE 12. TYPICAL SOFT-START WAVEFORMS

Power-On Reset

Before the controller has sufficient bias to guarantee proper

operation, the ISL6267 requires both a +5V input supply tied to

Pre-PWROK Metal VID

Typical motherboard start-up begins with the controller decoding

the SVC and SVD inputs to determine the pre-PWROK Metal VID

setting (see Table 1). Once the ENABLE input exceeds the rising

threshold, the ISL6267 decodes and locks the decoded value in

an on-board hold register.

V

and PV , as well as a battery or other input supply tied to

CC

, to exceed their respective rising power-on reset (POR)

CC

IN

thresholds. Once these thresholds are reached or exceeded, the

ISL6267 has enough bias to begin checking SVI inputs.

1

4

5

6

2

3

7

8

9

10

11

12

VCC

SVC

SVD

ENABLE

PWROK

V_SVI

METAL_VID

V

/ V

CORE NB

PGOOD

Interval 1 to 2: ISL6267 waits to POR.

Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.

Interval 3 to 4: ENABLE locks pre-Metal VID code. All outputs soft-start to this level.

Interval 4 to 5: PGOOD signal goes HIGH, indicating proper operation.

Interval 5 to 6: CPU detects PGOOD high, and drives PWROK high, to allow ISL6267 to prepare for SVI commands.

Interval 6 to 7: SVC and SVD data lines communicate change in VID code.

Interval 7 to 8: ISL6267 responds to VID-ON-THE-FLY code change.

Interval 8 to 9: PWROK is driven low, and ISL6267 returns all outputs to pre-PWROK Metal VID level.

Interval 9 to 10: PWROK driven high once again by CPU, and ISL6267 prepares for SVI commands.

Interval 10 to 11: SVC and SVD data lines communicate new VID code.

Interval 11 to 12: ISL6267 drives outputs to new VID code level.

Post 12: Enable falls, all internal drivers are tri-stated, and PGOOD is driven low.

FIGURE 13. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP

January 31, 2011

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ISL6267

If the PWROK input is de-asserted, then the controller steps both

TABLE 1. PRE-PWROK METAL VID CODES

the Core and the Northbridge VRs back to the stored pre-PWROK

metal VID level in the holding register from initial soft-start. No

attempt is made to read the SVC and SVD inputs during this time.

If PWROK is re-asserted, then the on-board SVI interface waits for

a set VID command.

SVC

SVD

OUTPUT VOLTAGE (V)

0

1

0

1

0

1

1.1

1.0

0.9

0.8

If ENABLE goes low during normal operation, all internal drivers

are tri-stated and PGOOD is pulled low. This event clears the

pre-PWROK metal VID code and forces the controller to check

SVC and SVD upon restart.

The internal DAC circuitry begins to ramp Core and Northbridge

VRs to the decoded pre-PWROK Metal VID output level. The

digital soft-start circuitry ramps the internal reference to the

target gradually at a fixed rate of approximately 2mV/µs. The

controlled ramp of all output voltage planes reduces in-rush

current during the soft-start interval. At the end of the soft-start

interval, the PGOOD output transitions high, indicating all output

planes are within regulation limits.

A POR event on either VCC or VIN during normal operation shuts

down both regulators, and both PGOOD outputs are pulled low.

The pre-PWROK metal VID code is not retained.

VID-on-the-Fly Transition

Once PWROK is high, the ISL6267 detects this flag and begins

monitoring the SVC and SVD pins for SVI instructions. The

microprocessor follows the protocol outlined in the following

sections to send instructions for VID-on-the-fly transitions. The

ISL6267 decodes the instruction and acknowledges the new VID

code. For VID codes higher than the current VID level, the

ISL6267 begins stepping the commanded VR outputs to the new

VID target with a typical slew rate of 7.5mV/µs, which meets the

AMD requirements.

If the ENABLE input falls below the enable falling threshold, the

ISL6267 tri-states both outputs. PGOOD is pulled low with the

loss of ENABLE. The Core and Northbridge planes decay, based

on output capacitance and load leakage resistance. If bias to

VCC falls below the POR level, the ISL6267 responds in the

manner previously described. Once VCC and ENABLE rise above

their respective rising thresholds, the internal DAC circuitry re-

acquires a pre-PWROK metal VID code, and the controller

soft-starts.

When the VID codes are lower than the current VID level, the

ISL6267 checks the state of PSI_L. If PSI_L is high, the controller

begins stepping the regulator output to the new VID target with a

typical slew rate of -7.5mV/µs. If PSI_L is low, the controller

allows the output voltage to decay and slowly steps the DAC

down with the natural decay of the output. This allows the

controller to quickly recover and move to a high VID code if

commanded. AMD requirements under these conditions do not

require the regulator to meet the minimum slew rate

specification of -5mV/µs. In either case, the slew rate is not

allowed to exceed 10mV/µs. The ISL6267 does not change the

state of PGOOD (VCCPWRGD in AMD specifications) when a

VID-on-the-fly transition occurs.

VFIX Mode

The ISL6267 does not support VFIX Mode. In the event a CPU is

not present on a motherboard and the ISL6267 is powered on,

the state of SVC and SVD sets the pre-PWROK metal VID as the

“Pre-PWROK Metal VID” on page 16 and begins soft-starting.

SVI Mode

Once the controller has successfully soft-starts and PGOOD and

PGOOD_NB transition high, the processor can assert PWROK to

signal the ISL6267 to prepare for SVI commands. The controller

actively monitors the SVI interface for set VID commands to

move the plane voltages to start-up VID values. Details of the SVI

Bus protocol are provided in the “AMD Design Guide for Voltage

Regulator Controllers Accepting Serial VID Codes” specification.

SVI WIRE Protocol

The SVI WIRE protocol is based on the I C bus concept. Two wires

2

[serial clock (SVC) and serial data (SVD)], carry information

between the AMD processor (master) and VR controller (slave) on

the bus. The master initiates and terminates SVI transactions

and drives the clock, SVC, during a transaction. The AMD

processor is always the master, and the voltage regulators are

the slaves. The slave receives the SVI transactions and acts

accordingly. Mobile SVI WIRE protocol timing is based on

Once a set VID command is received, the ISL6267 decodes the

information to determine which VR is affected and which VID

target is required (see Table 2). The internal DAC circuitry steps

the output voltage of the VR commanded to the new VID level.

During this time, one or more of the VR outputs could be

targeted. In the event either VR is commanded to power-off by

serial VID commands, the PGOOD signal remains asserted.

2

high-speed mode I C. See AMD publication #40182 for

additional details.

January 31, 2011

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ISL6267

.

TABLE 2. SERIAL VID CODES

SVID[6:0]

000_0000b

000_0001b

000_0010b

000_0011b

000_0100b

000_0101b

000_0110b

000_0111b

000_1000b

000_1001b

000_1010b

000_1011b

000_1100b

000_1101b

000_1110b

000_1111b

001_0000b

001_0001b

001_0010b

001_0011b

001_0100b

001_0101b

001_0110b

001_0111b

001_1000b

001_1001b

001_1010b

001_1011b

001_1100b

001_1101b

001_1110b

001_1111b

VOLTAGE (V)

1.5500

1.5375

1.5250

1.5125

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

SVID[6:0]

010_0000b

010_0001b

010_0010b

010_0011b

010_0100b

010_0101b

010_0110b

010_0111b

010_1000b

010_1001b

010_1010b

010_1011b

010_1100b

010_1101b

010_1110b

010_1111b

011_0000b

011_0001b

011_0010b

011_0011b

011_0100b

011_0101b

011_0110b

011_0111b

011_1000b

011_1001b

011_1010b

011_1011b

011_1100b

011_1101b

011_1110b

011_1111b

VOLTAGE (V)

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

SVID[6:0]

100_0000b

100_0001b

100_0010b

100_0011b

100_0100b

100_0101b

100_0110b

100_0111b

100_1000b

100_1001b

100_1010b

100_1011b

100_1100b

100_1101b

100_1110b

100_1111b

101_0000b

101_0001b

101_0010b

101_0011b

101_0100b

101_0101b

101_0110b

101_0111b

101_1000b

101_1001b

101_1010b

101_1011b

101_1100b

101_1101b

101_1110b

101_1111b

VOLTAGE (V)

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875*

0.4750*

0.4625*

0.4500*

0.4375*

0.4250*

0.4125*

0.4000*

0.3875*

0.3750*

0.3625*

SVID[6:0]

110_0000b

110_0001b

110_0010b

110_0011b

110_0100b

110_0101b

110_0110b

110_0111b

110_1000b

110_1001b

110_1010b

110_1011b

110_1100b

110_1101b

110_1110b

110_1111b

111_0000b

111_0001b

111_0010b

111_0011b

111_0100b

111_0101b

111_0110b

111_0111b

111_1000b

111_1001b

111_1010b

111_1011b

111_1100b

111_1101b

111_1110b

111_1111b

VOLTAGE (V)

0.3500*

0.3375*

0.3250*

0.3125*

0.3000*

0.2875*

0.2750*

0.2625*

0.2500*

0.2375*

0.2250*

0.2125*

0.2000*

0.1875*

0.1750*

0.1625*

0.1500*

0.1375*

0.1250*

0.1125*

0.1000*

0.0875*

0.0750*

0.0625*

0.0500*

0.0375*

0.0250*

0.0125*

OFF

NOTE: *Indicates a VID not required for AMD Family 10h processors.

January 31, 2011

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ISL6267

See Table 3

SVID

5

4

3

2

1

0

7

5

4

2

1

6

3

0

SVC

SVD

SLAVE ADDRESS PHASE

DATA PHASE

FIGURE 14. SEND BYTE EXAMPLE

SVI Bus Protocol

VR Offset Programming

The AMD processor bus protocol is compliant with SMBus send

byte protocol for VID transactions (see Figure 14). During a send

byte transaction, the processor sends the start sequence

followed by the slave address of the VR for which the VID

command applies. The address byte must be configured

according to Table 3. The processor then sends the write bit. After

the write bit, if the ISL6267 receives a valid address byte, it

sends the acknowledge bit. The processor then sends the PSI-L

bit and VID bits during the data phase. The Serial VID 8-bit data

field encoding is outlined in Table 4. If ISL6267 receives a valid

8-bit code during the data phase, it sends the acknowledge bit.

Finally, the processor sends the stop sequence. After the

ISL6267 has detected the stop, it can then proceed with the

VID-on-the-fly transition.

A positive or negative offset is programmed for the Core VR using

a resistor to ground from the PROG1 pin and the Northbridge in a

similar manner from the PROG2 pin. Table 5 provides the resistor

value to select the desired output voltage offset

TABLE 5. PROGx PIN RESISTOR VALUE

PROG1

RESISTOR VALUE

PROG1

VNB

[Ω]

V

[mV]

OFFSET [mV]

CORE OFFSET

0

50

590

43.75

37.50

31.25

25.00

18.75

12.50

6.25

43.75

37.50

31.25

25.00

18.75

12.50

6.25

1100

1690

2260

3160

4320

5620

6650

7870

9530

11500

14000

16500

18700

OPEN

TABLE 3. SVI SEND BYTE ADDRESS DESCRIPTION

BITS

DESCRIPTION

6:4 Always 110b

3

2

Reserved by AMD for future use

VDD1; if set, then the following data byte contains the VID for

VDD1 [Note: The ISL6267 does not support VDD1]

0.00

-6.25

1

0

VDD0; if set, then the following data byte contains the VID for

VID0

-12.50

-18.75

-25.00

-31.25

-37.50

-43.75

-12.50

-18.75

-25.00

-31.25

-37.50

-43.75

VDDNB; if set then the following data byte contains the VID for

VIDNB

TABLE 4. SERIAL VID 8-BIT DATA FIELD ENCODING

DESCRIPTION

BITS

7

PSI_L:

=0 means the processor is at an optimal load for the regulators

to enter power-saving mode

=1 means the processor is not at an optimal load for the

regulators to enter power-saving mode

Voltage Regulation and Load Line

Implementation

After the start sequence, the ISL6267 regulates the output voltage

to the value set by the VID information, per Table 2. The ISL6267

controls the no-load output voltage to an accuracy of ±0.5% over

the range of 0.75V to 1.55V. A differential amplifier allows

voltage sensing for precise voltage regulation at the

microprocessor die.

6:0 SVID[6:0] as defined in Table 2.

Operation

After the start-up sequence, the ISL6267 begins regulating the

Core and Northbridge output voltages to the pre-PWROK metal

VID programmed. The controller monitors SVI commands to

determine when to enter power-saving mode, implement

dynamic VID changes, and shut down individual outputs.

January 31, 2011

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19

ISL6267

amplifier regulates the inverting and non-inverting input voltages

to be equal as shown in Equation 3:

Rdroop

VCC_SENSE

+

-

VCC

+ V

= V

+ VSS

SENSE

(EQ. 3)

SENSE

DAC

Vdroop

droop

FB

VR LOCAL VO

“CATCH” RESISTOR

Idroop

Rewriting Equation 3 and substituting Equation 2 gives

Equation 4 is the exact equation required for load-line

implementation.

+

-

E/A

VIDs

COMP

VID<0:7>

VSS_SENSE

DAC

X 1

Σ

VDAC

+

RTN

VSS

VCC

– VSS

= V

– R

× I

droop droop

(EQ. 4)

+

-

SENSE

DAC

INTERNAL TO IC

The VCC

SENSE

and VSS

signals come from the processor die.

“CATCH” RESISTOR

SENSE

The feedback is, open circuit in the absence of the processor. As

Figure 15 shows, it is recommended to add a “catch” resistor to feed

the VR local output voltage back to the compensator, and to add

another “catch” resistor to connect the VR local output ground to the

RTN pin. These resistors, typically 10Ω~100Ω, provide voltage

feedback if the system is powered up without a processor installed.

FIGURE 15. DIFFERENTIAL SENSING AND LOAD LINE

IMPLEMENTATION

As the load current increases from zero, the output voltage

droops from the VID table value by an amount proportional to the

load current, to achieve the load line. The ISL6267 can sense the

inductor current through the intrinsic DC Resistance (DCR) of the

inductors, as shown in Figures 15 and 16, or through resistors in

series with the inductors as shown in Figure 17. In both methods,

Phase Current Balancing

R_dcr3

R_dcr2

R_dcr1

L3

L2

L1

R_pcb3

capacitor C voltage represents the inductor total currents. A

n

PHASE3

R_isen

droop amplifier converts C voltage into an internal current

n

I_L3

I_L2

I_L1

ISEN3

INTERNAL

source with the gain set by resistor R . The current source is used

i

C_isen

for load line implementation, current monitoring and overcurrent

protection.

R_pcb2

V_O

INTERNAL

TO IC

PHASE2

R_isen

ISEN2

Figure 15 shows the load-line implementation. The ISL6267

C_isen

drives a current source (I

Equation 1.

) out of the FB pin, as described by

droop

R_pcb1

PHASE1

R_isen

2xV

Cn

R

i

ISEN1

----------------

I

=

(EQ. 1)

droop

C_isen

FIGURE 16. CURRENT BALANCING CIRCUIT

When using inductor DCR current sensing, a single NTC element

is used to compensate the positive temperature coefficient of the

copper winding, thus sustaining the load-line accuracy with

reduced cost.

The ISL6267 monitors individual phase average current by

monitoring the ISEN1, ISEN2, and ISEN3 voltages. Figure 16

shows the current balancing circuit recommended for ISL6267.

Each phase node voltage is averaged by a low-pass filter

I

flows through resistor R

droop

and creates a voltage drop as

consisting of R

corresponding ISEN pin. R

and C

, and is presented to the

should be routed to the inductor

droop

shown in Equation 2.

isen

phase-node pad in order to eliminate the effect of phase node

parasitic PCB DCR. Equations 5 through 7 give the ISEN pin

voltages:

V

= R

× I

droop droop

(EQ. 2)

droop

V

= (R

+ R

) × I

V

is the droop voltage required to implement load line.

(EQ. 5)

droop

ISEN1

dcr1

pcb1

L1

Changing R

or scaling I

can change the load line slope.

droop

also sets the overcurrent protection level, it is

droop

Since I

droop

V

= (R

+ R

) × I

recommended to first scale I

then select an appropriate R

load line slope.

based on OCP requirement,

value to obtain the desired

(EQ. 6)

(EQ. 7)

ISEN2

dcr2

pcb2

L2

droop

V

= (R

+ R

) × I

ISEN3

dcr3

pcb3

L3

Differential Sensing

Figure 15 also shows the differential voltage sensing scheme.

VCC and VSS are the remote voltage sensing signals

from the processor die. A unity gain differential amplifier senses

where R

, R

and R

are inductor DCR; R

, R

dcr1 dcr2

dcr3

pcb1 pcb2

SENSE SENSE

and R

are parasitic PCB DCR between the inductor output

pcb3

side pad and the output voltage rail; and I , I and I are

inductor average currents.

L1 L2

L3

the VSS

voltage and adds it to the DAC output. The error

SENSE

January 31, 2011

FN7801.0

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ISL6267

The ISL6267 will adjusts the phase pulse-width relative to the

Rewriting Equation 11 gives Equation 13:

V

– V

= V – V

other phases to make V

= V

, thus to achieve

(EQ. 13)

(EQ. 14)

(EQ. 15)

ISEN1

= R

ISEN2

= R

ISEN3

and

1p

1n 2p 2n

I

= I = I , when R

L1 L2 L3 dcr1

dcr2

dcr3

Rewriting Equation 12 gives Equation 14:

V

R

= R

pcb2

= R

.

pcb3

pcb1

– V

= V – V

2p

2n 3p 3n

Using the same components for L1, L2 and L3 provides a good

match of R , R and R . Board layout determines R

,

dcr1 dcr2 dcr3 pcb1

Combining Equations 13 and 14 gives:

V

R

and R

. It is recommended to have symmetrical layout

pcb2

pcb3

– V

= V – V

3n

1p

1n

2p

2n

3p

for the power delivery path between each inductor and the output

voltage rail, such that R

= R

pcb2

= R

.

pcb1

pcb3

Therefore:

R_dcr3

L3

R_pcb3

V3p

R

× I

= R

× I

= R

× I

dcr3 L3

PHASE3

(EQ. 16)

dcr1

L1

dcr2

L2

R_isen

I_L3

I_L2

I_L1

ISEN3

Cisen

V_3n

Current balancing (I = I = I ) is achieved when

L1 L2 L3

R

= R

. R , R

and R do not have any

INTERNAL

TO IC

dcr1

effect.

dcr2 dcr3 pcb1 pcb2

pcb3

R_dcr2

L2

L1

R_pcb2

V

o

V2p

R_isen

PHASE2

Since the slave ripple capacitor voltages mimic the inductor

currents, the R ™ modulator can naturally achieve excellent

ISEN2

V_2n

3

R_isen

C_isen

current balancing during steady state and dynamic operations.

Figure 18 shows the current balancing performance of the

evaluation board with load transient of 12A/51A at different rep

rates. The inductor currents follow the load current dynamic

change with the output capacitors supplying the difference. The

inductor currents can track the load current well at a low

repetition rate, but cannot keep up when the repetition rate gets

into the hundred-kHz range, where it is out of the control loop

bandwidth. The controller achieves excellent current balancing in

all cases installed.

R_dcr1

R_pcb1

V1p

PHASE1

R_isen

ISEN1

C_isen

V_1n

FIGURE 17. DIFFERENTIAL-SENSING CURRENT BALANCING

CIRCUIT

Sometimes, it is difficult to implement symmetrical layout. For

the circuit shown in Figure 16, asymmetric layout causes

CCM Switching Frequency

The R

resistor between the COMP and the VW pins sets the

fset

different R

, R

and R values, thus creating a current

pcb1 pcb2

pcb3

VW windows size and therefore sets the switching frequency.

When the ISL6267 is in continuous conduction mode (CCM), the

switching frequency is not absolutely constant due to the nature

imbalance. Figure 17 shows a differential sensing current

balancing circuit recommended for ISL6267. The current sensing

traces should be routed to the inductor pads so they only pick up

the inductor DCR voltage. Each ISEN pin sees the average voltage

of three sources: its own, phase inductor phase-node pad, and

the other two phases inductor output side pads. Equations 8

through 10 give the ISEN pin voltages:

3

of the R ™ modulator. As explained in the “Multiphase R3™

Modulator” on page 14, the effective switching frequency

increases during load insertion and decreases during load

release to achieve fast response. Thus, the switching frequency is

relatively constant at steady state. Variation is expected when

the power stage condition, such as input voltage, output voltage,

load, etc. changes. The variation is usually less than 15% and

does not have any significant effect on output voltage ripple

magnitude. Equation 17 gives an estimate of the frequency-

V

= V + V + V

1p 2n 3n

(EQ. 8)

ISEN1

V

= V + V + V

1n 2p

(EQ. 9)

ISEN2

ISEN3

3n

3p

= V + V + V

(EQ. 10)

1n

2n

setting resistor (R ) value. A value of 8kΩ R

approximately 300kHz switching frequency. Lower resistance

gives higher switching frequency.

gives

fset fset

The ISL6267 will make V

Equations 11 and 12:

= V

= V as shown in

ISEN3

ISEN1

ISEN2

V

+ V + V

= V + V + V

(EQ. 11)

(EQ. 12)

1p

2n

3n

1n 2p

3n

3p

(EQ. 17)

R

(kΩ) = (Period(μs) – 0.29) × 2.65

fset

V

+ V + V

= V + V + V

1n 2n

1n

2p

3n

January 31, 2011

FN7801.0

21

ISL6267

Modes of Operation

REP RATE = 10kHz

TABLE 6. CORE VR MODES OF OPERATION

OCP

Threshold

(µA)

PWM3

To

External Stage

Driver

ISEN2

CONFIG. PSL_L

MODE

3-phase CCM

1-phase DE

To Power 3-phase

1

0

60

20

CPU VR

Config.

Tied to 5V

2-phase

CPU VR

Config.

1

0

2-phase CCM

1-phase DE

60

30

Tied to

5V

1-phase

CPU VR

Config.

X

1-phase DE

60

REP RATE = 25kHz

The Core VR can be configured for 3, 2- or 1-phase operation.

Table 6 shows Core VR configurations and operational modes,

programmed by the PWM3 and ISEN2 pin status and the PS

command. For 2-phase configuration, tie the PWM3 pin to 5V. In

this configuration, phases 1 and 2 are active. For 1-phase

configuration, tie the PWM3 pin and the ISEN2 pin to 5V. In this

configuration, only phase-1 is active and the controller operates

in DE mode and the PSI_L input is ignored.

In 3-phase configuration, Core VR operates in 3-phase CCM, with

PSI_L high. It enters 1-phase DE mode when PSI_L is low,

dropping phases 3 and 2, and reduces the overcurrent and the

way-overcurrent protection levels to one-third of the initial values.

REP RATE = 50kHz

In 2-phase configuration, Core VR operates in 2-phase CCM with

PSI_L high. It enters 1-phase DE mode with PSI_L low, by

dropping phase 2 and reduces the overcurrent and the

way-overcurrent protection levels to one-half of the initial values.

In 1-phase configuration, the Core VR operates in 1-phase DE and

ignores the PSI_L input. If a resistor is placed from COMP pin to

GND with a value less than 150kΩ, then the Core VR operates in

1-phase CCM with PSI_L high and enters 1-phase DE mode when

PSI_L is low. A resistor value of 100kΩ is recommended.

REP RATE = 100kHz

TABLE 7. NORTHBRIDGE VR MODES OF OPERATION

OCP

ISEN2_NB

To Power

CONFIG.

PSL_L

MODE

2-phase CCM

1-phase DE

Threshold

60uA

2-phase NB

VR Config.

1

0

X

Stage

30uA

Tied to 5V

1-phase NB

VR Config.

60uA

REP RATE = 200kHz

ISL6267 Northbridge (NB) VR can be configured for 2- or 1-phase

operation. Table 7 shows the Northbridge VR configurations and

operational modes, which are programmed by the ISEN2 pin

status and the PSI_L command. For 1-phase configuration, tie

the ISEN2_NB pin to 5V.

In 1-phase configuration, the Northbridge VR operates in 1-phase

DE and ignores the PSI_L input. If a resistor is placed from

COMP_NB pin to GND with a value less than 150kΩ, then the

Northbridge VR operates in 1-phase CCM with PSI_L high and

enters 1-phase DE mode when PSI_L is low. A resistor value of

100kΩ is recommended.

FIGURE 18. CURRENT BALANCING DURING DYNAMIC

OPERATION. CH1: I , CH2: I

, CH3: I , CH4:

L1

LOAD

L2

I

L3

The Northbridge VR can be disabled completely by tying

ISUMN_NB to 5V.

January 31, 2011

FN7801.0

22

ISL6267

threshold. When ENABLE and V return to their high operating

DD

levels, a soft-start occurs.

Dynamic Operation

Core VR and Northbridge VR behave the same during dynamic

operation. The controller responds to VID-on-the-fly changes by

slewing to the new voltage at the fixed 7.5mV/µs slew rate.

During negative VID transitions, the output voltage decays to the

lower VID value at the slew rate determined by the load.

Table 8 summarizes the fault protections.

TABLE 8. FAULT PROTECTION SUMMARY

FAULT DURATION

BEFORE

PROTECTION

ACTION

FAULT

RESET

SVI_L low command prompts the controller to enter DE mode.

Overvoltage protection is blanked during VID down transition in

DE mode until the output voltage is within 60mV of the VID value.

FAULT TYPE

Overcurrent

120µs

1ms

PWM tri-state,

PGOOD latched toggle or

low

ENABLE

Phase Current

Unbalance

During load insertion response, the Fast Clock function increases

the PWM pulse response speed. The controller monitors the

VSEN pin voltage and compares it to 100ns-filtered version.

When the unfiltered version is 20mV below the filtered version,

the controller knows there is a fast voltage dip due to load

insertion, and it issues an additional master clock signal to

deliver a PWM pulse immediately.

VDD toggle

Way-Overcurrent

(1.5xOC)

Immediately

Overvoltage +200mV

PGOOD latched

low. Actively pulls

the output

voltage to below

VID value, then

tri-state.

3

The R ™ modulator intrinsically has voltage feed-forward. The

output voltage is insensitive to a fast slew rate input voltage

change.

Over-Temperature

400µs

N/A

Protections

Core VR and Northbridge VR both provide overcurrent,

current-balance and overvoltage fault protections. The controller

also provides over-temperature protection. The following

discussion is based on Core VR and also applies to Northbridge VR.

FB2 Function

The FB2 function is only available for Core VR or Northbridge VR

in 2-phase configuration.

C1

R2

C3.1

C3.2

R2

C3.1

C3.2

CONTROLLER

IN

2-PHASE MODE

CONTROLLER

IN

1-PHASE MODE

The controller determines overcurrent protection (OCP) by

comparing the average value of the droop current (I

C2

R3

C2

R3

FB2

) with an

droop

internal current source threshold as Table 6 shows. It declares OCP

when I is above the threshold for 120µs.

R1

VSEN

droop

VSEN

COMP

E/A

FB

COMP

For overcurrent conditions above 1.5x the OCP level, the PWM

outputs immediately shuts off and PGOOD goes low to maximize

protection. This protection is also referred to as way-overcurrent

protection or fast overcurrent protection for short-circuit

protections.

VREF

FIGURE 19. FB2 FUNCTION

Figure 19 shows the FB2 function. A switch (called FB2 switch)

turns on to short the FB and the FB2 pins when the controller is in

2-phase mode. Capacitors C3.1 and C3.2 are in parallel, serving

as part of the compensator. When the controller enters 1-phase

mode, the FB2 switch turns off, removing C3.2 and leaving only

C3.1 in the compensator. The compensator gain increases with

the removal of C3.2. By properly sizing C3.1 and C3.2, the

compensator can be optimal for both 2-phase mode and 1-phase

mode.

The controller monitors the ISEN pin voltages to determine

current-balance protection. If the ISEN pin voltage difference is

greater than 9mV for 1ms, the controller will declare a fault and

latch off.

The controller takes the same actions for all of the previously

describe fault protections: de-assertion of PGOOD and turn-off of

the high-side and low-side power MOSFETs. Any residual inductor

current decays through the MOSFET body diodes.

When the FB2 switch is off, C3.2 is disconnected from the FB pin.

However, the controller still actively drives the FB2 pin voltage to

follow the FB pin voltage such that C3.2 voltage always follows

C3.1 voltage. When the controller turns on the FB2 switch, C3.2

is reconnected to the compensator smoothly.

The controller declares an overvoltage fault and de-asserts PGOOD if

the output voltage exceeds the VID set value by +250mV. The

ISL6267 immediately declares an OV fault, de-asserts PGOOD,

and turn on the low-side power MOSFETs. The low-side power

MOSFETs remain on until the output voltage is pulled down below

the VID set value when all power MOSFETs are turned off. If the

output voltage rises above the VID set value +250mV again, the

protection process is repeated. This behavior provides the

maximum amount of protection against shorted high-side power

MOSFETs while preventing output ringing below ground.

The FB2 function ensures excellent transient response in both

2-phase and 1-phase mode. If the FB2 function is not used,

populate C3.1 only.

Adaptive Body Diode Conduction Time

Reduction

In DCM, the controller turns off the low-side MOSFET when the

inductor current approaches zero. During on-time of the low-side

MOSFET, phase voltage is negative, and the amount is the

All of the previously described fault conditions can be reset by

bringing ENABLE low or by bringing V below the POR

DD

January 31, 2011

FN7801.0

23

ISL6267

MOSFET r

voltage drop, which is proportional to the

domain relationship between inductor total current I (s) and C

o

DS(ON)

n

inductor current. A phase comparator inside the controller

monitors the phase voltage during on-time of the low-side

MOSFET and compares it with a threshold to determine the zero

crossing point of the inductor current. If the inductor current has

not reached zero when the low-side MOSFET turns off, it will flow

through the low-side MOSFET body diode, causing the phase

node to have a larger voltage drop until it decays to zero. If the

inductor current has crossed zero and reversed the direction

when the low-side MOSFET turns off, it will flow through the

high-side MOSFET body diode, causing the phase node to have a

spike until it decays to zero. The controller continues monitoring

the phase voltage after turning off the low-side MOSFET. To

minimize the body diode-related loss, the controller also adjusts

the phase comparator threshold voltage accordingly in iterative

steps such that the low-side MOSFET body diode conducts for

approximately 40ns.

voltage V (s):

Cn

⎛

⎞

⎟

⎠

R

⎜

⎝

DCR

----------------------------------------- -----------

ntcnet

V

(s) =

×

× I (s) × A (s)

(EQ. 18)

Cn

o

cs

R

N

sum

--------------

+

R

ntcnet

N

(R

+ R ) × R

ntc p

ntcs

--------------------------------------------------

R

=

(EQ. 19)

(EQ. 20)

ntcnet

R

+ R

ntc p

ntcs

s

------

1 +

ω

L

s

----------------------

A

ω

(s) =

cs

L

------------

1 +

ω

sns

DCR

-----------

=

(EQ. 21)

(EQ. 22)

L

Key Component Selection

Inductor DCR Current-Sensing Network

1

------------------------------------------------------

PHASE1 PHASE2 PHASE3

=

sns

R

sum

N

--------------

R

×

R_SUM

ntcnet

-----------------------------------------

× C

n

R

R_SUM

sum

N

--------------

R

+

ntcnet

I_SUM+

R_SUM

where N is the number of phases.

R_NTCS

Transfer function A (s) always has unity gain at DC. The inductor

cs

DCR value increases as the winding temperature increases,

L

+

CNVCN

R_P

giving higher reading of the inductor DC current. The NTC R

ntc

-

R_NTC

R_O

DCR

value decrease as its temperature decreases. Proper selection of

, R , R and R parameters ensures that V

I_SUM-

RI

R

sum ntcs ntc Cn

p

represents the inductor total DC current over the temperature

range of interest.

R_O

There are many sets of parameters that can properly temperature-

compensate the DCR change. Since the NTC network and the R

resistors form a voltage divider, V is always a fraction of the

cn

sum

I_O

inductor DCR voltage. It is recommended to have a higher ratio of

to the inductor DCR voltage so the droop circuit has a higher

FIGURE 20. DCR CURRENT-SENSING NETWORK

V

cn

signal level to work with.

Figure 20 shows the inductor DCR current-sensing network for a

3-phase solution. An inductor current flows through the DCR and

A typical set of parameters that provide good temperature

creates a voltage drop. Each inductor has two resistors in R

sum

compensation are: R

= 3.65kΩ, R = 11kΩ, R = 2.61kΩ

sum

p

ntcs

and R connected to the pads to accurately sense the inductor

o

and R = 10kΩ (ERT-J1VR103J). The NTC network parameters

ntc

current by sensing the DCR voltage drop. The R

and R

sum

o

may need to be fine tuned on actual boards. One can apply full

load DC current and record the output voltage reading

immediately; then record the output voltage reading again when

the board has reached the thermal steady state. A good NTC

network can limit the output voltage drift to within 2mV. It is

recommended to follow the Intersil evaluation board layout and

current sensing network parameters to minimize engineering

time.

resistors are connected in a summing network as shown, and feed

the total current information to the NTC network (consisting of

R

, R and R ) and capacitor C . R is a negative

ntcs ntc ntc

p

n

temperature coefficient (NTC) thermistor, used to temperature

compensate the inductor DCR change.

The inductor output side pads are electrically shorted in the

schematic but have some parasitic impedance in actual board

layout, which is why one cannot simply short them together for the

current-sensing summing network. It is recommended to use

V

(s) also needs to represent real-time I (s) for the controller to

Cn

o

achieve good transient response. Transfer function A (s) has a

cs

1Ω~10Ω R to create quality signals. Since R value is much

o

pole w

sns

and a zero w . One needs to match w and w so

sns

L

smaller than the rest of the current sensing circuit, the following

analysis ignores it.

A

(s) is unity gain at all frequencies. By forcing w equal to w

cs sns

L

and solving for the solution, Equation 23 gives Cn value.

The summed inductor current information is presented to the

capacitor C . Equations 18 thru 22 describe the frequency

n

January 31, 2011

FN7801.0

24

ISL6267

L

-----------------------------------------------------------

(EQ. 23)

C

=

n

R

i

o

sum

i

--------------

R

×

L

ntcnet

N

-----------------------------------------

× DCR

R

sum

--------------

R

+

ntcnet

N

For example, given N = 3, R

sum

= 3.65kΩ, R = 11kΩ,

p

V

o

R

= 2.61kΩ, R = 10kΩ, DCR = 0.88mΩ and L = 0.36µH,

ntcs

ntc

Equation 23 gives C = 0.406µF.

RING

BACK

n

Assuming the compensator design is correct, Figure 21 shows the

expected load transient response waveforms if C is correctly

n

FIGURE 24. OUTPUT VOLTAGE RING-BACK PROBLEM

selected. When the load current I

has a square change, the

also has a square response.

core

output voltage V

core

ISUM+

If C value is too large or too small, V (s) does not accurately

Cn

n

represent real-time I (s) and worsens the transient response.

o

Figure 22 shows the load transient response when C is too

n

small. V

sags excessively upon load insertion and may create

core

Rntcs

Cn.1

a system failure. Figure 23 shows the transient response when

C is too large. V is sluggish in drooping to its final value.

Vcn

Cn.2

Rp

n

core

There is excessive overshoot if load insertion occurs during this

time, which may negatively affect the CPU reliability.

Rn

Rntc

ISUM-

Ri

OPTIONAL

i

o

Cip

Rip

OPTIONAL

V

o

FIGURE 25. OPTIONAL CIRCUITS FOR RING-BACK REDUCTION

FIGURE 21. DESIRED LOAD TRANSIENT RESPONSE

WAVEFORMS

Figure 24 shows the output voltage ring-back problem during

load transient response. The load current i has a fast step

o

change, but the inductor current i cannot accurately follow.

i

L

o

Instead, i responds in first-order system fashion due to the

L

nature of the current loop. The ESR and ESL effect of the output

capacitors makes the output voltage V dip quickly upon load

o

current change. However, the controller regulates V according to

o

the droop current i

, which is a real-time representation of i ;

droop

L

V

o

therefore, it pulls V back to the level dictated by i , causing the

o

L

ring-back problem. This phenomenon is not observed when the

output capacitor has very low ESR and ESL, as is the case with all

ceramic capacitors.

FIGURE 22. LOAD TRANSIENT RESPONSE WHEN C IS TOO

n

SMALL

Figure 25 shows two optional circuits for reduction of the

ring-back. C is the capacitor used to match the inductor time

n

constant. It usually takes the parallel of two (or more) capacitors

to get the desired value. Figure 25 shows that two capacitors

i

o

(C and C ) are in parallel. Resistor R is an optional

n.1 n.2

n

component to reduce the V ring-back. At steady state, C

+

o

n.1

C

provides the desired C capacitance. At the beginning of i

n.2

n o

change, the effective capacitance is less because R increases

n

V

the impedance of the C branch. As Figure 22 shows, V tends

o

n.1

o

to dip when C is too small, and this effect reduces the V

n

o

ring-back. This effect is more pronounced when C is much

n.1

FIGURE 23. LOAD TRANSIENT RESPONSE WHEN C IS TOO

n

larger than C . It is also more pronounced when R is bigger.

n.2

n

LARGE

However, the presence of R increases the ripple of the V signal

n

if C is too small. It is recommended to keep C greater than

n.2 n.2

2200pF. R value usually is a few ohms. C , C and R values

n

n.1 n.2

n

January 31, 2011

FN7801.0

25

ISL6267

should be determined through tuning the load transient response

waveforms on an actual board.

Overcurrent Protection

Refer to Equation 1 on page 20 and Figures 20, 24 and 26;

R

and C form an R-C branch in parallel with R , providing a

ip

resistor R sets the droop current, I . Tables 6 and 7 show the

ip

i

droop

lower impedance path than R at the beginning of i change. R

internal OCP threshold. It is recommended to design I

i

o

ip

droop

and C do not have any effect at steady state. Through proper

without using the R

resistor.

ip

comp

For example, the OCP threshold is 60µA for 3-phase solution.

is designed to be 40.9µA at full load, so the OCP trip level

selection of R and C values, i

ip ip

can resemble i rather than

o

droop

i , and V will not ring back. The recommended value for R is

L

o

ip

I

droop

100Ω. C should be determined through tuning the load

ip

is 1.5x of the full load current.

transient response waveforms on an actual board. The

recommended range for C is 100pF~2000pF. However, it

For inductor DCR sensing, Equation 27 gives the DC relationship

of V (s) and I (s):

ip

should be noted that the R -C branch may distort the i

ip ip

droop

cn

o

waveform. Instead of being triangular as the real inductor

⎛

⎜

⎝

⎞

⎟

⎠

R

current, i

affect i

may have sharp spikes, which may adversely

DCR

N

droop

average value detection and therefore may affect

ntcnet

----------------------------------------- -----------

V

=

×

× I

Cn

o

(EQ. 27)

R

droop

sum

--------------

+

R

OCP accuracy. User discretion is advised.

ntcnet

N

Substitution of Equation 27 into Equation 1 gives Equation 28:

R

Resistor Current-Sensing Network

2

DCR

ntcnet

PHASE1 PHASE2 PHASE3

---- ----------------------------------------- -----------

× I

o

I

=

×

(EQ. 28)

droop

R

N

i

sum

N

--------------

+

R

ntcnet

L

Therefore:

2R

× DCR × I

o

ntcnet

-------------------------------------------------------------------------------

R

=

(EQ. 29)

DCR

i

R

sum

N

⎛

⎞

⎠

R_SUM

--------------

N × R

+

× I

ntcnet

droop

⎝

Substitution of Equation 19 and application of the OCP condition

in Equation 29 gives Equation 30:

I_SUM+

+

(R

+ R ) × R

ntc p

RSEN

ntcs

RSEN

VCN

CN

RI

--------------------------------------------------

2 ×

× DCR × I

omax

I_SUM-

R

+ R

ntc p

R_O

ntcs

-

-------------------------------------------------------------------------------------------------------------------------

=

R

(EQ. 30)

i

(R

+ R ) × R

R

⎛

⎜

⎝

⎞

⎟

⎠

ntcs

ntc

p

sum

N

-------------------------------------------------- --------------

N ×

+

× I

droopmax

R

+ R

p

ntcs

ntc

where I

is the full load current and I

is the

omax

droopmax

corresponding droop current. For example, given N = 3,

I_O

R

= 3.65kΩ, R = 11kΩ, R

= 2.61kΩ, R = 10kΩ,

sum

DCR = 0.88mΩ, I

p

ntcs ntc

= 51A and I

= 40.9µA.

FIGURE 26. RESISTOR CURRENT-SENSING NETWORK

omax

droopmax

Equation 30 gives R = 606Ω.

i

Figure 26 shows the resistor current-sensing network for a

2-phase solution. Each inductor has a series current sensing

For resistor sensing, Equation 31 gives the DC relationship of

V

(s) and I (s).

resistor, R . R

accurately capture the inductor current information. The R

and R are connected to the R

pads to

cn

o

sen sum

o

sen

R

sum

and C

n

sen

------------

(EQ. 31)

V

=

× I

Cn

o

and R resistors are connected to capacitor C . R

N

o

n

sum

form a filter for noise attenuation. Equations 24 thru 26 give the

Substitution of Equation 31 into Equation 1 gives Equation 32:

R

V

(s) expression.

Cn

2

sen

R

---- ------------

× I

o

I

=

×

sen

N

(EQ. 24)

(EQ. 25)

(EQ. 32)

droop

------------

V

(s) =

× I (s) × A

(s)

R

N

Cn

o

Rsen

i

1

Therefore:

2R

----------------------

1 +

A

(s) =

Rsen

s

× I

------------

sen

o

(EQ. 33)

---------------------------

=

R

ω

i

sns

N × I

droop

1

---------------------------

ω

=

(EQ. 26)

Rsen

R

Substitution of Equation 33 and application of the OCP condition

in Equation 29 gives Equation 34:

sum

--------------

× C

n

N

2R

× I

sen

omax

--------------------------------------

R =

i

Transfer function A

(s) always has unity gain at DC. Current-

Rsen

(EQ. 34)

N × I

droopmax

sensing resistor R

value does not have significant variation

sen

over-temperature, so there is no need for the NTC network.

where I

is the full load current and I

is the

omax

droopmax

corresponding droop current. For example, given N = 3,

The recommended values are R = 1kΩ and C = 5600pF.

sum

n

R

= 1mΩ, I

omax

= 51A and I

= 40.9µA, Equation 34

droopmax

sen

gives R = 831Ω.

i

January 31, 2011

FN7801.0

26

ISL6267

current, multiplies it by a gain of the load-line slope, adds it on top

of the sensed output voltage, and then feeds it to the

compensator. T1 is measured after the summing node, and T2 is

measured in the voltage loop before the summing node. The

spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s)

can actually be measured on an ISL6267 regulator.

Load Line Slope

See Figure 15 for load-line implementation.

For inductor DCR sensing, substitution of Equation 28 into

Equation 2 gives the load-line slope expression:

V

2R

R

DCR

N

droop

ntcnet

-----------------

---------------------- ----------------------------------------- -----------

LL =

=

×

(EQ. 35)

I

R

sum

o

i

V_O

--------------

+

L

R

ntcnet

N

Q1

For resistor sensing, substitution of Equation 32 into Equation 2

i_O

V_IN

Q2

GATE

DRIVER

C_OUT

gives the load line slope expression:

V

2R

× R

droop

sen droop

(EQ. 36)

-----------------

-----------------------------------------

=

LL =

I

N × R

o

i

LOAD LINE SLOPE

Substitution of Equation 29 and rewriting Equation 35, or

+

substitution of Equation 33 and rewriting Equation 36, gives the

same result as in Equation 37:

²Ω⁰

+

-

EA

MOD.

I

o

COMP

+

---------------

R

=

× LL

(EQ. 37)

VID

droop

I

ISOLATION

TRANSFORMER

droop

CHANNEL B

CHANNEL A

One can use the full-load condition to calculate R

droop

. For

LOOP GAIN =

example, given I

= 51A, I

= 40.9µA and

= 2.37kΩ.

omax

LL = 1.9mΩ, Equation 37 gives R

droopmax

CHANNEL A

CHANNEL B

droop

NETWORK

ANALYZER

EXCITATION OUTPUT

It is recommended to start with the R

value calculated by

droop

Equation 37 and fine-tune it on the actual board to get accurate

load-line slope. One should record the output voltage readings at

no load and at full load for load-line slope calculation. Reading

the output voltage at lighter load instead of full load will increase

the measurement error.

FIGURE 28. LOOP GAIN T1(s) MEASUREMENT SET-UP

T1(s) is the total loop gain of the voltage loop and the droop loop.

It always has a higher crossover frequency than T2(s), therefore

has a higher impact on system stability.

T2(s) is the voltage loop gain with closed droop loop, thus having

a higher impact on output voltage response.

Compensator

Figure 21 shows the desired load transient response waveforms.

Figure 27 shows the equivalent circuit of a voltage regulator (VR)

with the droop function. A VR is equivalent to a voltage source

(= VID) and output impedance Z (s). If Z (s) is equal to the

Design the compensator to get stable T1(s) and T2(s) with sufficient

phase margin and an output impedance equal to or smaller than

the load-line slope.

out

load-line slope LL, i.e., a constant output impedance, then in the

entire frequency range, V will have a square response when I

L

o

V_O

has a square change.

Q1

I_O

V

IN

GATE

DRIVER

Q2

C_O

i

Z_out(s) = LL

o

LOAD LINE SLOPE

VR

V

VID

LOAD

o

Ω

+

20

+

-

EA

MOD.

+

COMP

VID

ISOLATION

TRANSFORMER

FIGURE 27. VOLTAGE REGULATOR EQUIVALENT CIRCUIT

CHANNEL B

CHANNEL A

LOOP GAIN =

Intersil provides a Microsoft Excel-based spreadsheet to help

CHANNEL A

CHANNEL B

design the compensator and the current sensing network so that

VR achieves constant output impedance as a stable system.

Figure 29 shows a screenshot of the spreadsheet.

NETWORK

ANALYZER

EXCITATION OUTPUT

FIGURE 29. LOOP GAIN T2(s) MEASUREMENT SET-UP

A VR with active droop function is a dual-loop system consisting of

a voltage loop and a droop loop, which is a current loop. However,

neither loop alone is sufficient to describe the entire system. The

spreadsheet shows two loop gain transfer functions, T1(s) and

T2(s), that describe the entire system. Figure 28 conceptually

shows T1(s) measurement set-up, and Figure 29 conceptually

shows T2(s) measurement set-up. The VR senses the inductor

Current Balancing

Refer to Figures 16 through 20 for information on current

balancing. The ISL6267 achieves current balancing through

matching the ISEN pin voltages. R

and C

form filters to

isen

remove the switching ripple of the phase node voltages. It is

January 31, 2011

FN7801.0

27

ISL6267

recommended to use a rather long R

that the ISEN voltages have minimal ripple and represent the DC

current flowing through the inductors. Recommended values are

C

time constant such

level. The addition of hysteresis to the over-temperature

threshold prevents nuisance trips. Once both pin voltages exceed

the over-temperature reset threshold, the pull-down on VR_HOT

is released. The signal changes state and the CPU resumes

normal operation. The over-temperature threshold returns to the

trip level.

isen isen

R = 10kΩ and C = 0.22µF.

s

NTC Thermal Monitors and VR_HOT Function

The ISL6267 features three pins (NTC, NTC_NB, and VR_HOT)

that allow the IC to monitor board temperature and alert the

AMD CPU of a thermal issue. Figure 30 shows the thermal

monitor feature of the ISL6267. An NTC network is connected

between the NTC and NTC_NB pins and GND. The controller

drives a 60µA current source out of the NTC pin and the NTC_NB

pin alternatively at 1kHz frequency with 50% duty cycle. The

pulsed current flows through the respective NTC resistor network

on the pins and creates a voltage that is compared to an

over-temperature trip threshold. If the voltage on both NTC pins is

higher than the over-temperature trip threshold, then VR_HOT is

pulled up by an external resistor on the pin.

Selection of the NTC components can vary depending on how the

resistor network is configured. The equivalent resistance at the

typical over-temperature threshold voltage of 0.88V, to change

the state of VR_HOT, is defined in Equation 38.

0.88V

60μA

(EQ. 38)

---------------

= 14.7k

The equivalent resistance at the typical reset threshold voltage of

0.92V required to change the state of VR_HOT back low, is

defined in Equation 39.

0.92V

60μA

(EQ. 39)

---------------

= 15.3k

The NTC thermistor value correlates this resistance change to the

required temperature hysteresis. A standard 1% resistor is

typically needed to meet the NTC pin threshold voltage.

NTC

+V

R

p

+

NTC

60µA

V

For example, a Panasonic NTC thermistor with B = 4700 has a

resistance ratio of 0.03322 of its nominal value at +105°C and

0.03956 of its nominal value at +100°C. The required resistance

of the NTC is defined in Equation 40.

R

NTC

VR_HOT

-

SW1

SW2

R

s

MONITOR

(15.3kΩ – 14.7kΩ)

(0.03956 – 0.03322)

(EQ. 40)

-------------------------------------------------------

= 94.6kΩ

SW1 SW2

NTC_NB

+

The closest, larger thermistor value for B = 4700 is 100kΩ. The

NTC thermistor part number is ERTJ1VV104.

R

p

INTERNAL TO

ISL6267

V

R

NTC

-

At +105°C, a 100kΩ NTC resistance drops to

(0.03322 x 100kΩ) = 3.322kΩ. With a 60µA current flowing out

of the NTC pin, the voltage drop across the resistor is only

(3.322kΩ x 60µA) = 0.199V. This value is much lower than the

threshold voltage of 0.88V. A standard resistor, 1% tolerance,

added in series with the thermistor is required to raise the

voltage on the pin. The resistance required to meet the trip

threshold is calculated in Equation 41.

R

s

FIGURE 30. CIRCUITRY ASSOCIATED WITH THE THERMAL

MONITOR FEATURE OF THE ISL6267

As the board temperature rises, the NTC thermistor resistance

decreases and the voltage at the NTC pin drops. When the

voltage on the NTC pin drops below the over-temperature trip

threshold, then VR_HOT is pulled low. The VR_HOT signal is used

to change the CPU operation and decrease power consumption.

With the reduction in power consumption by the CPU, the board

temperature decreases and the NTC thermistor voltage rises.

Once the over-temperature threshold is tripped and VR_HOT is

taken low, the over-temperature threshold changes to the reset

0.88V

60μA

(EQ. 41)

---------------

– 3.322kΩ = 11.34kΩ

The closest, standard 1% tolerance resistor is 11.3kΩ.

The NTC thermistor is placed in a hot spot on the board, typically

near the upper MOSFET of channel 1 of the respective output.

The standard resistor is placed next to the controller.

Layout Guidelines

Table 9 shows layout considerations for the ISL6267 controller. Refer to the reference designators shown in Figure 31.

TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER

ISL6267

SYMBOL

GND

LAYOUT GUIDELINES

BOTTOM PAD

Create analog ground plane underneath the controller and the analog signal processing components. Do not let

the power ground plane overlap with the analog ground plane. Avoid allowing noisy planes/traces (e.g., phase

node) to crossover/overlap the analog plane.

January 31, 2011

FN7801.0

28

ISL6267

TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER (Continued)

LAYOUT GUIDELINES

ISL6267

SYMBOL

FB2_NB

1

2

Place the compensator components (R25, R9, R24, C88, C51, C86, and C153) close to the controller.

FB_NB

3

COMP_NB

VW_NB

4

Place the capacitor (C85) across VW, and place COMP close to the controller.

No special consideration.

5

PGOOD_NB

6, 7, 8

9

SVD, PWROK, SVC Use good signal integrity practices.

ENABLE

PGOOD

VR_HOT

NTC

No special consideration.

10

11

12

Place the NTC thermistor (R46) close to the thermal source that is monitored to determine CPU V

throttling. Usually it is placed close to Core VR phase-1 high-side MOSFET.

thermal

CORE

13

14

15

16

VW

COMP

FB

Place the capacitor (C4) across VW and COMP close to the controller.

Place the compensator components (R7, R10, R11, C3, C6, C11 and C5) in general proximity to the controller.

FB2

ISEN3

ISEN2

ISEN1

Each ISEN pin has a capacitor (C

GND. Place Cisen capacitors as close as possible to the controller and keep the following loops small:

1. Any ISEN pin to another ISEN pin

) decoupling it to VSUMN and then through another capacitor (C

) to

vsumn

isen

17

18

2. Any ISEN pin to GND

The red traces in the following drawing show the loops to be minimized.

Phase1

L3

Risen

Ro

ISEN3

ISEN2

Cisen

V

o

Phase2

Risen

L2

L1

Phase3

Risen

ISEN1

GND

Vsumn

Cvsumn

19

20

VSEN

RTN

Place the VSEN/RTN filter (C12, C13) close to the controller for good decoupling.

January 31, 2011

FN7801.0

29

ISL6267

TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER (Continued)

LAYOUT GUIDELINES

ISL6267

21

SYMBOL

ISUMN

ISUMP

Place the current sensing circuit in general proximity of the controller.

Place capacitor Cn very close to the controller.

Place the NTC thermistor next to VR1 phase-1 inductor (L1) so it senses the inductor temperature correctly.

Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two

signals traces in parallel fashion with decent width (>20mil).

22

IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. Route R63 and R71

to Core VR phase-1 side pad of inductor L1. Route R88 to the output side pad of inductor L1. Route R65 and

R72 to Core VR phase-2 side pad of inductor L2. Route R90 to the output side pad of inductor L2. If possible,

route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center

of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the

inductor. The following drawings show the two preferred ways of routing current sensing traces.

INDUCTOR

VIAS

CURRENT-SENSING TRACES

23

24

25

26

27

28

VDD

VIN

A capacitor (C16) decouples it to GND. Place it in close proximity to the controller.

A capacitor (C17) decouples it to GND. Place it in close proximity to the controller.

No special consideration.

PROG1

BOOT1

UGATE1

PHASE1

Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.

Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from

crossing over or getting close. Recommend routing PHASE1 trace to VR1 phase-1 high-side MOSFET (Q2 and

Q8) source pins instead of general copper.

29

30

31

32

33

34

LGATE1

PWM3

VCCP

Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.

No special consideration.

A capacitor (C22) decouples it to GND. Place it in close proximity to the controller.

Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.

LGATE2

PHASE2

UGATE2

Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from

crossing over or getting close. Recommend routing PHASE2 trace to VR1 phase-2 high-side MOSFET (Q4 and

Q10) source pins instead of general copper.

35

36

37

38

39

BOOT2

Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.

No special consideration.

PWM2_NB

LGATE1_NB

PHASE1_NB

UGATE1_NB

Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.

Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from

crossing over or getting close. Recommend routing PHASE1G trace to VR2 phase-1 high-side MOSFET source

pins instead of general copper.

40

41

42

BOOT1_NB

PROG2

Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.

No special consideration.

NTC_NB

Place the NTC thermistor close to the thermal source that is monitored to determine GT V

thermal

CORE

throttling. Usually it is placed close to Northbridge VR phase-1 high-side MOSFET.

43

44

ISUMN_NB

ISUMP_NB

Place the current sensing circuit in general proximity to the controller.

Place capacitor Cn very close to the controller.

Place the NTC thermistor next to Northbridge VR phase-1 inductor (L1) so it senses the inductor temperature

correctly.

See ISUMN and ISUMP pins for layout guidelines of current-sensing trace routing.

January 31, 2011

FN7801.0

30

ISL6267

TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER (Continued)

LAYOUT GUIDELINES

ISL6267

45

SYMBOL

RTN_NB

Place the VSEN/RTN filter (C89, C90) in close proximity to the controller for good decoupling.

46

VSEN_NB

ISEN2_NB

ISEN1_NB

47

See ISEN1, ISEN2 and ISEN3 pins for layout guidelines of current-balancing circuit trace routing.

48

FIGURE 31. PORTION OF ISL6267EVAL1Z EVALUATION BOARD SCHEMATIC

January 31, 2011

FN7801.0

31

ISL6267

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest revision.

DATE

REVISION

FN7801.0

CHANGE

1/31/11

Initial Release.

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page

on intersil.com: ISL6267

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

January 31, 2011

32

FN7801.0

ISL6267

Package Outline Drawing

L48.6x6B

48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 9/09

4X

4.4

6.00

0.40

44X

A

6

B

PIN #1 INDEX AREA

48

37

6

1

36

PIN 1

INDEX AREA

4 .40 ± 0.15

25

12

0.15

(4X)

13

24

0.10 M C A B

0.05 M C

TOP VIEW

48X 0.45 ± 0.10

BOTTOM VIEW

4

48X 0.20

SEE DETAIL "X"

C

0.10

C

MAX 1.00

BASE PLANE

SEATING PLANE

0.08

( 44 X 0 . 40 )

( 5. 75 TYP )

(

C

SIDE VIEW

4. 40 )

5

0 . 2 REF

C

( 48X 0 . 20 )

0 . 00 MIN.

0 . 05 MAX.

( 48X 0 . 65 )

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

6.

January 31, 2011

FN7801.0

33


型号：	ISL6267EVAL1Z
厂家：	Intersil
描述：	Multiphase PWM Regulator for AMD Fusion Mobile CPUs 多相PWM稳压的AMD Fusion移动处理器
文件：	总33页 (文件大小：1156K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6267EVAL1Z [INTERSIL]

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