ISL24212IRTZ-T7 [RENESAS]
Analog Circuit;
| 型号： | ISL24212IRTZ-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Analog Circuit 光电二极管 |
| 文件： | 总12页 (文件大小：459K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Programmable V
Output Buffer
Calibrator with EEPROM and
COM
ISL24212
Features
The ISL24212 is an 8-bit programmable current sink that can be
used in conjunction with an external voltage divider to generate a
• Adjustable 8-bit, 256-Step, Current Sink Output
• 60MHz V
COM
Buffer/Amplifier
voltage source (V
) positioned between the analog supply
COM
• On-Chip 8-Bit EEPROM
voltage and ground. The current sink’s full-scale range is
controlled by an external resistor, R . With the appropriate
• Up/Down Counter Interface
• Guaranteed Monotonic Over-Temperature
SET
choice of external resistors R and R , the V
COM
voltage range
1
2
can be controlled between any arbitrary voltage range. The
ISL24212 has an 8-bit data register and 8-bit EEPROM for storing
both a volatile and a permanent value for its output, accessible
through a single up/down counter interface pin (CTL). After the
• 4.5V to 19.0V Analog Supply Range for Normal Operation
(10.8V Minimum Analog Supply Voltage for Programming)
• 2.25V to 3.6V Logic Supply Voltage Operating Range
• Pb-free (RoHS-compliant)
part is programmed with the desired V
value, the Counter
COM
Enable pin (CE) can be grounded to prevent further changes. On
every power-up, the EEPROM contents are automatically
transferred to the data register and the pre-programmed output
voltage appears at the VCOM_OUT pin.
• Ultra-Thin 10 Ld TDFN (3x3x0.8mm max)
Applications
• LCD Panel V
Generator
COM
The ISL24212 also features an integrated, wide-bandwidth, high
output drive buffer amplifier that can directly drive the V
input of an LCD panel.
• Electrophoretic Display V
Generator
COM
COM
Related Literature
• See Application Note “ISL24212IRTZ-EVALZ Evaluation Board
User Guide” (Coming Soon)
The ISL24212 is available in an 10 Ld 3mm x 3mm TDFN
package. This package has a maximum height of 0.8mm for very
low profile designs. The ambient operating temperature range is
-40°C to +85°C.
VDD
AVDD
6
3
R1
2
DVR_OUT
7
CTL
CE
I/O PIN*
I/O PIN
R2
MICRO-
CONTROLLER
1
INN
LCD PANEL
8
ISL24212
10
9
VCOM
VCOM_OUT
SET
RSET
5
* 0, 1, TRISTATE
FIGURE 1. TYPICAL ISL24212 APPLICATION
March 15, 2011
FN7590.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL24212
Block Diagram
AVDD
3
VDD
6
V
COM BUFFER
AMPLIFER
4
ANALOG DCP
DNC
2
AND
DVR_OUT
CURRENT SINK
DIGITAL
INTERFACE
DAC
REGISTERS
7
8
UP/DOWN
COUNTER
CTL
CE
10
Q1
VCOM_OUT
A2
A1
1
9
8-Bit EEPROM
INN
CS
SET
5
GND
FIGURE 2. BLOCK DIAGRAM OF THE ISL24212
Pin Configuration
ISL24212
(10 LD TDFN)
TOP VIEW
VCOM_OUT
1
2
3
4
5
INN
DVR_OUT
AVDD
10
9
SET
CE
EXPOSED
THERMAL
PAD*
8
CTL
VDD
DNC
GND
7
6
(*CONNECT THERMAL PAD TO GND)
Pin Descriptions
PIN
PIN
NAME
NUMBER
FUNCTION
IN
1
2
Negative input of the op amp. To create a unity-gain V voltage buffer, connect this pin to the VCOM_OUT pin.
COM
N
DVR_OUT
Current Sink Output. The sink current into the DVR_OUT (Digital Variable Resistor) pin is equal to the DAC setting times the maximum
adjustable sink current divided by 256. See the “SET” pin function description (pin 9) for setting the maximum adjustable sink
current.
AV
3
4
5
6
7
High-Voltage Analog Supply. Bypass to GND with 0.1µF capacitor.
Do Not Connect to external circuitry. It is acceptable to ground this pin.
Ground connection.
DD
DNC
GND
V
Digital power supply input. Bypass to GND with 0.1µF capacitor.
DD
CTL
Up/Down Control for internal counter and Internal EEPROM Programming Control Input. When CE is high:
A low-to-mid transition increments the 8-bit counter, adding 1 to the DAC setting, increasing the DVR_OUT sink current, and
lowering the divider voltage at the DVR_OUT pin.
A high-to-mid transition decrements the 8-bit counter, subtracting 1 from the DAC setting, decreasing the DVR_OUT sink current,
and increasing the divider voltage at the DVR_OUT pin.
To program the EEPROM, take this pin to >4.9V (see “CTL EEPROM Programming Signal Time” in the “Electrical Specification”
table on page 5 for details). Float when not in use.
FN7590.0
March 15, 2011
2
ISL24212
Pin Descriptions(Continued)
PIN
PIN
NAME
NUMBER
FUNCTION
CE
8
9
Counter Enable Pin. Connect CE to V to enable adjustment of the output sink current. Float or connect CE to GND to prevent
DD
further adjustment or programming (Note: the CE pin has an internal 500nA pull-down sink current). The EEPROM value will be
copied to the register on a V to V transition.
OH OL
SET
Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum adjustable sink current of the
DVR_OUT pin. The maximum adjustable sink current is equal to (AV /20) divided by R
.
DD
SET
VCOM_OUT
PAD
10
-
Output of the buffer amplifier
Thermal pad should be connected to system ground plane to optimize thermal performance.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
INTERFACE
COUNTER
ISL24212IRTZ
4212
Evaluation Board
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL24212IRTZ-EVALZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page ISL24212. For more information on MSL please see techbrief TB363.
FN7590.0
March 15, 2011
3
ISL24212
Absolute Maximum Ratings
Thermal Information
Supply Voltage
Thermal Resistance (Typical)
10 Ld TDFN Package (Notes 4, 5) . . . . . . .
θ
(°C/W)
53
θ
(°C/W)
11
JA
JC
AV to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
DD
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
Moisture Sensitivity (see Technical Brief TB363)
DD
Input Voltage with respect to Ground
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
SET, IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
N
SCL, SDA and WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V +0.3V
DD
Output Voltage with respect to Ground
DVR_OUT, VCOM_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV
DD
Continuous Output Current
DVR_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
VCOM_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±100mA
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 2kV
Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
Operating Range
AV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V
DD
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V
DD
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Test Conditions: V = 3.3V, AV = 18V, R = 5kΩ, R = 10kΩ, R = 10kΩ, (See Figure 5), VCOM_OUT pin
DD
DD
SET
1
2
connected to IN , unless otherwise specified. Typicals are at T = +25°C. Boldface limits apply over the operating temperature range,
N
A
-40°C to +85°C.
MIN
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
DC CHARACTERISTICS
V
V
Supply Range - Operating
2.25
10.8
4.5
3.6
19
19
V
V
V
DD
DD
AV
AV
AV Supply Range Supporting EEPROM Programming
DD
DD
DD
AV Supply Range for Wide-Supply Operation without
DD
EEPROM Programming
I
V
Supply Current
CTL = 0.5*V
95
300
6.5
µA
DD
DD
DD
DD
I
AV Supply Current
CTL = 0.5*V
3.8
mA
AVDD
DD
DVR_OUT CHARACTERISTICS
SET
SET Zero-Scale Error
±3
±8
LSB
LSB
V
ZSE
FSE
SET
SET Full-Scale Error
V
DVR_OUT Voltage Range
SET Voltage Drift
V
+ 1.75
AV
DD
DVR_OUT
SET
SET
7
4
µV/°C
mA
VD
I
Maximum DVR_OUT Sink Current
Integral Non-Linearity
Differential Non-Linearity
DVR_OUT
INL
±2
LSB
LSB
DNL
±1
±15
±1
OUTPUT AMPLIFIER CHARACTERISTICS
V
Input Offset Voltage
±2
-6.3
±0.01
75
mV
µV/°C
μA
OS
TCV
Input Offset Voltage Drift
Input Bias Current
OS
I
B
CMRR
PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Open Loop Gain
55
60
55
dB
82
dB
A
75
dB
VOL
V
Output Swing Low
I = -5mA
50
150
mV
OL
L
FN7590.0
March 15, 2011
4
ISL24212
Electrical Specifications Test Conditions: V = 3.3V, AV = 18V, R = 5kΩ, R = 10kΩ, R = 10kΩ, (See Figure 5), VCOM_OUT pin
DD
DD
SET
1
2
connected to IN , unless otherwise specified. Typicals are at T = +25°C. Boldface limits apply over the operating temperature range,
N
A
-40°C to +85°C. (Continued)
MIN
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 6)
TYP
17.9
430
555
116
93
(Note 6)
UNITS
V
V
Output Swing High
I = 5mA
17.85
300
450
70
OH
L
I
Short Circuit Current (Sinking)
Short Circuit Current (Sourcing)
Slew Rate (Rising)
mA
SC
mA
SR
1KΩ || 8pF Load
1KΩ || 8pF Load
V/µs
V/µs
ns
Slew Rate (Falling)
50
t
Settling Time to 0.2%
-3dB Bandwidth
150
60
S
BW
MHz
EEPROM CHARACTERISTICS
EEPROM Programming Time (internal)
UP/DOWN COUNTER CONTROL INPUTS (SEE FIGURE 11)
t
100
ms
PROG
V
CE and CTL Input Logic High Threshold
CE and CTL Input Logic Low Threshold
CE Input Pull Down Current Sink
CTL Input Bias Current
0.7*V
V
V
IH
DD
V
0.3*V
1.5
15
IL
DD
I
0.5
7
µA
µA
µA
µs
ms
µs
µs
µs
µs
µs
V
CS_PD
I
CTL = GND (sourcing)
CTL
CTL = V (sinking)
DD
7
15
t
CE to CTL Start Delay
50
ST
t
EEPROM Recall Time (after CE de-asserted)
CTL High Pulse Rejection Width
10
20
20
READ
t
H_REJ
t
CTL Low Pulse Rejection Width
L_REJ
t
CTL High Minimum Valid Pulse Width
CTL Low Minimum Valid Pulse Width
CTL Minimum Time Between Counts
CTL EEPROM Program Voltage (see Figure 9)
CTL EEPROM Programming Signal Time
CTL High-to-Mid to DVR_OUT propagation time
CTL Low-to-Mid to DVR_OUT propagation time
200
200
10
H_MIN
t
L_MIN
t
MTC
V
4.9
19
PROG
PROG
t
200
65
µs
µs
µs
t
H_PROP
t
65
L_PROP
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7590.0
March 15, 2011
5
ISL24212
Application Information
AVDD
REGISTER
VALUE
LCD panels have a V
(common voltage) that must be precisely
adjustment
COM
19R
set to minimize flicker. Figure 3 shows a typical V
COM
circuit using a mechanical potentiometer, and the equivalent
circuit replacement using the ISL24212. Having a digital counter
interface enables automatic, digital flicker minimization during
production test and alignment. After programming, the counter
interface is no longer needed - the ISL24212 automatically powers
255
254
AVDD
20
253
252
VDCP
up with the correct V
voltage programmed previously.
COM
The ISL24212 uses a digitally controllable potentiometer (DCP),
with 256 steps of resolution (see Figure 4) to change the current
drawn at the DVR_OUT pin, which then changes the voltage
R
251
2
created by the R - R resistor divider (see Figure 5). The DVR_OUT
1
2
1
voltage is then buffered by A2 to generate a buffered output voltage
at the V pin, capable of directly driving the V input of
0
COM_OUT COM
an LCD panel. The amount of current sunk is controlled by the
setting of the DCP, which is recalled at power-up from the
ISL24212’s internal EEPROM. The EEPROM is typically
programmed during panel manufacture. As noted in the
“Electrical Specifications” on page 4, the ISL24212 requires a
FIGURE 4. SIMPLIFIED SCHEMATIC OF DCP
Output Current Sink
Figure 5 shows the schematic of the DVR_OUT current sink. The
combination of amplifier A1, transistor Q1, and resistor R
forms a voltage-controlled current source, with the voltage
determined by the DCP setting.
minimum AV voltage of 10.8V for EEPROM programming, but
DD
will work in normal operation down to 4.5V after the EEPROM
has been programmed, with no additional EEPROM writing.
SET
AVDD
AVDD
RA
R1
IDVR_OUT
DVR_OUT
AVDD
RB
VCOM
R1 = RA
R2
RC
R2 = RB+RC
RSET = RARB + RARC
20RB
VDCP
VCOM_OUT
Q1
A2
VOUT
A1
AVDD
VDD
AVDD
INN
VSAT
R1
ISL24212
VCOM
VCOM_OUT
IOUT
SET
IOUT
GND
VSET = VDCP = IOUT * RSET
RSET
DVR_OUT
SET
INN
R2
RSET
FIGURE 5. CURRENT SINK CIRCUIT
FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT
The external R
resistor sets the full-scale (maximum) sink current
that can be pulled from the DVR_OUT node. The relationship
SET
DCP (Digitally Controllable Potentiometer)
between I
and Register Value is shown in Equation 2.
DVR_OUT
The DCP controls the voltage that ultimately controls the SET
current. Figure 4 shows the relationship between the register
value and the DCP’s tap position. Note that a register value of 0
selects the first step of the resistor string. The output voltage of
the DCP is given in Equation 1:
V
AV
RegisterValue + 1
1
DCP
DD
⎛
⎝
⎞ ⎛ ⎞ ⎛
⎞
⎠
(EQ. 2)
-------------
-------------------------------------------------- -------------- ------------
I
=
=
DVROUT
⎠ ⎝
⎠ ⎝
R
SET
R
256
20
SET
AV
(EQ. 1)
RegisterValue + 1
DD
⎛
⎝
⎞ ⎛
⎞
⎠
-------------------------------------------------- --------------
V
=
DCP
⎠ ⎝
256
20
FN7590.0
March 15, 2011
6
ISL24212
The maximum value of I
DVR_OUT
substituting the maximum register value of 255 into Equation 2,
resulting in Equation 3:
can be calculated by
First, verify that our chosen R
meets the minimum
requirement described in Equation 5:
SET
15
⎛
⎜
⎜
⎜
⎝
⎛
⎜
⎜
⎜
⎝
⎞
⎟
⎟
⎟
⎠
⎞
⎟
A
------
VDD
(EQ. 3)
--------------------
16
(MAX) =
(EQ. 9)
DVROUT
------------------------------
(7.5kΩ) >
R
(MIN) =
= 0.163kΩ
⎟
⎟
⎠
20R
SET
SET
15
⎛
⎞
------
6.5V –
⎝
⎠
20
Equation 2 can also be used to calculate the unit sink current
step size per Register Code, resulting in Equation 4:
AV
Using Equations 6 and 7, calculate the values of R and R :
DD
(EQ. 4)
1
2
---------------------------------------------
=
I
STEP
(256)(20)(R
)
SET
8.5–6.5
(EQ. 10)
⎛
⎝
⎞
⎠
-------------------------------------
R
= 5120 ⋅ 7500 ⋅
= 35.4kΩ
1
2
256 ⋅ 8.5 – 6.5
Determination of R
SET
8.5 – 6.5
-----------------------------------------------------------------
⎛
⎝
⎞
(EQ. 11)
R
= 5120 ⋅ 7500 ⋅
= 46.4kΩ
The ultimate goal for the ISL24212 is to generate an adjustable
⎠
255 ⋅ 15 + 6.5 – 256 ⋅ 8.5
voltage between two endpoints, V and V , with
COM_MIN COM_MAX
a fixed power supply voltage, AV . This is accomplished by
DD
choosing the correct values for R , R and R . The exact value
Table 1 shows the resulting V
value for these conditions.
voltage as a function of register
SET
1
2
COM
of R
is not critical. Values from 1k to more than 100k will
work under most conditions. Equation 5 calculates the minimum
SET
TABLE 1. EXAMPLE V
vs REGISTER VALUE
DVR_OUT
R
value:
SET
AV
⎛
⎜
⎜
⎜
⎜
⎝
⎞
⎟
⎟
⎟
⎟
⎠
REGISTER VALUE
V
(V)
DVR_OUT
8.49
DD
--------------
(EQ. 5)
16
-----------------------------------------------------
0
R
(MIN) =
(kΩ)
SET
AV
DD
20
⎛
⎝
⎞
⎠
--------------
–
V
20
8.34
8.18
8.02
7.87
7.71
7.55
7.50
7.40
7.24
7.09
6.93
6.77
6.62
6.50
OUT(MIN)
40
Note that this is the absolute minimum value for R . Larger
SET
60
R
values reduce quiescent power, since R and R are
SET
proportional to R . The ISL24212 is tested with a 5kΩ R
1 2
.
SET
80
SET
100
120
127
140
160
180
200
220
240
255
Determination of R and R
1
2
With AV , V
and V
known and R chosen
DD COM(MIN)
COM(MAX)
SET
per the above requirements, R and R can be determined using
1
2
Equations 6 and 7:
V
– V
COM(MIN)
⎛
⎞
⎟
⎠
COM(MAX)
(EQ. 6)
--------------------------------------------------------------------------------
R
R
= 5120 ⋅ R
= 5120 ⋅ R
⎜
⎝
1
2
SET
SET
256 ⋅ V
– V
COM(MAX)
COM(MIN)
V
– V
⎛
⎜
⎝
⎞
⎟
⎠
COM(MAX)
COM(MIN)
--------------------------------------------------------------------------------------------------------------------
255 ⋅ AV
+ V
– 256 ⋅ V
COM(MIN) COM(MAX)
DD
(EQ. 7)
Final Transfer Function
The voltage at the DVR_OUT pin can be calculated from
Equation 8:
Output Voltage Span Calculation
It is also possible to calculate V
existing resistor values.
and V
from the
is drawn
COM(MIN)
COM(MAX)
occurs when the greatest current, I
DVR(MAX),
R
R
1
20R
SET
⎛
⎜
⎝
⎞ ⎛
⎟ ⎜
⎠ ⎝
⎛
⎞⎞
⎟⎟
⎠⎠
RegisterValue + 1
-------------------------------------------------- --------------------
1 –
2
--------------------
V
= AV
⎜
V
COM_MIN
DVROUT
DD
R + R
256
⎝
1
2
from the middle node of the R1/R2 divider. Substituting
RegisterValue = 255 into Equation 8 gives the following:
(EQ. 8)
R
R
1
20R
SET
With amplifier A2 in the unity-gain configuration (V
tied
⎛
⎜
⎝
⎞ ⎛
⎟ ⎜
⎠ ⎝
⎛
⎜
⎝
⎞⎞
⎟⎟
⎠⎠
(EQ. 12)
(EQ. 13)
2
COM_OUT
--------------------
--------------------
V
= AV
1 –
COM(MIN)
DD
to IN as shown in Figure 5), V
= V
= V .
R + R
N
DVROUT
COM_OUT
COM
1
2
Example
Similarly, RegisterValue = 0 for V
COM(MAX)
:
As an example, suppose the A
supply is 15V, the desired
VDD
R
R
1
⎛
⎜
⎝
⎞ ⎛
⎟ ⎜
⎠ ⎝
⎛
⎞⎞
⎟⎟
⎠⎠
1
2
V
= 6.5V and the desired V
= 8.5V. R is
--------------------
--------- --------------------
⎜
V
= AV
1 –
COM_MIN COM_MAX
SET
COM(MAX)
DD
R + R
256 20R
⎝
SET
1
2
arbitrarily chosen to be 7.5kΩ.
FN7590.0
March 15, 2011
7
ISL24212
By finding the difference of Equation 13 and Equation 12, the total
span of V can be found:
Do not remove V or AV within 100ms of the start of the
DD DD
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed, may result in
corrupted data in the EEPROM.
COM
R
R
1
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎞
⎟
⎠
1
2
⎛
⎝
⎞
--------- --------------------
⎜
(EQ. 14)
--------------------
V
SPAN = AV
1 –
COM
DD
⎠
256 20R
⎝
SET
R + R
1
2
Operating and Programming
Supply Voltage and Current
Assuming that the I
expression in Equation 14 simplifies to:
(MIN) = 0 instead of I
, the
DVROUT
STEP
To program the EEPROM, AV must be ≥10.8V. If further
R
⋅ R
R
⋅ R
1
DD
AV
⎛
⎜
⎝
⎞ ⎛
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
1
2
DD
2
-------------------- --------------------
--------------------
programming is not required, the ISL24212 will operate over an
V
SPAN =
=
I
(MAX)
DVROUT
⎟ ⎜
COM
R
+ R
20R
R + R
1 2
⎠ ⎝
2
1
SET
AV range of 4.5V to 19V.
DD
(EQ. 15)
During EEPROM programming, I and I
DD AVDD
will temporarily be
4-5x higher for up to 100ms (t
).
PROG
DVR_OUT Pin Leakage Current
When the voltage on the DVR_OUT pin is greater than 10V, an
additional leakage current flows into the pin in addition to the
Up/Down Counter Interface
The ISL24212 allows the adjustment of the output V
and the programming of the non-volatile memory through a
single pin (CTL) when the CE (counter enable) pin is high. The CTL
pin is biased so that its voltage is set to VDD/2 if the driving
circuit is set to Tristate or High Impedance (Hi-Z), allowing
up/down operation using common digital I/O logic.
I
current. Figure 6 shows the I current and the DVR_OUT
SET
SET
voltage
COM
pin current for DVR_OUT pin voltage up to 19V. In applications
where the voltage on the DVR_OUT pin will be greater than 10V,
the actual output voltage will be lower than the voltage
calculated by Equation 8 due to this extra current. The graph in
Figure 6 was measured with R
= 4.99kΩ.
SET
0.30
REGISTER = 255
CTL Pin
0.25
0.20
0.15
0.10
0.05
0.00
When a mid-high-mid transition is detected on the CTL pin (see
Figure 11), the internal register value counts down by one at the
OUT PIN CURRENT
trailing (high-mid) edge, and the output V
voltage is
COM
increased according to Equation 8. Similarly, when a mid-low-mid
transition is detected on the CTL pin, the internal register value
counts up by one at the trailing (low-mid) edge, and the output
SET PIN CURRENT
V
voltage is decreased. Once the maximum or minimum
COM
value is reached, the counter saturates and will not overflow or
underflow beyond those values.
CTL should have a noise filter to reduce bouncing or noise on the
input that could cause unwanted counts when the CE pin is high.
Figure 8 shows a simple debouncing circuit consisting of a series
1kΩ resistor and a shunt 0.01µF capacitor connected on the CTL
pin. To avoid unintentional adjustment, the ISL24212 guarantees
to reject CTL pulses shorter than 20µs.
0
2
4
6
8
10
12
14
16
18
20
OUT PIN VOLTAGE (V)
FIGURE 6. DVR_OUT PIN LEAKAGE CURRENT
AV
DD
Power Supply Sequence
CLOSE TO
PROGRAM
EEPROM
The recommended power supply sequencing is shown in
Figure 7. When applying power, V should be applied before or
DD
at the same time as AV . The minimum time for t is 0µs.
DD VS
ISL24212
CTL
1kΩ
When removing power, the sequence of V and AV is not
DD DD
important.
0.01µF
VDD
FIGURE 8. EXTERNAL DEBOUNCER ON CTL PIN
This pin is pulled above 4.9V to program the EEPROM. See
“Programming the EEPROM” on page 9 for details.
AVDD
tVS
After CE (Counter Enable) is asserted and after programming
EEPROM, the very first CTL pulse is ignored (see Figure 11) to
avoid the possibility of a false count (CTL state may be unknown
after programming).
FIGURE 7. POWER SUPPLY SEQUENCE
FN7590.0
March 15, 2011
8
ISL24212
1. Power-up the ISL24212. The EEPROM value will be loaded.
CE Pin
2. Set the CE pin to V
.
DD
To change the counter controlling the output voltage, the CE
(Counter Enable) pin must be pulled high (V ). When the CE pin
3. Change the V
OUT
voltage using the CTL pin to the desired
DD
is pulled low, the counter value is loaded from EEPROM, which
takes 10ms (during which the inputs should remain constant).
The CE pin has an internal pull-down to keep it at a logic low
when not being driven. CE should be pulled low before powering
the device down to ensure that any glitches or transients during
power-down will not cause unwanted EEPROM overwriting.
value, noting that first pulse will be ignored.
4. Pull the CTL pin to 4.9V or higher for at least 200µs. The
counter value will be written to EEPROM after 100ms.
5. Change the V
OUT
value (using the CTL pin) to a different value,
noting that first pulse after programming will be ignored.
6. Set the CE pin to 0V. The stored output value will be loaded
from EEPROM after 10ms.
The CE pin has a Schmitt trigger on the input to prevent false
triggering during slow transitions of the CE pin. The CE pin
transition time should be 10µs or less.
7. Verify that the output value is the same value programmed in
Step 4.
The CTL pin should be left floating after programming. The
Programming the EEPROM
voltage at the CTL pin will be internally biased to V /2 to ensure
DD
To program the non-volatile EEPROM, pull the CTL pin above 4.9V
for more than 200µs. The level and timing is shown in Figure 9. It
then takes a maximum of 100ms after CTL crosses 4.9V for the
programming to be completed inside the device.
that no additional pulses will be seen by the Up/Down counter. To
prevent further changes, ground the CE pin.
Typical Application Circuit
Shown below in Figure 10 is a typical circuit that can be used to
program the ISL24212 via the up/down counter interface. Three
momentary push-button switches are required. SW1 connected
CTL VOLTAGE
EEPROM
>200µs
OPERATION
COMPLETE
4.9V
between CTL and AV allows the user to bring CTL above V for
100ms
DD DD
programming the EEPROM, SW2 connected to V to pull CTL up,
DD
and SW3 connected to GND to pull CTL to down. All the switches
should have 1kΩ current-limiting resistors in series.
For adjustment and programming to occur, the CE pin has to be
t
PROG
TIME
set to V . This can be achieved by a single-pull double-throw
DD
switch (SW4) connected between V and GND.
DD
FIGURE 9. EEPROM PROGRAMMING
Note that pressing the UP button increments the counter, but
When the part is programmed, the data in the counter register is
written into the EEPROM. This value will be loaded from the
EEPROM during subsequent power-ups as well as when the CE
pin is pulled low. The ISL24212 is factory-programmed to
mid-scale. As with asserting CE, the first pulse after a program
operation is ignored. The EEPROM contents can be written and
verified using the following steps:
results in V decreasing. Similarly, pressing the DOWN
COM_OUT
button decrements the counter, and results in V
increasing.
COM_OUT
AV
DD
V
DD
V
AV
DD
DD
R1
ENABLE
ADJUST /
PROGRAM
AV
V
DD
DD
0.1µF
0.1µF
SW4
1kΩ
1kΩ
R2
DISABLE
V
AV
DVR_OUT
DD
DD
SW2
CLOSE TO
PROGRAM
EEPROM
UP
CE
ISL24212
VCOM_OUT
IN
SW1
CTL
N
V
to LCD Panel
COM
GND
SET
0.01µF
DOWN
SW3
RSET
1kΩ
FIGURE 10. TYPICAL APPLICATION CIRCUIT
FN7590.0
March 15, 2011
9
ISL24212
Up/Down Counter Waveforms
The operation modes of the ISL24212 is shown in Table 2.
TABLE 2. ISL 24212 OPERATION MODES
INPUT
OUTPUT
CTL
X
CE
Lo
COUNTER
V
EEPROM
COM_OUT
No Change
X
Lo to Hi
Hi
Ignore first CTL pulse
No Change
No Change
No Change
Hi to Mid
Lo to Mid
Decrement
Increment
No Change
Increase
Decrease
No Change
Hi
Mid to >4.9V
Hi
Write Counter
Value to EEPROM
>4.9V to Mid
X
Hi
Ignore next CTL Pulse
No Change
No Change
Hi to Lo
EEPROM
Programmed
Value
Read Value
Figure 11 shows the associated waveforms.
NOTE:
FIRST PULSE AFTER
PROGRAMMING IS
IGNORED
FIRST PULSE AFTER
ASSERTING CE IS
IGNORED
AFTER COUNTER ENABLE IS ASSERTED,
THE FIRST CTL PULSE IS IGNORED
t
PROG
V
= 4.9V
PROG
t
H_REJ
t
ST
t
MTC
t
READ
CTL HIGH
CTL V /2
DD
CTL LOW
t
L_REJ
t
L_MIN
t
H_MIN
CE
DISABLE ADJUSTMENT
ENABLE ADJUSTMENT
t
L_PROP
t
H_PROP
ENABLE ADJUSTMENT
AVDD
VDD
COUNTER
OUTPUT
7A
7A
79
7B
78
7B
7A
ASSUME COUNTER
STARTS WITH VALUE 78
DEASSERTING CE
RELOADS 7B
FROM EEPROM
WRITE 7B TO
EEPROM
VCOM
EXAMPLE POST POWER-UP TIMING
FIGURE 11. COUNTER INTERFACE TIMING DIAGRAM
FN7590.0
March 15, 2011
10
ISL24212
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
FN7590.0
CHANGE
3/15/11
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL24212
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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FN7590.0
March 15, 2011
11
ISL24212
Package Outline Drawing
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
2.0 REF
8X 0.50 BSC
6
3.00
A
PIN 1
INDEX AREA
B
1
5
6
10X 0 . 30
PIN 1
INDEX AREA
3.00
1.50
0.15
(4X)
C
C
A B
0.10
0.05
M
M
10
5
10 X 0.25
4
TOP VIEW
( 2.30 )
2.30
BOTTOM VIEW
0 .80 MAX
SEE DETAIL "X"
0.10 C
C
(2.90)
SEATING PLANE
0.08 C
(1.50)
SIDE VIEW
(10 X 0.50)
5
0 . 2 REF
C
( 8X 0 .50 )
( 10X 0.25 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
Angular ±2.50°
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Compliant to JEDEC MO-229-WEED-3 except exposed pad length (2.30mm).
7.
FN7590.0
March 15, 2011
12
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