ISL25700FRUZ-T7A [INTERSIL]
Programmable Temperature Controlled MOSFET Driver; 可编程温度控制MOSFET驱动器
| 型号： | ISL25700FRUZ-T7A |
| 厂家： | 
Intersil |
| 描述： | Programmable Temperature Controlled MOSFET Driver |
| 文件： | 总18页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Programmable Temperature Controlled MOSFET Driver
ISL25700
Features
2
• User-programmable Setpoint via I C Serial Interface
• Setpoint Temperature Range from +40°C to +110°C
• Operational Temperature Range from -40°C to +125°C
• 3°C Initial Setpoint Accuracy
The Temperature Controlled MOSFET Driver is a highly
integrated solution that combines a MOSFET driver with
overcurrent protection and two 8-bit resolution DACs on
a monolithic CMOS integrated circuit (IC).
The ISL25700 sets up and monitors temperature at the
point of interest, compares it with the user programmable
setpoint, and adjusts the output until the set temperature is
reached. An external power MOSFET, a heater, an NTC
thermistor and the ISL25700 are parts of the temperature
control loop.
• Coarse and Fine Tuning Setpoint Control
- +15°C Coarse Adjustment
- +0.1°C Fine Adjustment
• ±0.5°C Long-term Drift Error
• Programmable Current Protection of External MOSFET
• 5-bit Selectable Gain Control
It also features programmable overcurrent protection of
the MOSFET. The current protection automatically adjusts
the output voltage in order to keep MOSFET power under
user defined limits. The protection settings always
override the temperature settings that cause violation of
the current limit.
• Wide Power Supply Range: 3V to 15V
• Works with 20kΩ to 200kΩ External NTC Thermistor
• General Purpose 8-bit DAC - 0.4% Output Resolution
• High Reliability
There is an additional 8-bit General Purpose DAC that is
available for application specific use.
- Endurance: 10,000 Data Changes per Bit per Register
- Register Data Retention: 10 years @ T ≤ +125°C
The ISL25700 can be used in a variety of applications
where constant temperature is a key parameter.
• 10 Lead μTQFN 2.1mmx1.6mm Package
• Pb-free (RoHS Compliant)
Applications*(see page 17)
• Oven Controlled Applications with Micro Temperature
Chamber in:
- Basestations
- Spectrometers
- Precision Meters
- Precision Generators
100
80
60
40
20
0
0
3
6
9
12
15
TIME (MINUTES)
FIGURE 1. TYPICAL TEMPERATURE SETTLING TIME
September 3, 2010
FN6885.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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1
ISL25700
Block Diagram/Application Circuit
FN6885.0
September 3, 2010
2
ISL25700
Pin Configuration
ISL25700
(10 LD μTQFN)
TOP VIEW
NC
O
VDD
CCOMP
9
1
2
3
4
8
7
6
SCL
SDA
GND
ISENSE
VOUT
VDAC
R
TH
Pin Descriptions
μTQFN PIN
SYMBOL
DESCRIPTION
1
2
VDD
Power supply. This pins supplies the power necessary to operate the chip.
2
2
SCL
I C interface input clock. This input is the serial clock of the I C serial interface.
SCL requires an external pull-up resistor. It has an internal pull-down resistor of ~3MΩ to
prevent a floating input if the pin will be left unconnected.
2
3
SDA
Open Drain Serial Data Input/Output for the I C interface. The SDA is a bidirectional serial
2
data input/output pin for I C interface. It receives device address, operation code and data
from an I C external master device at the rising edge of the serial clock SCL, and it shifts out
2
data after each falling edge of the serial clock.
The SDA pin requires an external pull-up resistor. It has an internal pull-down resistor of
~3MΩ to prevent a floating input if the pin will be left unconnected.
4
5
GND
Ground. Bias and reference ground of the chip.
R
External NTC thermistor. An external NTC thermistor makes one shoulder of the Wheatstone
TH
bridge and must be connected between the R
pin and GND.
TH
6
VDAC
DAC Output. This is the output of the precision 8-bit DAC. Default DAC output is in the range
of 0V to 2V. The DAC output range can be extended with a gain of 2 by setting the DAC Gain
bit.
7
8
VOUT
Output voltage that controls an external P-MOSFET. This pin drives an external P-MOSFET
proportional to unbalanced condition of the Wheatstone bridge.
ISENSE
Current Sense input. This pin monitors voltage drop over an external current sense resistor
RSENSE. Power dissipation of the P-MOSFET will be limited when ISENSE exceeds the voltage
drop limit set in the Current Sense Register.
9
CCOMP
NC
Compensation capacitor. A compensation ceramic capacitor must be added between CCOMP
and GND to increase chip stability. This capacitor provides a negative feedback for the
operational amplifier and its value can be from 30pF to 1000pF.
10
Not internally connected.
FN6885.0
September 3, 2010
3
ISL25700
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
UNITS
PER REEL
TEMP RANGE
PACKAGE
(Pb-free)
PKG.
DWG. #
(°C)
ISL25700FRUZ-T
GT
GT
GT
3000
-40 to +125
-40 to +125
-40 to +125
10 Ld 2.1x1.6 μTQFN L10.2.1x1.6A
10 Ld 2.1x1.6 μTQFN L10.2.1x1.6A
10 Ld 2.1x1.6 μTQFN L10.2.1x1.6A
ISL25700FRUZ-TK
ISL25700FRUZ-T7A
NOTES:
1000
250
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL25700. For more information on MSL please
see techbrief TB363.
FN6885.0
September 3, 2010
4
ISL25700
Absolute Maximum Ratings
Thermal Information
Voltage at any Digital Interface Pin
with respect to GND. . . . . . . . . . . . . . . . . . . .-0.3V to 6V
Thermal Resistance (Typical)
θ
JA (°C/W) θJC (°C/W)
135 75
10 Ld μTQFN Package (Note 4, 5) .
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16.5V
DD
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C
Maximum Junction Temperature (Plastic Package) . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . 5kV
Machine Model (Tested per JESD22-A115B) . . . . . . . 200V
Latchup. . . . . . . . . . . . . . . . . . .Class II, Level A at +125°C
Recommended Operating Conditions
Temperature Range (Full-range Industrial) . . . . -40°C to +125°C
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 15V
DD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. For θ the “case temp” location is the center on the top of package.
JC
Analog Specifications Over recommended operating conditions unless otherwise stated. Boldface limits apply over
the operating temperature range, -40°C to +125°C.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 13) (Note 6) (Note 13) UNITS
T
Temperature Set Point
T
must be above
MIN
MAX
40
110
±3
15
°C
°C
°C
°C
SET
SET
ambient
Temperature Set Point Accuracy 3 sigma standard deviation
T
Coarse Adjustment of Set Point
Fine Adjustment of Set Point
R
B
= 100k @ +25°C,
TH
SET_COARSE
= 4100k (Note 14)
25/85
T
0.1
°C
SET_FINE
T
Fine Control Integral
Non-linearity
-2.5
-2
±0.9
+2.5
+2
LSB
(Note 7)
SET_FINE_INL
(Note 9)
T
Fine Control Differential
Non-linearity
±0.5
±0.5
LSB
(Note 7)
SET_FINE_DNL
(Note 8)
T
Long-term Drift of Set Point
1000h, Reg.1 = x2h, Reg.2 = 80h,
Reg.3 = 90h
°C
DRIFT
I
Thermistor Current Range
NTC Thermistor Range
25
20
40
55
μA
kΩ
V
TH
R
Resistance @ +25°C
100
200
TH
V
External P-MOSFET Gate Voltage I
= 0μA
= 0μA
0.25
V
DD
OUT
OUT
V
Swing @ Fixed V
DD
I
MIN
V
- 2.5
V
OUT
Output Current
Overcurrent Protection Set Point V
OUT
DD
I
7
μA
mV
OUT
V
= I x R
;
200 to 1750
SENSE
SENSE SENSE SENSE
see Table 3
GENERAL PURPOSE DAC (MEASUREMENTS BETWEEN GND AND VDAC)
V
Maximum DAC Output
Using internal V
load, Gain = 1
, V
REF DD
≤ 5V, No
2
2.5
V
V
DAC MAX
V
> 5V, No load, Gain = 2
4
5.0
+1
DD
INL
Integral Non-Linearity
No load
-1
±0.4
LSB
(Note 9)
(Note 7)
DNL
Differential Non-linearity
No load
-0.75
±0.3
+0.75
LSB
(Note 8)
(Note 7)
FN6885.0
September 3, 2010
5
ISL25700
Analog Specifications Over recommended operating conditions unless otherwise stated. Boldface limits apply over
the operating temperature range, -40°C to +125°C. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 13) (Note 6) (Note 13) UNITS
V
Offset
DAC register set to 0, No load
0
0.2
1
LSB
(Note 7)
DAC_OFFSET
R
DAC Output Impedance
350
-85
Ω
OUT
PSRR
Power Supply Rejection Ratio DAC at middle scale, frequency
from 0Hz to 25kHz
dB
TC
Temperature Coefficient
DAC register set between 20 hex
and FF hex
±45
ppm/°C
V
(Notes 10,
11)
Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits
apply over the operating temperature range, -40°C to +125°C.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 13) (Note 6) (Note 13) UNITS
I
V
Supply Current
f
SCL
= 400kHz; SDA = Open;
2
4
mA
DD1
DD
(Non-Volatile Write/read)
(for I C, Active, Read and Write
States) I
= 0mA, DAC unload
PMOS
= 0mA, DAC unload
PMOS
I
V
Supply Current
I
2.8
2
mA
μA
μs
V
DD2
DD
(Volatile Write/read)
I
Leakage Current, at SDA and Voltage at pin from GND to VCC
SCL Pins
-2
LkgDig
t
DAC Settling Time
From bus STOP condition to V
change
3
DAC
(Note 11)
DAC
V
Power-On Recall Voltage
Minimum V at which memory recall
DD
2.5
2.9
POR
occurs
V
Ramp V
Ramp Rate
@ any level from 0V to 15V
0.2
50
1
V/ms
ms
DD
DD
Power-Up Delay
t
V
above V
, to DAC Register recall
2
D
DD POR
(Note 11)
completed, and I C Interface in
standby state
EEPROM SPECIFICATIONS
EEPROM Endurance
10,000
50
Cycles
Years
Years
EEPROM Retention
Temperature ≤ +55°C
Temperature ≤ +125°C
10
SERIAL INTERFACE SPECIFICATIONS
2
V
I C Bus Voltage
V
V
≤ V
DD
2.7
1.4
5.5
0.8
V
V
I2C
I2C
V
SDA, and SCL Input Buffer
LOW Voltage
from 2.7V to 5.5V
IL
I2C
V
SDA, and SCL Input Buffer
HIGH Voltage
V
from 2.7V to 5.5V
V
V
IH
I2C
Hysteresis SDA and SCL Input Buffer
(Note 11) Hysteresis
0.05*V
0
I2C
V
SDA Output Buffer LOW
(Note 11) Voltage, Sinking 4mA
0.4
10
V
OL
Cpin
SDA, and SCL Pin Capacitance
pF
(Note 11)
f
SCL Frequency
Pulse Width Suppression Time Any pulse narrower than the max spec
400
50
kHz
ns
SCL
t
IN
(Note 11) at SDA and SCL Inputs
is suppressed
FN6885.0
September 3, 2010
6
ISL25700
Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits
apply over the operating temperature range, -40°C to +125°C. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 13) (Note 6) (Note 13) UNITS
t
SCL Falling Edge to SDA
SCL falling edge crossing 30% of V
,
900
ns
ns
AA
I2C
(Note 11) Output Data Valid
until SDA exits the 30% to 70% of
window
V
I2C
SDA crossing 70% of V
t
Time the Bus Must be Free
during a
1300
BUF
I2C
STOP condition, to SDA crossing 70%
of V during the following START
(Note 11) Before the Start of a New
Transmission
I2C
condition
t
Clock LOW Time
Measured at the 30% of V
Measured at the 70% of V
crossing
crossing
1300
600
ns
ns
ns
LOW
I2C
t
Clock HIGH Time
HIGH
I2C
t
START Condition Setup Time
SCL rising edge to SDA falling edge.
Both crossing 70% of V
600
SU:STA
.
I2C
From SDA falling edge crossing 30%
of V to SCL falling edge crossing
t
t
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
600
100
0
ns
ns
ns
ns
ns
HD:STA
I2C
70% of V
I2C
From SDA exiting the 30% to 70% of
window, to SCL rising edge
SU:DAT
V
I2C
crossing 30% of V
I2C
From SCL falling edge crossing 70% of
to SDA entering the 30% to 70%
t
HD:DAT
V
I2C
of V
window
I2C
t
STOP Condition Setup Time
Output Data Hold Time
From SCL rising edge crossing 70% of
600
0
SU:STO
V
, to SDA rising edge crossing 30%
I2C
I2C
of V
t
From SCL falling edge crossing 30% of
DH
V
, until SDA enters the 30% to
I2C
70% of V
window
I2C
t
SDA and SCL Rise Time
SDA and SCL Fall Time
From 30% to 70% of V
20 +
0.1 * Cb
250
250
400
ns
ns
R
I2C
I2C
t
From 70% to 30% of V
20 +
0.1 * Cb
F
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
SDA and SCL Bus Pull-Up Maximum is determined by t and t .
10
1
pF
Rpu
kΩ
R
F
(Note 11) Resistor Off-Chip
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
t
Non-Volatile Write Cycle Time
15
20
ms
WC
(Notes
11, 12)
NOTES:
6. Typical values are for T = +25°C and 12V supply voltage.
A
7. LSB: [VDAC
255
– VDAC ]/255. VDAC and VDAC are the DAC output voltage when DAC register set to FF hex and 00 hex
255 0
0
respectively.
8. DNL = [VDAC – VDAC ]/LSB-1, for i = 1 to 255. i is the DAC register setting.
i
i-1
9. INL = [VDAC – (i • LSB + VDAC )]/LSB for i = 1 to 255.
i
0
VDAC (T) – VDAC (40°C)
6
10
i
i
TC = ------------------------------------------------------------------------ × ---------------------------
V
VDAC (40°C)
(T – 40)°C
for i = 1 to 255 decimal, T = -40°C to +125°C, referenced to 40°C.
10.
11. Limits established by characterization and are not production tested.
12. t is the time from a valid STOP condition at the end of a Write sequence of a I C serial interface Write operation, to the
i
2
WC
end of the self-timed internal non-volatile write cycle. The Busy Polling method can be used to determine the end of the
non-volatile write cycle.
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
14. B
25/85
is a thermistor material specific constant; represents the slope of the Resistance vs. Temperature curve.
FN6885.0
September 3, 2010
7
ISL25700
SDA vs SCL Timing
t
t
t
t
R
t
F
HIGH
LOW
WC
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA
(INPUT TIMING)
t
t
t
BUF
AA
DH
SDA
(OUTPUT TIMING)
Typical Performance Curves
2.5
V
= 12V
V
= 15V
DD
DD
MEASURED AT RT PIN
2.0
1.5
1.0
0.5
0.0
C
= 10nF
COMP
15
10
AFTER 10 MIN SETTLING TIME
MARKER = 14.6μV/√Hz
V
= 5V
40
DD
V
= 3V
DD
5
-40
-20
0
20
60
80
100 120
0
0.1
TEMPERATURE (°C)
1.0
10
100
FREQUENCY (Hz)
FIGURE 2. SUPPLY CURRENT I
vs V
FIGURE 3. NOISE LEVEL AT R INPUT IN CLOSE LOOP
TH
DD
DD
APPLICATION 2μV/√Hz @ 1Hz
V
= 12V
DD
V
OUT
V
DAC
0.5ms/DIVISION
0.5μs/DIVISION
FIGURE 5. GP DAC SETTLING TIME (FULL SCALE,
GAIN = 2)
FIGURE 4. V
POWER UP DELAY
OUT
FN6885.0
September 3, 2010
8
ISL25700
Typical Performance Curves (Continued)
0.2
0.2
0.1
GAIN = 1
GAIN = 1
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
GAIN = 2
0
50
100
150
200
250
0
50
100
150
200
250
CODE (DECIMAL)
CODE (DECIMAL)
FIGURE 7. GP DAC DNL vs CODE V
= 5V
FIGURE 6. GP DAC DNL vs CODE V
= 3V
DD
DD
0.2
0.5
GAIN = 1
GAIN = 1
0.1
0
0.3
0.1
-0.1
-0.2
-0.3
-0.1
-0.3
-0.5
GAIN = 2
0
50
100
150
200
250
0
50
100
150
200
250
CODE (DECIMAL)
CODE (DECIMAL)
FIGURE 8. GP DAC DNL vs CODE V
= 15V
FIGURE 9. GP DAC INL vs CODE V
= 3V
DD
DD
0.5
0.5
0.3
0.1
0.3
0.1
GAIN = 1
GAIN = 1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
GAIN = 2
GAIN = 2
200
0
50
100
150
250
0
50
100
150
200
250
CODE (DECIMAL)
CODE (DECIMAL)
FIGURE 11. GP DAC INL vs CODE V
= 15V
FIGURE 10. GP DAC INL vs CODE V
= 5V
DD
DD
FN6885.0
September 3, 2010
9
ISL25700
Typical Performance Curves (Continued)
0.5
0.3
0.1
V
= 15V
V
= 5V
DD
DD
-0.1
-0.3
-0.5
5
55
105
155
205
255
CODE (DECIMAL)
FIGURE 12. GP DAC GAIN ERROR
The internal current sensing circuitry provides the
ability to control and adjust the power dissipated in the
P-MOSFET through the Current Sense Register,
Reg.01h[7:3]. This function allows for adjusting the
initial turn on heating curve and protects from
over-heating of the P-MOSFET. An external current
Principles of Operation
The ISL25700 allows for precisely controlling the
temperature of an external object and/or power
dissipation of the external P-MOSFET. The temperature
control is done by continuously sensing resistance of
the NTC thermistor, and adjusting the current flow
through the P-MOSFET (temperature controlling
element).
sensing resistor R
, serial with the P-MOSFET, is
SENSE
required. A current limit can be selected for the chosen
. It should have an effective voltage drop from
R
SENSE
200mV to 1750mV and be inside the safe operating
area of the MOSFET.
ISL25700 drives the P-MOSFET proportionally inverted
to the difference between the object temperature and
target temperature set point (T
), set by the user
SET
A General Purpose 8-bit DAC, GP DAC provides a
2
through the I C serial interface. Temperature is sensed
by the external NTC thermistor and converted to a
driving voltage by the Wheatstone bridge and its
amplifier. One leg of the current-mode Wheatstone
bridge contains an external NTC thermistor with the
programmable 8-bit FTC DAC and another leg contains
the selectable current source K1 that feeds an internal
programmable voltage output V
through the General
DAC
Purpose DAC Register, Reg.04h[7:0]. The output swing of
General Purpose DAC can be set through the Gain
Control bit in Reg.03h[6] or totally disabled by resetting
the DAC Enable Bit in Reg.03h[7].
Memory Map
resistor R
.
INT
The are two types of memory banks in the chip;
volatile (RAM) and non-volatile (EEPROM). Volatile
registers from address 00h to 07h are identical to
non-volatile registers in terms of the register’s name
and bit definitions. All the data is recalled from
non-volatile registers and maintained in the volatile
registers at power-up. It is possible to do independent
write/read to the volatile and non-volatile banks after
power-up by setting NV bit in the Control/Status
Register, Reg.08h[7]. Note that the data written to the
non-volatile registers will be automatically written to
corresponding volatile registers, however no direct
reading from non-volatile registers is possible. All the
readings are from corresponding volatile registers.
The 8-bit FTC DAC allows fine-tuning the T
SET
resolution better than +0.1°C within a +15°C coarse
temperature range window. The T temperature is set
through the Temperature Coarse Range Control Register,
Reg.01h[2:0], and the Fine Temperature Control
Register, Reg.02h[7:0]; refer to “ISL25700 MEMORY
MAP” on page 11. A +15°C temperature coarse range
with
SET
window can be centered on T
point based on the
SET
thermistor’s parameters, such as resistance, R/T curve
type, tolerance and NTC slope and by adjusting a current
ratio flowing through the legs of the Wheatstone bridge.
Note that the T
target temperature should be higher
SET
than the anticipated maximum ambient temperature for
the application.
The Memory Map of the chip is in Table 1.
There are total of 32 system gain settings available in
the Gain Control Register, Reg.03h[4:0], with 0.35dB
resolution per step. The gain control allows to prevent
the thermal system from oscillation by adjusting the
total system gain remotely, without use of external
components.
FN6885.0
September 3, 2010
10
ISL25700
TABLE 1. ISL25700 MEMORY MAP
BIT MAP
REGISTER
DEFAULT
REGISTER NAME
ADDRESS
7
6
5
4
3
2
1
0
SETTINGS
Device ID (Read Only)
00h
ID[7]
ID[6]
ID[5]
ID[4]
ID[3]
ID[2]
ID[1]
ID[0]
00h
03h
Current Sense/
01h
CS[4] CS[3] CS[2] CS[1] CS[0] CTC[2] CTC[1] CTC[0]
Coarse Temperature Control
Fine Temperature Control
02h
03h
FTC[7] FTC[6] FTC[5] FTC[4] FTC[3] FTC[2] FTC[1] FTC[0]
80h
90h
Gain Control (DAC Enable/
DAC
DAC
NA
SLG[4] SLG[3] SLG[2] SLG[1] SLG[0]
DAC Gain/System Loop Gain)
Enable Gain
General Purpose DAC
04h
05h
06h
07h
08h
DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]
GP1[7] GP1[6] GP1[5] GP1[4] GP1[3] GP1[2] GP1[1] GP1[0]
GP2[7] GP2[6] GP2[5] GP2[4] GP2[3] GP2[2] GP2[1] GP2[0]
sign bit ERR[6] ERR[5] ERR[4] ERR[3] ERR[2] ERR[1] ERR[0]
80h
00h
00h
XX
General Purpose Register 1
General Purpose Register 2
R
Absolute Error (Read Only)
INT
Control/Status Register
(Volatile Only)
NV
NA
NA
NA
NA
NA
NA
BUSY
00h
error stored in Reg.07h[7:0] converted to a decimal
number; bit [7] represents a sign bit, 0 for “+” and 1 for
“-”;
α= –1337×10 - 1st order temperature coefficient,
ppm/°C;
Device ID Register (Reg.00h)
This is a read only register. It contains device ID code 00h.
–6
Coarse Temperature Control (Reg.01h [2:0])
These 3 bits allow one to choose one of the seven coarse
windows for the temperature set point. The default set
–6
β= 5×10
- 2nd order temperature coefficient,
2
point is about +59°C for the 100k R
thermistor with a
TH
ppm/°C ;
temperature coefficient of -4.25%/°C at +25°C, i.e.
Reg.01h[2:0] = 011b. The temperature set point can be
changed to any other set point within an operational
range from +40°C to +110°C, or use another type of
thermistor, including different resistance value or R/T
curve type (NTC slope), and then center the +15°C
coarse range temperature window on that new setting
T - temperature in Celsius.
The K1, K2 and K3 coefficients and the thermistor value
range for each Coarse Temperature setting in
Reg.01h[2:0] should be taken according to Table 2.
TABLE 2. COARSE TEMPERATURE RANGE
based on the ratio of R
/R according to Equation 1:
INT TH
THERMISTOR
RESISTANCE RANGE
AT SET POINT (kΩ)
Code
Register
01h[2:0]
K2 + K3 × ---------------
R
(T)
(EQ. 1)
255
INT
K1
K2
K3
---------------------------------------- = -------------------------------------------
R
(setpoint) K1
TH
000
001
010
100
011
101
110
111
Do not use
where:
- is an internal 9kΩ resistor, forming another leg of
3
4
3
3
3
3
3
3
3
2
2
2
2
2
2
2
5.4 to 9.0
7.2 to 12.0
9.0 to 15.0
12.6 to 21.0
14.4 to 24.0
16.2 to 27.0
21.6 to 36.0
R
INT
the Wheatstone Bridge;
5
K1, K2 and K3 - are coefficients representing the ratio of
the current flowing through the legs of the Wheatstone
Bridge;
7
8
Code - is the decimal code in the Fine Temperature
Control register 02h.
9
12
The value of internal resistor R
can vary from part to
part and depends on the package temperature. The
INT
Current Sense Threshold (Reg.01h [7:3])
This register sets the current limit trip point. When the
actual R
Equation 2:
at temperature T can be calculated using
INT
voltage applied to the I
programmed voltage threshold, V
forming a negative feedback loop proportional to I
pin falls below the
goes high, thus
SENSE
2
(EQ. 2)
R
(T) = R
(25)x[1 + α(T – 25) + β(T – 25) ]
INT
INT
OUT
SENSE
where:
x R
.
SENSE
R
(25) = 9000 + R
abs. error x 15 - is internal
INT INT
resistor value at +25°C in Ohms;
The value for this register should be taken according to
Table 3.
R
abs. error - is a signed integer value of absolute
INT
FN6885.0
September 3, 2010
11
ISL25700
System Loop Gain (Reg.03h [4:0])
TABLE 3. CURRENT SENSE THRESHOLD
This 5 bits allow one to adjust a total system loop gain in
±0.35dB per step, according to Table 4.
SENSE RESISTOR
VOLTAGE DROP
THRESHOLD
TYPICAL ERROR (%)
Register
01h[7:3]
Value
The default system loop gain depends on the MOSFET
type, thermal conductivity and level of insulation from
the ambient temperature.
V
- (I
X R
) V
= 3V V
= 15V
DD
SENSE
SENSE
DD
DD
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
V
- 200mV
- 250mV
- 300mV
- 350mV
- 400mV
- 450mV
- 500mV
- 550mV
- 600mV
- 650mV
- 700mV
- 750mV
- 800mV
- 850mV
- 900mV
- 950mV
- 1000mV
- 1050mV
- 1100mV
- 1150mV
- 1200mV
- 1250mV
- 1300mV
- 1350mV
- 1400mV
- 1450mV
- 1500mV
- 1550mV
- 1600mV
- 1650mV
- 1700mV
- 1750mV
±5
+20
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
±5
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
+20
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
TABLE 4. SYSTEM LOOP GAIN ADJUSTMENT
LOOP GAIN ADJUSTMENT
Reg.03h[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
(dB)
-5.60
-5.25
-4.90
-4.55
-4.20
-3.85
-3.50
-3.15
-2.80
-2.45
-2.10
-1.75
-1.40
-1.05
-0.70
-0.35
Initial Gain (default)
0.35
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
0.70
1.05
1.40
1.75
2.10
2.45
2.80
3.15
3.50
3.85
4.20
Fine Temperature Control Register
(Reg.02h [7:0])
4.55
4.90
This register allows fine tuning to the final temperature
within the predetermined range set in Reg.01h[2:0]
T
5.25
SET
by choosing appropriate code for the 8-bit FTC DAC. The
final temperature can be adjusted with approximately
+0.07°C increment/decrement resolution per step.
FN6885.0
September 3, 2010
12
ISL25700
DAC Enable and Gain Control (Reg.03h [7:6])
Protocol Conventions
When the DAC Enable bit, Reg.03h[7], is 0, the DAC output
is disabled, regardless of Reg.04h settings. When DAC
Enable bit is 1, the DAC output depends on the settings of
the DAC Gain bit Reg.03[6] and Reg.04h[7:0].
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 13). On power-up of the ISL25700, the SDA pin is
in the input mode.
When the DAC Gain bit, Reg.03h[6], is 0, the DAC output
range is from 0V to 2V, i.e. Gain = 1. When the DAC Gain
bit is 1, the DAC output range is from 0V to 4V, i.e.
Gain = 2.
2
All I C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The ISL25700 continuously monitors
the SDA and SCL lines for the START condition and does
not respond to any command until this condition is met
(see Figure 13). A START condition is ignored during the
power-up sequence and during internal non-volatile write
cycles.
General Purpose DAC Register (Reg.04h [7:0])
This 8-bit register writes directly to the GP DAC to set the
output voltage. The default setting of this register is 80h.
The DAC output depends on the Gain setting in Reg.03h[6].
2
General Purpose Registers (Reg.05h and
Reg.06h)
These 8-bit General Purpose non-volatile and volatile
registers can be used for application specific purposes.
For example, they can be used to store calibration data
or other valuable system information.
All I C interface operations must be terminated by a
STOP condition, which is a LOW to HIGH transition of
SDA while SCL is HIGH (see Figure 13). A STOP condition
at the end of a read operation, or at the end of a write
operation to volatile bytes, only places the device in its
standby mode. A STOP condition during a write operation
to a non-volatile byte initiates an internal non-volatile
write cycle. The device enters its standby state when the
internal non-volatile write cycle is completed.
R
Absolute Error Register (Reg.07h [7:0])
INT
This register contains the difference between the nominal
value and the real value of the internal resistor R . The
INT
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting
device, either master or slave, releases the SDA bus
after transmitting 8 bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the 8 bits of data (see Figure 14).
nominal value of this resistor is 9k and the voltage drop
on this resistor represents the temperature setpoint. The
LSB weight of the R
Equation 2 for calculation of R
absolute error is 15Ω. Refer to
INT
.
INT
Control/Status Register (Reg.08h [7:0])
The setting of the NV bit, Reg.08h[7], determines if data
is to be read or written to the non-volatile and/or volatile
memory. When this bit is 0, all operation will be targeted
to non-volatile memory, and the data will be copied to
volatile memory simultaneously. When this bit is 1, all
operation will be targeted to the volatile memory only.
The default setting of the NV bit is 0.
The ISL25700 responds with an ACK after recognition of
a START condition, followed by a valid Identification Byte,
and once again after successful receipt of an Address
Byte. The ISL25700 also responds with an ACK after
receiving a Data Byte of a write operation. The master
must respond with an ACK after receiving a Data Byte of
a read operation.
The Busy bit, Reg.08h[0], is a read only bit. When “1” is
read from this bit, it indicates that the non-volatile cycle
is in progress. Reading from this bit eliminates getting a
NACK if the host attempts to write to the non-volatile
memory before the previous data is stored.
A valid Identification Byte contains 0101000 in seven MSBs.
The LSB is the Read/Write bit. Its value is “1” for a Read
operation and “0” for a Write operation (see Table 5).
TABLE 5. IDENTIFICATION BYTE FORMAT
0
1
0
1
0
0
0
R/W
2
I C Serial Interface
(MSB)
(LSB)
The ISL25700 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master always initiates data transfers and provides the
clock for both transmit and receive operations.
Therefore, the ISL25700 operates as a slave device in all
applications.
2
All communication over the I C interface is conducted by
sending the MSB of each byte of data first.
FN6885.0
September 3, 2010
13
ISL25700
SCL
SDA
START
DATA
DATA
DATA
STOP
STABLE CHANGE STABLE
FIGURE 13. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT
FROM RECEIVER
START
ACK
FIGURE 14. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
S
SIGNALS
FROM THE
MASTER
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
SIGNAL AT
SDA
0 1 0 1
0 0 0 0
0 0 0 0
SIGNALS
FROM THE
ISL25700
A
C
K
A
C
K
A
C
K
FIGURE 15. BYTE WRITE SEQUENCE
READ
S
S
SIGNALS
FROM THE
MASTER
T
A
R
T
T
S
T
O
P
A
C
K
A
C
K
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0
IDENTIFICATIO
N BYTE WITH
R/W = 1
ADDRESS
BYTE
SIGNAL AT
SDA
0 1 0 1 0 0 0 0
0 0 0 0
0 1 0 1 0 0 0 1
A
C
K
A
C
K
A
C
K
SIGNALS
FROM THE
SLAVE
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 16. READ SEQUENCE
FN6885.0
September 3, 2010
14
ISL25700
point should be in the middle of the coarse range.
Note, the coarse ranges overlap.
Write Operation
A Write operation requires a START condition, followed by
a valid Identification Byte, a valid Address Byte, a Data
Byte, and a STOP condition. After each of the three
bytes, the ISL25700 responds with an ACK. At this time,
if the Data Byte is to be written only to volatile registers,
then the device enters its standby state. If the Data Byte
is to be written also to non-volatile memory, the
3. Set the Current Sense limit in Reg.01h[7:3] and
System Loop Gain in Reg. 03h[4:0] as high as
possible to enable fast settling yet prevent thermal
oscillation.
4. Perform system calibration and fine tuning using an
external temperature sensor.
ISL25700 begins its internal write cycle to non-volatile
memory. During the internal non-volatile write cycle, the
device ignores transitions at the SDA and SCL pins, and
the SDA output is at a high impedance state. When the
internal non-volatile write cycle is completed, the
ISL25700 enters its standby state (see Figure 14).
Thermistor Selection
Chose the thermistor whose resistance at the desired
temperature set point T
will be within the range
SET
specified in Table 2. The R/T characteristics of the
thermistor are usually provided by the manufacturer as a
table or as a curve.
The byte at address 08h determines if the Data Byte is to
be written to volatile and/or non-volatile memory (see
“Memory Map” on page 10). A 20ms delay is required
between two consecutive writes to the non-volatile
registers.
For example, you are going to stabilize the temperature
at T
= +91.5°C. You decided to use a 100k NTC
SET
thermistor from Vishay, NTCS0805E3104FXT. The
resistance at +91.5°C will be 8109.12Ω, according to the
manufacturer data provided online at
Polling Method
http://www.vishay.com/doc?29100. This resistance fits
in the coarse temperature range settings of 001b or
002b, as per Table 2.
It is possible to check if the non-volatile memory write
cycle is finished or is in progress by polling (reading) the
BUSY bit in Control/Status Register, Reg.08h[0] (see
“Control/Status Register (Reg.08h [7:0])” on page 13).
The non-volatile write cycle is in progress when the BUSY
bit is 1. No other write attempt is allowed when the BUSY
bit is 1. The non-volatile write cycle is finished when the
BUSY bit is 0.
Current Sense Resistor and MOSFET Selection
The current sense resistor should be selected with
consideration of system maximum power consumption,
maximum current, and minimum resolution. It is
recommended to select a current sense resistor in the
range from 0.1Ω to 10Ω. The 0.1Ω resistor allows
sensing and will limit the maximum current from 2A to
17.5A, while a 10Ω resistor allows selecting a current
limit from 20mA to 175mA. The type and size of current
sense resistor should have an appropriate power rating.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 16). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
bit set to “0”, an Address Byte, a second START, and a
second Identification byte with the R/W bit set to “1”.
After each of the three bytes, the ISL25700 responds
with an ACK. Then the ISL25700 then transmits the Data
Byte. The master then terminates the read operation
(issuing a STOP condition) following the last bit of the
Data Byte (see Figure 16).
The ISL25700 will work only with the P-type of power
MOSFETs or Darlington pair. Since the driving capability is
limited, it is not recommended to drive a bipolar
transistor. The power MOSFET can be used as a heater
inside a micro temperature chamber.
System Loop Gain Setting
Assemble the application circuit including ISL25700, the
power MOSFET, heating element and thermistor. The
System Loop Gain allows controlling thermal stability of
the feedback system. In other words, current through
the power MOSFET should settle fast and without
oscillation when setpoint changes from one temperature
to another. Settling time of the current can be monitored
by oscilloscope with the current probe.
The byte at address 08h determines if the Data Bytes
being read are from volatile or non-volatile memory (see
“Memory Map” on page 10).
Application Information
In order to get the correct temperature setting, it is very
important to chose an appropriate thermistor and
calibrate the complete system. The following sequence
describes the thermistor selection and calibration
procedure.
Another way to determine system stability is to obtain a
phase margin of the system by analyzing Bode plots.
Bode plots of the gain and phase margins can be
obtained by disconnecting the thermistor from R
-
TH
1. Select a thermistor type and get the RT curve from
manufacturer.
breaking the loop, and connecting a low frequency signal
analyzer between the R pin and the thermistor. That
TH
2. Find out a thermistor resistance at the desired
temperature and select the coarse temperature
range from Table 2. The thermistor value at set
will allow analysis of the system transfer function vs.
frequency. Note the thermistor has to be biased with
30μA DC current from an external supply. The signal
analyzer sweeps the frequency at input node (R ) and
TH
FN6885.0
September 3, 2010
15
ISL25700
measures the phase change of the output node
(thermistor). As a rule of thumb, phase margin should be
at least 45° when the system gain reaches 0dB.
Placement and Layout Consideration
It is recommended to place the ISL25700 and thermistor
as close as possible to each other, inside the insulated
area to achieve higher accuracy and keep the ground
trace between the thermistor and the device as short as
possible. The device ground pin and the system ground
should be connected at a single point, known as the
“single point ground”, preventing picking up the common
It is not recommended to change the system loop gain
when it is determined.
Calibration Procedure
Power-up the circuit and program Reg.01h[2:0] = 001b
of ISL25700. Use an externally calibrated temperature
sensor to measure the temperature of the thermistor.
When the thermistor temperature is stabilized, it can be
adjusted to the desired point by changing the Fine
Temperature Control settings in Reg.02h[7:0] until the
external thermometer indicates +91.5°C (for this
example).
ground noise into the R
feedback pin.
TH
The ISL25700 also can be placed outside of the insulated
area and far away from the thermistor, but the setpoint
accuracy will decrease, due to the wide ambient
temperature range. It is recommended to use a look-up
table based on Equation 2 to compensate for the setpoint
shift.
The decimal FTC code can be calculated by solving for
Equations 1 and 2 as follows:
Put a 1μF capacitor in parallel with 0.1μF decoupling
capacitor close to the VDD pin.
K1 × R
(T) – K2 × R (T)
INT
TH
(EQ. 3)
Code = ----------------------------------------------------------------------------- × 255
It is recommended to have a pull-up resistor of 500k or
higher, or a high-pass RC filter, as shown in the “Block
Diagram/Application Circuit” on page 2, to the gate of a
P-MOSFET in order to prevent a high current spike
through the MOSFET at power-up. The time constant of
the high-pass filter should be in the range of 1μs to 20μs.
K3 × R (T)
TH
Note, the final application system temperature depends
on the allowed power consumption and the level of
insulation from the ambient temperature.
Two different calibration point settings can be stored in
General Purpose non-volatile registers. More calibrated
temperature points can be stored and used as a look-up
table in an external memory.
FN6885.0
September 3, 2010
16
ISL25700
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE REVISION
CHANGE
9/3/10
FN6885.0 Initial release.
Products
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FN6885.0
September 3, 2010
17
ISL25700
Package Outline Drawing
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
8.
PIN 1
INDEX AREA
2.10
A
PIN #1 ID
8.
0.05 MIN.
B
1
4
1
4X 0.20 MIN.
0.10 MIN.
10
5
0.80
10X 0.40
10 X 0.20
0.10
9
6
2X
6X 0.50
4
TOP VIEW
(10 X 0.20)
0.10 M C A B
M C
BOTTOM VIEW
SEE DETAIL "X"
(0.05 MIN)
(0.10 MIN.)
MAX. 0.55
PACKAGE
OUTLINE
1
0.10 C
C
(10X 0.60)
SEATING PLANE
0.08 C
(2.00)
SIDE VIEW
0 . 125 REF
(0.80)
(1.30)
C
(6X 0.50 )
(2.50)
0-0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All Dimensions are in millimeters. Angles are in degrees.
Dimensions in ( ) for Reference Only.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Maximum package warpage is 0.05mm.
6. Maximum allowable burrs is 0.076mm in all directions.
7. Same as JEDEC MO-255UABD except:
No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm
Lead Length dim. = 0.45mm max. not 0.42mm.
8. The configuration of the pin #1 identifier is optional, but must be located within
the zone indicated. The pin #1 identifier may be either a mold or mark feature.
FN6885.0
September 3, 2010
18
相关型号：
ISL26102AVZ-T7
2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24, ROHS COMPLIANT, PLASTIC, MO-153, TSSOP-24
RENESAS
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