ISL24202IRTZ-T13 [RENESAS]
Programmable VCOM Calibrator with EEPROM, TDFN, /Reel;
| 型号： | ISL24202IRTZ-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Programmable VCOM Calibrator with EEPROM, TDFN, /Reel 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总12页 (文件大小：428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Programmable V
Calibrator with EEPROM
COM
ISL24202
Features
The ISL24202 is an 8-bit programmable current sink that can be
used in conjunction with an external voltage divider to generate a
• Adjustable 8-Bit, 256-Step, Current Sink Output
• On-Chip 8-Bit EEPROM
voltage source (V
) positioned between the analog supply
COM
• Up/Down Counter Interface
voltage and ground. The current sink’s full-scale range is
controlled by an external resistor, R . With the appropriate
• Guaranteed Monotonic Over-Temperature
SET
choice of external resistors R and R , the V
COM
voltage range
1
2
• 4.5V to 19.0V Analog Supply Range for Normal Operation
(10.8V Minimum Analog Supply Voltage for Programming)
can be controlled between any arbitrary voltage range. The
ISL24202 has an 8-bit data register and 8-bit EEPROM for storing
both a volatile and a permanent value for its output, accessible
through a single up/down counter interface pin (CTL). After the
• 2.25V to 3.6V Logic Supply Voltage Operating Range
• Pb-free (RoHS-Compliant)
part is programmed with the desired V
value, the Counter
COM
• Ultra-Thin 8 Ld TDFN (3 x 3 x 0.8mm Max)
Enable pin (CE) can be grounded to prevent further changes. On
every power-up the EEPROM contents are automatically
transferred to the data register, and the pre-programmed output
Applications
• LCD Panel V
Generator
voltage appears at the V
pin.
COM
OUT
• Electrophoretic Display V
Generator
COM
The ISL24202 can be used with a high output drive buffer
amplifier, which allows it to directly drive the V
LCD panel.
input of an
COM
Related Literature
• See AN1633 for ISL24202 Evaluation Board Application Note
“ISL24202IRTZ-EVALZ Evaluation Board User Guide” (Coming
Soon)
The ISL24202 is available in an 8 Ld 3mm x 3mm TDFN
package. This package has a maximum height of 0.8mm for very
low profile designs. The ambient operating temperature range is
-40°C to +85°C.
VDD
AVDD
5
2
6
R1
R2
CTL
LCD PANEL
I/O PIN*
1
MICRO-
CONTROLLER
OUT
7
ISL24202
VCOM
I/O PIN
CE
8
SET
EL5411T
RSET
4
* 0, 1, TRI-STATE
FIGURE 1. TYPICAL ISL24202 APPLICATION
March 15, 2011
FN7587.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL24202
Block Diagram
VDD
AVDD
2
5
VDD
RBIAS
3
DNC
1
ANALOG DCP
AND
CURRENT SINK
OUT
6
CTL
DIGITAL
INTERFACE
DAC
REGISTERS
UP/DOWN
COUNTER
RBIAS
Q1
7
A1
CE
8-BIT EEPROM
CS
8
SET
4
GND
FIGURE 2. BLOCK DIAGRAM OF THE ISL24202
Pin Descriptions
PIN NAME PIN #
Pin Configuration
ISL24202
(8 LD TDFN)
TOP VIEW
FUNCTION
OUT
1
Adjustable Sink Current Output Pin. The sink current into
the OUT pin is equal to the DAC setting times the
maximum adjustable sink current divided by 256. See
the “SET” pin function description below (pin 8) for
setting the maximum adjustable sink current.
SET
CE
OUT
AVDD
DNC
GND
1
2
3
4
8
7
A
2
3
High-Voltage Analog Supply. Bypass to GND with 0.1µF
capacitor.
VDD
CTL
VDD
6
5
PAD
DNC
Do Not Connect to external circuitry. It is acceptable to
ground this pin.
GND
4
5
Ground connection.
(*CONNECT THERMAL PAD TO GND)
V
Digital power supply input. Bypass to GND with 0.1µF
de-coupling capacitor.
DD
CTL
6
Up/Down Control for internal counter and Internal
EEPROM Programming Control Input. When CE is high:
A low-to-mid transition increments the 8-bit counter,
adding 1 to the DAC setting, increasing the OUT sink
current, and lowering the divider voltage at the OUT pin.
A high-to-mid transition decrements the 8-bit counter,
subtracting 1 from the DAC setting, decreasing the OUT
sink current, and increasing the divider voltage at the
OUT pin.
To program the EEPROM, take this pin to >4.9V (see
“CTL EEPROM Programming Signal Time” in the
“Electrical Specifications” table on page 5 for details).
Float when not in use.
CE
7
Counter Enable Pin. Connect CE to V to enable
DD
adjustment of the output sink current. Float or connect
CE to GND to prevent further adjustment or
programming (Note: the CE pin has an internal 500nA
pull-down sink current). The EEPROM value will be
copied to the register on a V to V transition.
OH OL
SET
8
-
Maximum Sink Current Adjustment Pin. Connect a
resistor from SET to GND to set the maximum
adjustable sink current of the OUT pin. The maximum
adjustable sink current is equal to (AV /20) divided
DD
by R
.
SET
PAD
Thermal pad should be connected to system ground
plane to optimize thermal performance.
FN7587.0
March 15, 2011
2
ISL24202
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
PACKAGE
(Pb-Free)
PKG.
DWG. #
INTERFACE
COUNTER
(°C)
ISL24202IRTZ
202Z
Evaluation Board
-40 to +85
8 Ld 3x3 TDFN
L8.3x3A
ISL24202IRTZ-EVALZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page ISL24202. For more information on MSL please see techbrief TB363.
FN7587.0
March 15, 2011
3
ISL24202
Absolute Maximum Ratings
Thermal Information
Supply Voltage
Thermal Resistance (Typical)
8 Ld TDFN Package (Notes 4, 5). . . . . . . . .
θ
(°C/W)
53
θ
(°C/W)
11
JA
JC
AV to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
DD
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
Moisture Sensitivity (see Technical Brief TB363)
DD
Input Voltage with respect to Ground
SET, CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV +0.3V
CE and WP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V +0.3V
DD
Output Voltage with respect to Ground
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
DD
OUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV
DD
Continuous Output Current
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 2kV
Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
Operating Range
AV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V
DD
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V
DD
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Test Conditions: V = 3.3V, AV = 18V, R = 5kΩ, R = 10kΩ, R = 10kΩ, (See Figure 5). Typicals are at
DD
DD
SET
1
2
T
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
A
MIN
MAX
SYMBOL
DC CHARACTERISTICS
Supply Range - Operating
PARAMETER
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
V
V
2.25
10.8
4.5
3.6
19
19
V
V
V
DD
DD
AV
AV
AV Supply Range Supporting EEPROM Programming
DD
DD
DD
AV Supply Range for Wide-Supply Operation without
DD
EEPROM Programming
I
V
Supply Current
CTL = 0.5*V
40
24
65
38
µA
µA
DD
DD
DD
DD
I
AV Supply Current
CTL = 0.5*V
AVDD
DD
OUT PIN CHARACTERISTICS
SET
SET Zero-Scale Error
SET Full-Scale Error
±3
±8
LSB
LSB
V
ZSE
FSE
SET
V
OUT Voltage Range
V
+ 1.75
AV
DD
OUT
SET
SET
SET Voltage Drift
7
4
µV/°C
mA
VD
I
Maximum OUT Sink Current
Integral Non-Linearity
Differential Non-Linearity
OUT
INL
±2
LSB
LSB
DNL
±1
EEPROM CHARACTERISTICS
EEPROM Programming Time (internal)
UP/DOWN COUNTER CONTROL INPUTS (SEE FIGURE 11)
t
100
ms
PROG
V
CE and CTL Input Logic High Threshold
CE and CTL Input Logic Low Threshold
CE Input Pull Down Current Sink
CTL Input Bias Current
0.7*V
V
IH
DD
V
0.3*V
1.5
15
V
IL
CS_PD
DD
I
0.5
7
µA
µA
µA
µs
ms
I
CTL = GND (sourcing)
CTL = V (sinking)
CTL
7
15
DD
t
CE to CTL Start Delay
50
ST
t
EEPROM Recall Time (after CE de-asserted)
10
READ
FN7587.0
March 15, 2011
4
ISL24202
Electrical Specifications Test Conditions: V = 3.3V, AV = 18V, R = 5kΩ, R = 10kΩ, R = 10kΩ, (See Figure 5). Typicals are at
DD
DD
SET
1
2
T
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
A
MIN
MAX
SYMBOL
PARAMETER
CTL High Pulse Rejection Width
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
µs
µs
µs
µs
µs
V
t
20
20
H_REJ
t
CTL Low Pulse Rejection Width
L_REJ
t
CTL High Minimum Valid Pulse Width
CTL Low Minimum Valid Pulse Width
CTL Minimum Time Between Counts
CTL EEPROM Program Voltage (see Figure 9)
CTL EEPROM Programming Signal Time
CTL High-to-Mid to OUT Propagation Time
CTL Low-to-Mid to OUT Propagation Time
200
200
10
H_MIN
t
L_MIN
t
MTC
V
4.9
19
PROG
PROG
t
200
65
µs
µs
µs
t
H_PROP
t
65
L_PROP
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7587.0
March 15, 2011
5
ISL24202
Application Information
AVDD
REGISTER VALUE
255
LCD panels have a V
(common voltage) that must be precisely
adjustment
COM
19R
set to minimize flicker. Figure 3 shows a typical V
COM
circuit using a mechanical potentiometer, and the equivalent
circuit replacement using the ISL24202. Having a digital counter
interface enables automatic, digital flicker minimization during
production test and alignment. After programming, the counter
interface is not needed again - the ISL24202 automatically powers
AVDD
20
254
253
VDCP
up with the correct V
voltage programmed previously.
COM
252
The ISL24202 uses a digitally controllable potentiometer (DCP),
with 256 steps of resolution (Figure 4) to change the current
drawn at the OUT pin, which then changes the voltage created by
R
251
2
the R - R resistor divider (Figure 5). The OUT voltage can then be
1
2
1
buffered by an external amplifier (A2) to generate a buffered output
voltage (V ) capable of driving the V input of an LCD panel.
0
COM COM
The amount of current sunk is controlled by the setting of the
DCP, which is recalled at power-up from the ISL24202’s internal
EEPROM. The EEPROM is typically programmed during panel
manufacture. As noted in the “Electrical Specifications” section
FIGURE 4. SIMPLIFIED SCHEMATIC OF DCP
on page 4, the ISL24202 requires a minimum AV voltage of
Output Current Sink
Figure 5 shows the schematic of the OUT current sink. The
combination of amplifier A1, transistor Q1, and resistor R
forms a voltage-controlled current source, with the voltage
determined by the DCP setting.
DD
10.8V for EEPROM programming, but will work in normal
operation down to 4.5V after the EEPROM has been
programmed, with no additional EEPROM writing.
AVDD
SET
AVDD
AVDD
RA
R1
OUT
RB
VCOM
VOUT
VDCP
IOUT
Q1
R2
R1 = RA
VSAT
A1
RC
R2 = RB+RC
SET
VSET = VDCP = IOUT * RSET
RSET = RARB + RARC
20RB
RSET
IOUT
FIGURE 5. CURRENT SINK CIRCUIT
VDD
AVDD
AVDD
The external R
resistor sets the full-scale (maximum) sink current
that can be pulled from the OUT node. The relationship between
SET
ISL24202
R1
I
and Register Value is shown in Equation 2.
IOUT
OUT
OUT
VCOM
V
AV
DD
20
A2
RegisterValue + 1
1
DCP
⎛
⎝
⎞ ⎛
⎞ ⎛
⎠ ⎝
⎞
⎠
SET
(EQ. 2)
-------------
-------------------------------------------------- -------------- ------------
I
=
=
R2
OUT
⎠ ⎝
R
256
R
SET
SET
RSET
The maximum value of I
can be calculated by substituting the
OUT
maximum register value of 255 into Equation 2, resulting in
Equation 3:
FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT
A
VDD
(EQ. 3)
--------------------
I
(MAX) =
OUT
DCP (Digitally Controllable Potentiometer)
20R
SET
The DCP controls the voltage that ultimately controls the SET
current. Figure 4 shows the relationship between the register
value and the DCP’s tap position. Note that a register value of 0
selects the first step of the resistor string. The output voltage of
the DCP is given in Equation 1:
Equation 2 can also be used to calculate the unit sink current
step size per Register Code, resulting in Equation 4:
AV
DD
(EQ. 4)
---------------------------------------------
=
I
STEP
(256)(20)(R
)
SET
AV
(EQ. 1)
RegisterValue + 1
DD
⎛
⎝
⎞ ⎛
⎞
⎠
-------------------------------------------------- --------------
V
=
DCP
⎠ ⎝
256
20
FN7587.0
March 15, 2011
6
ISL24202
Using Equations 6 and 7, calculate the values of R and R :
Determination of R
The ultimate goal for the ISL24202 is to generate an adjustable
voltage between two endpoints, V and V , with
a fixed power supply voltage, AV . This is accomplished by
1
2
SET
8.5–6.5
(EQ. 10)
⎛
⎝
⎞
⎠
-------------------------------------
R
R
= 5120 ⋅ 7500 ⋅
= 5120 ⋅ 7500 ⋅
= 35.4kΩ
1
2
256 ⋅ 8.5 – 6.5
COM_MIN COM_MAX
DD
8.5 – 6.5
-----------------------------------------------------------------
⎛
⎝
⎞
choosing the correct values for R , R and R . The exact value
(EQ. 11)
= 46.4kΩ
SET
1
2
⎠
255 ⋅ 15 + 6.5 – 256 ⋅ 8.5
of R
is not critical. Values from 1k to more than 100k will
work under most conditions. The following expression calculates
SET
the minimum R
value:
SET
Table 1 shows the resulting V
value for these conditions.
voltage as a function of register
COM
AV
⎛
⎜
⎞
⎟
⎟
⎟
⎟
⎠
DD
--------------
(EQ. 5)
16
⎜
⎜
⎜
⎝
-----------------------------------------------------
R
(MIN) =
(kΩ)
TABLE 1. EXAMPLE V
vs REGISTER VALUE
OUT
SET
AV
DD
20
⎛
⎝
⎞
⎠
--------------
–
V
OUT(MIN)
REGISTER VALUE
V
(V)
OUT
0
8.49
8.34
8.18
8.02
7.87
7.71
7.55
7.50
7.40
7.24
7.09
6.93
6.77
6.62
6.50
Note that this is the absolute minimum value for R . Larger
SET
20
R
values reduce quiescent power, since R and R are
SET
1 2
proportional to R . The ISL24202 is tested with a 5kΩ R
.
SET SET
40
60
Determination of R and R
1
2
With AV , V
and V
known and R chosen
80
DD COM(MIN)
COM(MAX)
SET
per the above requirements, R and R can be determined using
1
2
100
120
127
140
160
180
200
220
240
255
Equations 6 and 7:
V
– V
COM(MIN)
⎛
⎞
⎟
⎠
COM(MAX)
(EQ. 6)
--------------------------------------------------------------------------------
R
R
= 5120 ⋅ R
= 5120 ⋅ R
⎜
⎝
1
2
SET
SET
256 ⋅ V
– V
COM(MAX)
COM(MIN)
V
– V
⎛
⎜
⎝
⎞
⎟
⎠
COM(MAX)
COM(MIN)
--------------------------------------------------------------------------------------------------------------------
255 ⋅ AV
+ V
– 256 ⋅ V
COM(MIN) COM(MAX)
DD
(EQ. 7)
Final Transfer Function
The voltage at the OUT pin can be calculated from Equation 8:
R
R
1
20R
⎝
SET
⎛
⎜
⎝
⎞ ⎛
⎟ ⎜
⎠ ⎝
⎛
⎞⎞
⎟⎟
⎠⎠
RegisterValue + 1
-------------------------------------------------- --------------------
1 –
2
--------------------
V
= AV
⎜
OUT
DD
R + R
256
1
2
Output Voltage Span Calculation
(EQ. 8)
It is also possible to calculate V
existing resistor values.
and V
from the
is drawn
COM(MIN)
COM(MAX)
occurs when the greatest current, I
OUT(MAX),
With external amplifier A2 in the unity-gain configuration,
= V
V
V
.
COM
COM_MIN
OUT
from the middle node of the R /R divider. Substituting
1
2
RegisterValue = 255 into Equation 8 gives the following:
Example
As an example, suppose the A
R
R
1
⎛
⎜
⎝
⎞ ⎛
⎟ ⎜
⎠ ⎝
⎛
⎜
⎝
⎞⎞
⎟⎟
⎠⎠
supply is 15V, the desired
2
(EQ. 12)
(EQ. 13)
VDD
--------------------
1
--------------------
V
= AV
1 –
COM(MIN)
DD
R + R
2
20R
SET
V
= 6.5V and the desired V
= 8.5V. R
is
COM_MIN
arbitrarily chosen to be 7.5kΩ.
COM_MAX
SET
Similarly, RegisterValue = 0 for V
COM(MAX)
:
First, verify that our chosen R
meets the minimum
SET
requirement described in Equation 5:
R
R
1
⎛
⎜
⎝
⎞ ⎛
⎟ ⎜
⎠ ⎝
⎛
⎞⎞
⎟⎟
⎠⎠
1
2
--------------------
--------- --------------------
⎜
V
= AV
1 –
COM(MAX)
DD
R + R
256 20R
⎝
SET
1
2
15
⎛
⎜
⎜
⎜
⎝
⎛
⎜
⎜
⎜
⎝
⎞
⎟
⎟
⎟
⎠
⎞
⎟
------
16
(EQ. 9)
------------------------------
(7.5kΩ) >
R
(MIN) =
= 0.163kΩ
⎟
⎟
⎠
By finding the difference of Equation 13 and Equation 12, the total
span of V can be found:
SET
15
⎛
⎞
------
6.5V –
COM
⎝
⎠
20
R
R
1
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎞
⎟
⎠
1
2
⎛
⎝
⎞
--------- --------------------
⎜
(EQ. 14)
--------------------
V
SPAN = AV
1 –
COM
DD
⎠
256 20R
⎝
SET
R +R
1
2
FN7587.0
March 15, 2011
7
ISL24202
Assuming that the I
in Equation 14 simplifies to:
(MIN) = 0 instead of I
OUT
, the expression
STEP
Operating and Programming
Supply Voltage and Current
R
⋅ R
R ⋅ R
1
2
AV
⎛
⎜
⎝
⎞ ⎛
⎞
⎟
⎠
⎛
⎜
⎝
⎞
1
2
DD
-------------------- --------------------
--------------------
To program the EEPROM, AV must be ≥10.8V. If further
V
SPAN =
=
I
(MAX)
DVROUT
⎟ ⎜
⎟
DD
COM
R
+ R
20R
R + R
1 2
⎠ ⎝
⎠
1
2
SET
programming is not required, the ISL24202 will operate over an
(EQ. 15)
AV range of 4.5V to 19V.
DD
During EEPROM programming, I and I
DD AVDD
will temporarily be
OUT Pin Leakage Current
When the voltage on the OUT pin is greater than 10V, an
4-5x higher for up to 100ms (t
).
PROG
additional leakage current flows into the pin in addition to the
current. Figure 6 shows the I current and the OUT pin
current for OUT pin voltage up to 19V. In applications where the
voltage on the OUT pin will be greater than 10V, the actual output
voltage will be lower than the voltage calculated by Equation 8
due to this extra current. The graph in Figure 6 was measured
Up/Down Counter Interface
I
SET
SET
The ISL24202 allows the adjustment of the output V
voltage
COM
and the programming of the non-volatile memory through a
single pin (CTL) when the CE (counter enable) pin is high. The CTL
pin is biased so that its voltage is set to VDD/2 if the driving
circuit is set to Tri-state or High Impedance (Hi-Z), allowing
up/down operation using common digital I/O logic.
with R
= 4.99kΩ.
SET
0.30
REGISTER = 255
CTL Pin
0.25
0.20
0.15
0.10
0.05
0.00
OUT PIN CURRENT
SET PIN CURRENT
When a mid-high-mid transition is detected on the CTL pin (see
Figure 11), the internal register value counts down by one at the
trailing (high-mid) edge, and the output V
voltage is
COM
increased according to Equation 8. Similarly, when a mid-low-mid
transition is detected on the CTL pin, the internal register value
counts up by one at the trailing (low-mid) edge, and the output
V
voltage is decreased. Once the maximum or minimum
COM
value is reached, the counter saturates and will not overflow or
underflow beyond those values.
CTL should have a noise filter to reduce bouncing or noise on the
input that could cause unwanted counts when the CE pin is high.
Figure 8 shows a simple debouncing circuit consisting of a series
1kΩ resistor and a shunt 0.01µF capacitor connected on the CTL
pin. To avoid unintentional adjustment, the ISL24202 guarantees
to reject CTL pulses shorter than 20µs.
0
2
4
6
8
10
12
14
16
18
20
OUT PIN VOLTAGE (V)
FIGURE 6. OUT PIN LEAKAGE CURRENT
AV
DD
Power Supply Sequence
CLOSE TO
PROGRAM
EEPROM
The recommended power supply sequencing is shown in
Figure 7. When applying power, V should be applied before or
DD
ISL24202
CTL
1kΩ
at the same time as AV . The minimum time for t is 0µs.
DD VS
When removing power, the sequence of V and AV is not
DD DD
important.
0.01µF
VDD
FIGURE 8. EXTERNAL DEBOUNCER ON CTL PIN
AVDD
This pin is pulled above 4.9V to program the EEPROM. See
“Programming the EEPROM” on page 9 for details.
tVS
FIGURE 7. POWER SUPPLY SEQUENCE
After CE (Counter Enable) is asserted and after programming
EEPROM, the very first CTL pulse is ignored (see Figure 11) to
avoid the possibility of a false count (since CTL state may be
unknown after programming).
Do not remove V or AV within 100ms of the start of the
DD DD
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
CE Pin
To change the counter controlling the output voltage, the CE
(Counter Enable) pin must be pulled high (V ). When the CE pin
DD
is pulled low, the counter value is loaded from EEPROM, which
takes 10ms (during which the inputs should remain constant).
The CE pin has an internal pull-down to keep it at a logic low
FN7587.0
March 15, 2011
8
ISL24202
when not being driven. CE should be pulled low before powering
1. Power-up the ISL24202. The EEPROM value will be loaded.
the device down to ensure that any glitches or transients during
power-down will not cause unwanted EEPROM overwriting.
2. Set the CE pin to V
.
DD
3. Change the V
OUT
voltage using the CTL pin to the desired
The CE pin has a Schmitt trigger on the input to prevent false
triggering during slow transitions of the CE pin. The CE pin
transition time should be 10µs or less.
value, noting that first pulse will be ignored.
4. Pull the CTL pin to 4.9V or higher for at least 200µs. The
counter value will be written to EEPROM after 100ms.
5. Change the V
OUT
value (using the CTL pin) to a different value,
Programming the EEPROM
noting that first pulse after programming will be ignored.
To program the non-volatile EEPROM, pull the CTL pin above 4.9V
for more than 200µs. The level and timing is shown in Figure 9. It
then takes a maximum of 100ms after CTL crosses 4.9V for the
programming to be completed inside the device.
6. Set the CE pin to 0V. The stored output value will be loaded
from EEPROM after 10ms.
7. Verify that the output value is the same value programmed in
Step 4.
CTL VOLTAGE
The CTL pin should be left floating after programming. The
EEPROM
>200µs
OPERATION
voltage at the CTL pin will be internally biased to V /2 to ensure
DD
COMPLETE
that no additional pulses will be seen by the Up/Down counter. To
prevent further changes, ground the CE pin.
4.9V
100ms
Typical Application Circuit
Shown below in Figure 10 is a typical circuit that can be used to
program the ISL24202 via the up/down counter interface. Three
momentary push-button switches are required. SW1 connected
t
PROG
TIME
between CTL and AV allows the user to bring CTL above V for
DD DD
programming the EEPROM, SW2 connected to V to pull CTL up,
DD
FIGURE 9. EEPROM PROGRAMMING
and SW3 connected to GND to pull CTL to down. All the switches
should have 1kΩ current-limiting resistors in series.
When the part is programmed, the data in the counter register is
written into the EEPROM. This value will be loaded from the
EEPROM during subsequent power-ups as well as when the CE
pin is pulled low. The ISL24202 is factory-programmed to
mid-scale. As with asserting CE, the first pulse after a program
operation is ignored. The EEPROM contents can be written and
verified using the following steps:
For adjustment and programming to occur, the CE pin has to be
set to V . This can be achieved by a single-pull double-throw
DD
switch (SW4) connected between V and GND.
DD
Note that pressing the UP button increments the counter, but
results in V
decreasing. Similarly, pressing the DOWN
COM_OUT
button decrements the counter, and results in V
increasing.
COM_OUT
V
DD
V
AV
DD
DD
ENABLE
ADJUST /
PROGRAM
AV
DD
AV
V
DD
DD
0.1µF
0.1µF
SW4
1kΩ
1kΩ
DISABLE
V
AV
DD
DD
SW2
CLOSE TO
R
R
1
2
PROGRAM
EEPROM
UP
EL5411T
CE
CTL
ISL24202
OUT
SW1
V
to LCD Panel
COM
GND
SET
0.01µF
DOWN
SW3
R
SET
1kΩ
FIGURE 10. TYPICAL APPLICATION CIRCUIT
FN7587.0
March 15, 2011
9
ISL24202
Up/Down Counter Waveforms
The operation modes of the ISL24202 is shown in Table 2.
TABLE 2. ISL24202 OPERATION MODES
INPUT
OUTPUT
CTL
X
CE
Lo
Counter
V
EEPROM
COM_OUT
No Change
X
Lo to Hi
Hi
Ignore first CTL pulse
No Change
No Change
No Change
Hi to Mid
Lo to Mid
Decrement
Increment
No Change
Increase
Decrease
No Change
Hi
Mid to >4.9V
Hi
Write Counter
Value to EEPROM
>4.9V to Mid
X
Hi
Ignore next CTL Pulse
No Change
No Change
Hi to Lo
EEPROM
Programmed
Value
Read Value
Figure 11 shows the associated waveforms.
NOTE:
FIRST PULSE AFTER
PROGRAMMING IS
IGNORED
FIRST PULSE AFTER
ASSERTING CE IS
IGNORED
AFTER COUNTER ENABLE IS ASSERTED,
THE FIRST CTL PULSE IS IGNORED
t
PROG
V
= 4.9V
PROG
t
H_REJ
t
ST
t
MTC
t
READ
CTL HIGH
CTL V /2
DD
CTL LOW
t
L_REJ
t
L_MIN
t
H_MIN
CE
DISABLE ADJUSTMENT
ENABLE ADJUSTMENT
t
L_PROP
t
H_PROP
ENABLE ADJUSTMENT
AVDD
VDD
COUNTER
OUTPUT
7A
7A
79
7B
78
7B
7A
ASSUME COUNTER
STARTS WITH VALUE 78
DEASSERTING CE
RELOADS 7B
FROM EEPROM
WRITE 7B TO
EEPROM
VCOM
EXAMPLE POST POWER-UP TIMING
FIGURE 11. COUNTER INTERFACE TIMING DIAGRAM
FN7587.0
March 15, 2011
10
ISL24202
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
FN7587.0
CHANGE
3/15/11
Initial release.
Products
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*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
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FN7587.0
March 15, 2011
11
ISL24202
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
( 1.95)
3.00
A
B
( 8X 0.50)
(1.50)
6
PIN 1
INDEX AREA
( 2.90 )
(4X)
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
0.10 C
2X 1.950
C
6X 0.65
0.75 ±0.05
0.08 C
1
PIN #1
INDEX AREA
6
SIDE VIEW
1.50 ±0.10
5
8
C
0 . 2 REF
4
8X 0.30 ±0.05
0.10 M C A B
8X 0.30 ± 0.10
0 . 02 NOM.
0 . 05 MAX.
2.30 ±0.10
DETAIL "X"
BOTTOM VIEW
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
7.
FN7587.0
March 15, 2011
12
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