ISL23448WFVZ-T7A [RENESAS]
Quad, 128 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™); QFN20, TSSOP20; Temp Range: -40° to 125°C;
| 型号： | ISL23448WFVZ-T7A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Quad, 128 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™); QFN20, TSSOP20; Temp Range: -40° to 125°C 光电二极管 转换器 |
| 文件： | 总21页 (文件大小：1053K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
NOT RECOMMENDED FOR NEW
RECOMMENDED REPLACEMEN
ISL23428
DESIGNS
T PART
ISL23448
FN7905
Rev 0.00
August 19, 2011
Quad, 128 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)
The ISL23448 is a volatile, low voltage, low noise, low power,
Features
128 tap, quad digitally controlled potentiometer (DCP) with an
• Four potentiometers per package
• 128 resistor taps
SPI Bus™ interface. It integrates four DCP cores, wiper
switches and control logic on a monolithic CMOS integrated
circuit.
• 10kΩ 50kΩor 100kΩ total resistance
Each digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI bus interface. Each potentiometer has an associated
volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly
written to and read by the user. The contents of the WRi
controls the position of the wiper. When powered on, the wiper
of each DCP will always commence at mid-scale (64 tap
position).
• SPI serial interface
- No additional level translator for low bus supply
- Daisy Chaining of multiple DCPs
• Power supply
- V = 1.7V to 5.5V analog power supply
CC
- V
LOGIC
= 1.2V to 5.5V SPI bus/logic power supply
• Maximum supply current without serial bus activity
(standby)
The low voltage, low power consumption, and small package
of the ISL23448 make it an ideal choice for use in battery
- 5µA @ V and V
CC
- 2µA @ V and V
CC
= 5V
LOGIC
LOGIC
= 1.7V
operated equipment. In addition, the ISL23448 has a V
LOGIC
pin allowing down to 1.2V bus operation, independent from the
• Shutdown Mode
V
value. This allows for low logic levels to be connected
CC
- Forces the DCP into an end-to-end open circuit and RWi is
connected to RLi internally
directly to the ISL23448 without passing through a voltage
level shifter.
- Reduces power consumption by disconnecting the DCP
resistor from the circuit
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal processing.
• Wiper resistance: 70Ω typical @ V = 3.3V
CC
• Power-on preset to mid-scale (64 tap position)
• Extended industrial temperature range: -40°C to +125°C
• 20 Ld TSSOP or 20 Ld QFN packages
Applications
• Power supply margining
• Trimming sensor circuits
• Pb-free (RoHS compliant)
• Gain adjustment in battery powered instruments
• RF power amplifier bias compensation
10000
8000
6000
4000
VREF
RH1
-
VREF_M
1 DCP
OF
ISL23448
RW1
+
2000
0
ISL28114
RL1
0
32
64
96
128
TAP POSITION (DECIMAL)
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
FIGURE 2. V
ADJUSTMENT
REF
POSITION, 10kΩ DCP
FN7905 Rev 0.00
August 19, 2011
Page 1 of 21
ISL23448
Block Diagram
VLOGIC
VCC
RH0
WR0
VOLATILE
REGISTER
RW0
SDI
SDO
SCK
POWER UP
INTERFACE
CONTROL
AND
STATUS
LOGIC
RL0
RH1
I/O
BLOCK
LEVEL
SHIFTER
WR1
VOLATILE
REGISTER
RW1
CS
RL1
RH2
WR2
VOLATILE
REGISTER
RW2
RL2
RH3
WR3
VOLATILE
REGISTER
RW3
RL3
GND
Pin Configurations
Pin Descriptions
ISL23448
(20 LD TSSOP)
TOP VIEW
TSSOP
QFN
19
20
1
SYMBOL
DESCRIPTION
1
2
3
RL0
DCP0 “low” terminal
1
2
3
4
5
6
7
8
9
RL3
RL0
20
19
RW0
DCP0 wiper terminal
RW0
RW3
V
Analog power supply.
Range 1.7V to 5.5V
CC
V
18 RH3
17 RL2
16 RW2
15 RH2
14 SCK
13 SDO
CC
RH0
RL1
4
5
2
3
RH0
RL1
DCP0 “high” terminal
DCP1 “low” terminal
DCP1 wiper terminal
DCP1 “high” terminal
Ground pin
RW1
RH1
GND
6
4
RW1
RH1
GND
7
5
V
12
GND
LOGIC
8, 12
9
6, 10
7
SDI 10
11 CS
V
SPI bus/logic supply
Range 1.2V to 5.5V
LOGIC
ISL23448
(20 LD QFN)
TOP VIEW
10
11
13
8
9
SDI
CS
Logic Pin - Serial bus data input
Logic Pin - Active low chip select
11
SDO
Logic Pin - Serial bus data output
(configurable)
20 19 18 17
14
15
16
17
18
19
20
12
13
14
15
16
17
18
SCK
RH2
RW2
RL2
Logic Pin - Serial bus clock input
DCP2 “high” terminal
DCP2 wiper terminal
DCP2 “low” terminal
DCP3 “high” terminal
DCP3 wiper terminal
DCP3 “low” terminal
V
1
2
3
4
5
6
RH3
RL2
RW2
RH2
SCK
16
CC
15
14
13
12
RH0
RL1
RH3
RW3
RL3
RW1
RH1
11 SDO
GND
7
8
9
10
FN7905 Rev 0.00
August 19, 2011
Page 2 of 21
ISL23448
Ordering Information
PART NUMBER
RESISTANCE
OPTION
(kΩ)
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
(Notes 1, 2, 3)
PART MARKING
ISL23448TFVZ
23448 TFVZ
23448 UFVZ
23448 WFVZ
448T
100
50
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
20 Ld TSSOP
M20.173
ISL23448UFVZ
ISL23448WFVZ
ISL23448TFRZ
ISL23448UFRZ
ISL23448WFRZ
NOTES:
20 Ld TSSOP
20 Ld TSSOP
20 Ld 3x4 QFN
20 Ld 3x4 QFN
20 Ld 3x4 QFN
M20.173
M20.173
L20.3x4
L20.3x4
L20.3x4
10
100
50
448U
448W
10
1. Add “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL23448. For more information on MSL please see techbrief TB363.
FN7905 Rev 0.00
August 19, 2011
Page 3 of 21
ISL23448
Absolute Maximum Ratings
Thermal Information
Supply Voltage Range
Thermal Resistance (Typical)
20 Ld TSSOP Package (Notes 4, 7) . . . . . .
20 Ld QFN Package (Notes 5, 6) . . . . . . . .
JA (°C/W)
85
JC (°C/W)
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
33
4
CC
LOGIC
40
Voltage on Any DCP Terminal Pin. . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Wiper Current I (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
ESD Rating
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 6kV
CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 300V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
V
V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V
CC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V
LOGIC
DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to V
CC
Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379
6. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. For , the “case temp” location is taken at the package top center.
JC
Analog Specifications
V
= 2.7V to 5.5V, V
= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
LOGIC
CC
Boldface limits apply over the operating temperature range, -40°C to +125°C.
MIN
TYP
MAX
SYMBOL
PARAMETER
RH to RL Resistance
TEST CONDITIONS
(Note 20)
(Note 8)
(Note 20) UNITS
R
W option
U option
T option
10
50
kΩ
kΩ
kΩ
TOTAL
100
±2
RH to RL Resistance Tolerance
-20
+20
%
ppm/°C
ppm/°C
ppm/°C
V
End-to-End Temperature Coefficient
W option
U option
T option
125
65
45
V
, V
RH RL
DCP Terminal Voltage
Wiper Resistance
V
or V to GND
RL
0
V
CC
RH
R
RH - floating, V = 0V, force I current to the wiper,
RL
70
200
Ω
W
W
I
= (V - V )/R
W
CC RL
TOTAL,
V
= 2.7V to 5.5V
CC
V
= 1.7V
580
32/32/32
< 0.1
16
Ω
pF
CC
C /C /C Terminal Capacitance
See “DCP Macro Model” on page 8
Voltage at pin from GND to V
H
L
W
I
Leakage on DCP Pins
Resistor Noise Density
-0.4
0.4
µA
LkgDCP
Noise
CC
Wiper at middle point, W option
Wiper at middle point, U option
Wiper at middle point, T option
nV/√Hz
nV/√Hz
nV/√Hz
dB
49
61
Feed Thru Digital Feed-through from Bus to Wiper Wiper at middle point
-65
PSRR
Power Supply Reject Ratio
Wiper output change if V change ±10%; wiper at
CC
-75
dB
middle point
FN7905 Rev 0.00
August 19, 2011
Page 4 of 21
ISL23448
Analog Specifications
V
= 2.7V to 5.5V, V
= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
LOGIC
CC
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 20)
(Note 8)
(Note 20) UNITS
VOLTAGE DIVIDER MODE (0V @ RL; V @ RH; measured at RW, unloaded)
CC
Integral Non-linearity, Guaranteed
(Note 13) Monotonic
INL
W option
U, T option
W option
U, T option
W option
U, T option
W option
U, T option
-0.5
-0.5
-0.5
-0.5
-3
±0.15
±0.15
±0.15
±0.15
-1.5
+1.0
+0.5
+0.5
+0.5
0
LSB
(Note 9)
LSB
(Note 9)
DNL
Differential Non-linearity, Guaranteed
LSB
(Note 9)
(Note 12) Monotonic
LSB
(Note 9)
FSerror Full-scale Error
(Note 11)
LSB
(Note 9)
-1.5
0
-0.9
0
LSB
(Note 9)
ZSerror Zero-scale Error
(Note 10)
1.5
3
LSB
(Note 9)
0
0.9
1.5
2
LSB
(Note 9)
Vmatch DCP to DCP Matching
(Note 22)
DCPs at same tap position, same voltage at all RH
terminals, and same voltage at all RL terminals
-2
±0.5
LSB
(Note 9)
TC
(Note 14)
Ratiometric Temperature Coefficient
W option, Wiper Register set to 40 hex
U option, Wiper Register set to 40 hex
T option, Wiper Register set to 40 hex
8
4
ppm/°C
ppm/°C
ppm/°C
ns
V
2.3
300
t
Large Signal Wiper Settling Time
-3dB Cutoff Frequency
From code 0 to 7F hex, measured from 0 to 1LSB
settling of the wiper
LS_Settling
f
Wiper at middle point W option
Wiper at middle point U option
Wiper at middle point T option
1200
250
kHz
kHz
kHz
cutoff
120
RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)
R
Integral Non-linearity, Guaranteed
W option; V = 2.7V to 5.5V
CC
-1.0
-0.5
-0.5
-0.5
±0.5
+1.0
+0.5
+0.5
+0.5
MI
(Note 15)
INL
(Note 18) Monotonic
W option; V = 1.7V
CC
4
MI
(Note 15)
U, T option; V = 2.7V to 5.5V
CC
±0.15
1
MI
(Note 15)
U, T option; V = 1.7V
CC
MI
(Note 15)
R
Differential Non-linearity, Guaranteed
W option; V = 2.7V to 5.5V
CC
±0.15
±0.4
±0.15
±0.4
MI
(Note 15)
DNL
(Note 17) Monotonic
W option; V = 1.7V
CC
MI
(Note 15)
U, T option; V = 2.7V to 5.5V
CC
MI
(Note 15)
U, T option; V = 1.7V
CC
MI
(Note 15)
FN7905 Rev 0.00
August 19, 2011
Page 5 of 21
ISL23448
Analog Specifications
V
= 2.7V to 5.5V, V
= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
LOGIC
CC
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
W option; V = 2.7V to 5.5V
(Note 20)
(Note 8)
(Note 20) UNITS
R
Offset, wiper at 0 position
0
0
1.8
3
1
2
MI
(Note 15)
offset
(Note 16)
CC
W option; V = 1.7V
CC
3
MI
(Note 15)
U, T option; V = 2.7V to 5.5V
CC
0.3
0.5
±0.5
170
80
MI
(Note 15)
U, T option; V = 1.7V
CC
MI
(Note 15)
Rmatch DCP to DCP Matching
(Note 23)
Any two DCPs at the same tap position with the
same terminal voltages
-2
LSB
(Note 9)
TCR
(Note 19)
Resistance Temperature Coefficient
W option; Wiper register set between 19 hex and
7F hex
ppm/°C
ppm/°C
ppm/°C
U option; Wiper register set between 19 hex and
7F hex
T option; Wiper register set between 19 hex and
7F hex
50
Operating Specifications
V
= 2.7V to 5.5V, V
= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
LOGIC
CC
Boldface limits apply over the operating temperature range, -40°C to +125°C.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 20)
(Note 8)
(Note 20) UNITS
I
V
Supply Current (Write/Read)
V
= 5.5V, V = 5.5V,
1.5
mA
LOGIC
LOGIC
LOGIC
CC
f
= 5MHz (for SPI active read and write)
SCK
V
= 1.2V, V = 1.7V,
CC
30
µA
LOGIC
= 1MHz (for SPI active read and write)
f
SCK
I
V
V
Supply Current (Write/Read)
V
V
V
= 5.5V, V = 5.5V
CC
110
10
2
µA
µA
µA
CC
CC
LOGIC
LOGIC
LOGIC
= 1.2V, V = 1.7V
CC
I
Standby Current
= V = 5.5V,
CC
LOGIC SB
LOGIC
SPI interface in standby
V
= 1.2V, V = 1.7V,
0.5
3
µA
µA
µA
µA
µA
µA
µA
µA
LOGIC
CC
SPI interface in standby
I
V
Standby Current
V = V = 5.5V,
LOGIC CC
SPI interface in standby
CC SB
CC
V
= 1.2V, V = 1.7V,
1.5
2
LOGIC
CC
SPI interface in standby
I
V
Shutdown Current
V
= V = 5.5V,
LOGIC SHDN LOGIC
LOGIC CC
SPI interface in standby
V
= 1.2V, V = 1.7V,
0.5
3
LOGIC
CC
SPI interface in standby
I
V
Shutdown Current
V = V = 5.5V,
LOGIC CC
SPI interface in standby
CC SHDN
CC
V
= 1.2V, V = 1.7V,
1.5
0.4
LOGIC
CC
SPI interface in standby
I
Leakage Current, at Pins CS, SDO, SDI,
SCK
Voltage at pin from GND to V
-0.4
<0.1
LkgDig
LOGIC
FN7905 Rev 0.00
August 19, 2011
Page 6 of 21
ISL23448
Operating Specifications
V
= 2.7V to 5.5V, V
= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
LOGIC
CC
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
Wiper Response Time
TEST CONDITIONS
(Note 20)
(Note 8)
(Note 20) UNITS
t
W option; CS rising edge to wiper new position,
from 10% to 90% of final value.
0.4
1.5
3.5
1.5
µs
µs
µs
µs
DCP
U option; CS rising edge to wiper new position,
from 10% to 90% of final value.
T option; CS rising edge to wiper new position,
from 10% to 90% of final value.
tShdnRec DCP Recall Time From Shutdown Mode
CS rising edge to wiper recalled position and RH
connection
V
V
V
V Ramp Rate (Note 21)
Ramp monotonic at any level
0.01
50
V/ms
CC, LOGIC
CC , LOGIC
Ramp
Serial Interface Specification For SCK, SDI, SDO, CS unless otherwise noted.
MIN
TYP
MAX
SYMBOL
PARAMETER
Input LOW Voltage
TEST CONDITIONS
(Note 20)
(Note 8) (Note 20) UNITS
V
-0.3
0.3 x V
V
V
V
IL
LOGIC
+ 0.3
V
Input HIGH Voltage
0.7 x V
V
LOGIC
IH
LOGIC
Hysteresis
SDI and SCK Input Buffer
Hysteresis
V
V
> 2V
< 2V
0.05 x V
LOGIC
LOGIC
LOGIC
0.1 x V
0
LOGIC
V
SDO Output Buffer LOW Voltage
SDO Pull-up Resistor Off-chip
I
I
= 3mA, V
> 2V
0.4
V
V
OL
OL
OL
LOGIC
= 1.5mA, V
< 2V
0.2 x V
LOGIC
LOGIC
R
Maximum is determined by t and t with
1.5
kΩ
pu
RO
FO
maximum bus load Cb = 30pF, f
= 5MHz
SCK
C
SCK, SDO, SDI, CS Pin Capacitance
SCK Frequency
10
pF
MHz
MHz
ns
pin
f
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 1.7V to 5.5V
= 1.2V to 1.6V
≥ 1.7V
5
1
SCK
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
t
SPI Clock Cycle Time
200
CYC
t
SPI Clock High Time
≥ 1.7V
100
100
250
250
50
ns
WH
t
SPI Clock Low Time
≥ 1.7V
ns
WL
t
Lead Time
≥ 1.7V
ns
LEAD
t
Lag Time
≥ 1.7V
ns
LAG
t
SDI, SCK and CS Input Setup Time
SDI, SCK and CS Input Hold Time
SDI, SCK and CS Input Rise Time
SDI, SCK and CS Input Fall Time
SDO Output Disable Time
SDO Output Setup Time
SDO Output Valid Time
SDO Output Hold Time
SDO Output Rise Time
≥ 1.7V
ns
SU
t
≥ 1.7V
50
ns
H
t
≥ 1.7V
10
ns
RI
t
≥ 1.7V
10
20
ns
FI
t
≥ 1.7V
0
100
ns
DIS
t
≥ 1.7V
50
ns
SO
t
≥ 1.7V
150
0
ns
V
t
≥ 1.7V
ns
HO
RO
t
R
= 1.5k, Cbus = 30pF
60
ns
pu
FN7905 Rev 0.00
August 19, 2011
Page 7 of 21
ISL23448
Serial Interface Specification For SCK, SDI, SDO, CS unless otherwise noted. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
SDO Output Fall Time
CS Deselect Time
TEST CONDITIONS
= 1.5k, Cbus = 30pF
pu
(Note 20)
(Note 8) (Note 20) UNITS
t
R
60
ns
µs
FO
CS
t
2
NOTES:
8. Typical values are for T = +25°C and 3.3V supply voltages.
A
9. LSB = [V(RW)
127
– V(RW) ]/127. V(RW)
and V(RW) are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental
127 0
0
voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW) /LSB.
0
11. FS error = [V(RW)
127
– V ]/LSB.
CC
12. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 127. i is the DCP register setting.
i-1
i
13. INL = [V(RW) – i • LSB – V(RW) ]/LSB for i = 1 to 127
i
0
MaxVRW – MinVRW
6
14.
10
for i = 8 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage
and Min( ) is the minimum value of the wiper voltage over the temperature range.
i
i
----------------------------------------------------------------------------- ---------------------
TC
=
V
VRW +25°C
+165°C
i
15. MI = |RW
– RW |/127. MI is a minimum increment. RW
and RW are the measured resistances for the DCP register set to 7F hex and 00
0
127
hex respectively.
0
127
16. Roffset = RW /MI, when measuring between RW and RL.
0
Roffset = RW
/MI, when measuring between RW and RH.
127
17. RDNL = (RW – RW )/MI -1, for i = 8 to 127.
i-1
i
18. RINL = [RW – (MI • i) – RW ]/MI, for i = 8 to 127.
i
0
6
19.
for i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
MaxRi – MinRi
10
+165°C
------------------------------------------------------ ---------------------
TC
=
R
Ri+25°C
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the V and the V supplies at the same time. If this is not possible, it is recommended to ramp-up the V
LOGIC
CC LOGIC
first followed by the V
.
CC
22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.
23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.
DCP Macro Model
R
TOTAL
RH
RL
C
C
L
H
C
W
32pF
32pF
32pF
RW
FN7905 Rev 0.00
August 19, 2011
Page 8 of 21
ISL23448
Timing Diagrams
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
t
CYC
SCK
...
t
WH
t
t
t
RI
FI
t
WL
SU
H
...
MSB
SDI
LSB
SDO
Output Timing
CS
SCK
...
...
t
t
t
DIS
SO
HO
MSB
LSB
SDO
t
V
ADDR
SDI
XDCP™ Timing (For All Load Instructions)
CS
t
DCP
SCK
...
...
MSB
LSB
SDI
V
W
SDO
*When CS is HIGH
SDO at Z or Hi-Z state
FN7905 Rev 0.00
August 19, 2011
Page 9 of 21
ISL23448
Typical Performance Curves
0.12
0.06
0.00
-0.06
-0.12
0.04
0.02
0.00
-0.02
-0.04
0
32
64
96
128
0
32
64
96
128
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. 10kΩ DNL vs TAP POSITION, V = 3.3V, +25°C
FIGURE 4. 50kΩ DNL vs TAP POSITION, V = 3.3V, +25°C
CC
CC
0.16
0.12
0.08
0.04
0.00
0.16
0.08
0.00
-0.08
-0.16
0
32
64
96
128
0
32
64
96
128
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 5. 10kΩ INL vs TAP POSITION, V = 3.3V, +25°C
FIGURE 6. 50kΩ INL vs TAP POSITION, V = 3.3V, +25°C
CC
CC
0.04
0.02
0.12
0.06
0.00
0.00
-0.02
-0.04
-0.06
-0.12
0
32
64
96
128
0
32
64
96
128
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 7. 10kΩ RDNL vs TAP POSITION, V = 3.3V, +25°C
FIGURE 8. 50kΩ RDNL vs TAP POSITION, V = 3.3V, +25°C
CC
CC
FN7905 Rev 0.00
August 19, 2011
Page 10 of 21
ISL23448
Typical Performance Curves (Continued)
0.4
0.3
0.2
0.1
0.0
0.08
0.04
0.00
-0.04
-0.08
0
32
64
96
128
0
32
64
96
128
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 9. 10kΩ RINL vs TAP POSITION, V = 3.3V, +25°C
FIGURE 10. 50kΩ RINL vs TAP POSITION, V = 3.3V, +25°C
CC
CC
100
120
+125°C
+25°C
+125°C
+25°C
100
80
80
60
40
60
40
-40°C
-40°C
20
20
0
0
0
32
64
96
128
0
32
64
96
128
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 11. 10kΩ WIPER RESISTANCE vs TAP POSITION, V = 3.3V
FIGURE 12. 50kΩ WIPER RESISTANCE vs TAP POSITION, V = 3.3V
CC
CC
200
150
100
50
40
30
20
10
0
0
15
43
71
99
127
15
43
71
99
127
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 13. 10kΩ TCv vs TAP POSITION, V = 3.3V
CC
FIGURE 14. 50kΩ TCv vs TAP POSITION, V = 3.3V
CC
FN7905 Rev 0.00
August 19, 2011
Page 11 of 21
ISL23448
Typical Performance Curves (Continued)
400
300
200
100
0
100
80
60
40
20
0
15
43
71
99
127
15
43
71
99
127
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 15. 10kΩ TCr vs TAP POSITION
FIGURE 16. 50kΩ TCr vs TAP POSITION, V = 3.3V
CC
100
20
15
10
5
80
60
40
20
0
0
15
43
71
99
127
15
43
71
99
127
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 17. 100kΩ TCv vs TAP POSITION, V = 3.3V
FIGURE 18. 100kΩ TCr vs TAP POSITION, V = 3.3V
CC
CC
CH1: 20mV/DIV, 2µs/DIV
CH2: 2V/DIV, 2µs/DIV
SCK CLOCK
WIPER
CS RISING
RW PIN
CH1: 1V/DIV, 1µs/DIV
CH2: 10mV/DIV, 1µs/DIV
FIGURE 19. WIPER DIGITAL FEED-THROUGH
FIGURE 20. WIPER TRANSITION GLITCH
FN7905 Rev 0.00
August 19, 2011
Page 12 of 21
ISL23448
Typical Performance Curves (Continued)
V
CC
1V/DIV
0.2µs/DIV
CS
0.5V/DIV
20µs/DIV
WIPER
WIPER
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME
FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
1.8
1.6
1.4
1.2
1.0
CH1: RH TERMINAL
CH2: RW TERMINAL
V
= 5.5V, V = 5.5V
LOGIC
CC
0.8
0.6
0.4
0.2
0
V
= 1.7V, V
= 1.2V
CC
LOGIC
-40
-15
10
35
60
85
110
0.5V/DIV, 0.2µs/DIV
-3dB FREQUENCY = 1.437MHz AT MIDDLE TAP
TEMPERATURE (°C)
FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY
FIGURE 24. STANDBY CURRENT vs TEMPERATURE
Power Pins
Functional Pin Descriptions
Potentiometers Pins
V
CC
Power terminal for the potentiometer section analog power
source. Can be any value needed to support the voltage range of
RHI AND RLI
The high (RHi, i = 0, 1, 2, 3) and low (RLi, i = 0, 1, 2, 3) terminals
of the ISL23448 are equivalent to the fixed terminals of a
mechanical potentiometer. RHi and RLi are referenced to the
relative position of the wiper and not the voltage potential on the
terminals. With WRi set to 127 decimal, the wiper will be closest
to RHi, and with the WRi set to 0, the wiper is closest to RLi.
the DCP pins, from 1.7V to 5.5V, independent of the V
voltage.
LOGIC
Bus Interface Pins
SERIAL CLOCK (SCK)
This input is the serial clock of the SPI serial interface.
RWI
SERIAL DATA INPUT (SDI)
RWi (i = 0, 1, 2, 3) is the wiper terminal, and it is equivalent to the
movable terminal of a mechanical potentiometer. The position of
the wiper within the array is determined by the WRi register.
The SDI is a serial data input pin for SPI interface. It receives
operation code, wiper address and data from the SPI remote
host device. The data bits are shifted in at the rising edge of the
serial clock SCK, while the CS input is low.
FN7905 Rev 0.00
August 19, 2011
Page 13 of 21
ISL23448
to RHi. At the same time, the resistance between RWi and RLi
increases monotonically, while the resistance between RHi and RWi
decreases monotonically.
SERIAL DATA OUTPUT (SDO)
The SDO is a serial data output pin. During a read cycle, the data
bits are shifted out on the falling edge of the serial clock SCK and
will be available to the master on the following rising edge of SCK.
While the ISL23448 is being powered up, all the WRi are reset to
40h (64 decimal), which positions RWi at the center between RLi
and RHi.
The output type is configured through ACR[1] bit for Push-Pull or
Open Drain operation. The default setting for this pin is Push-Pull.
An external pull-up resistor is required for Open Drain output
operation. When CS is HIGH, the SDO pin is in tri-state (Z) or
high-tri-state (Hi-Z) depending on the selected configuration.
The WRi can be read or written to directly using the SPI serial
interface as described in the following sections.
Memory Description
CHIP SELECT (CS)
The ISL23448 contains five volatile 8-bit registers: Wiper Register
WR0, Wiper Register WR1, Wiper Register WR2, Wiper Register
WR3 and Access Control Register (ACR). The memory map of
ISL23448 is shown in Table 1. The Wiper Register WRi at address i,
contains current wiper position of DCPi (i = 0, 1, 2, 3). The Access
Control Register (ACR) at address 10h contains information and
control bits described in Table 2.
CS LOW enables the ISL23448, placing it in the active power
mode. A HIGH to LOW transition on CS is required prior to the
start of any operation after power-up. When CS is HIGH, the
ISL23448 is deselected and the SDO pin is at high impedance,
and the device will be in the standby state.
V
LOGIC
TABLE 1. MEMORY MAP
Digital power source for the logic control section. It supplies an
internal level translator for 1.2V to 5.5V serial bus operation. Use
the same supply as the SPI logic source.
ADDRESS
(hex)
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
10
3
ACR
WR3
WR2
WR1
WR0
40
40
40
40
40
Principles of Operation
The ISL23448 is an integrated circuit incorporating four DCPs
with its associated registers and an SPI serial interface providing
direct communication between a host and the potentiometer.
The resistor array is comprised of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
2
1
0
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
0
6
5
0
4
0
3
0
2
0
1
0
0
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap
positions.
NAME/
VALUE
SHDN
SDO
The SDO bit (ACR[1]) configures the type of SDO output pin. The
default value of SDO bit is 0 for Push-Pull output. The SDO pin
can be configured as Open Drain output for some applications. In
this case, an external pull-up resistor is required. Reference the
“Serial Interface Specification” on page 7.
Voltage at any of the DCP pins, RHi, RLi or RWi, should not
exceed V level at any conditions during power-up and normal
CC
operation.
The V
pin is the terminal for the logic control digital power
LOGIC
source. It should use the same supply as the SPI logic source,
which allows reliable communication with a wide range of
Shutdown Function
microcontrollers and is independent from the V level. This is
extremely important in systems where the master supply has
lower levels than the DCP analog supply.
CC
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e., each DCP is
forced to end-to-end open circuit and each RW shorted to RL
through a 2kΩ serial resistor, as shown in Figure 25. The default
value of the SHDN bit is 1.
DCP Description
Each DCP is implemented with a combination of resistor elements
and CMOS switches. The physical ends of each DCP are equivalent
to the fixed terminals of a mechanical potentiometer (RHi and RLi
pins). The RWi pin of the DCP is connected to intermediate nodes,
and is equivalent to the wiper terminal of a mechanical
RH
potentiometer. The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Register (WRi). When the WR of
a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal (RWi)
is closest to its “Low” terminal (RLi). When the WRi register of a DCP
contains all ones (WRi[7:0] = 7Fh), its wiper terminal (RWi) is closest
to its “High” terminal (RHi). As the value of the WRi increases from
all zeroes (0) to all ones (127 decimal), the wiper moves
RW
2kΩ
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
monotonically from the position closest to RLi to the position closest
FN7905 Rev 0.00
August 19, 2011
Page 14 of 21
ISL23448
When the device enters shutdown, all current DCP WR settings are
maintained. When the device exits shutdown, the wipers will return
to the previous WR settings after a short settling time (see
Figure 26).
Protocol Conventions
The SPI protocol contains Instruction Byte followed by one or more
Data Bytes. A valid Instruction Byte contains instruction as the three
MSBs, with the following five register address bits (see Table 3).
In shutdown mode, if there is a glitch on the power supply which
causes it to drop below 1.3V for more than 0.2 to 0.4µs the
wipers will be RESET to their mid position. This is done to avoid
an undefined state at the wiper outputs.
The next byte sent to the ISL23448 is the Data Byte.
TABLE 3. INSTRUCTION BYTE FORMAT
BIT #
7
6
5
4
3
2
1
0
I2
I1
I0
R4
R3
R2
R1
R0
Table 4 contains a valid instruction set for ISL23448.
If the [R4:R0] bits are zero, one, two or three then the read or write
is to the WRi register. If the [R4:R0] are 10000, then the operation
is to the ACR.
POWER-UP
MID SCALE = 40H
USER PROGRAMMED
AFTER SHDN
Write Operation
SHDN RELEASED
SHDN ACTIVATED
WIPER RESTORE TO
A write operation to the ISL23448 is a two or more bytes
operation. First, it requires that the CS transition from
HIGH-to-LOW. Then, the host sends a valid Instruction Byte,
followed by one or more Data Bytes to the SDI pin. The host
terminates the write operation by pulling the CS pin from
LOW-to-HIGH. Instruction is executed on the rising edge of CS
(see Figure 27).
THE ORIGINAL POSITION
SHDN MODE
TIME (s)
0
FIGURE 26. SHUTDOWN MODE WIPER RESPONSE
SPI Serial Interface
Read Operation
The ISL23448 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with data
clocked in on the rising edge of SCK, and clocked out on the
falling edge of SCK. CS must be LOW during communication with
the ISL23448. The SCK and CS lines are controlled by the host or
master. The ISL23448 operates only as a slave device.
A Read operation to the ISL23448 is a four byte operation. First,
it requires that the CS transition from HIGH-to-LOW. Then, the
host sends a valid Instruction Byte, followed by a “dummy” Data
Byte, NOP Instruction Byte and another “dummy” Data Byte to
the SDI pin. The SPI host receives the Instruction Byte (instruction
code + register address) and requested Data Byte from the SDO
pin on the rising edge of SCK during the third and fourth bytes,
respectively. The host terminates the read by pulling the CS pin
from LOW-to-HIGH (see Figure 28).
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
TABLE 4. INSTRUCTION SET
INSTRUCTION SET
I2
0
0
0
1
1
I1
0
0
1
0
1
I0
0
1
1
0
0
R4
X
R3
X
R2
X
R1
X
R0
X
OPERATION
NOP
X
X
X
X
X
ACR READ
X
X
X
X
X
ACR WRTE
R4
R4
R3
R3
R2
R2
R1
R1
R0
R0
WRi or ACR READ
WRi or ACR WRTE
Where X means “do not care”.
FN7905 Rev 0.00
August 19, 2011
Page 15 of 21
ISL23448
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
DATA BYTE
WR INSTRUCTION
ADDR
SDI
SDO
FIGURE 27. TWO BYTE WRITE SEQUENCE
1
8
16
24
32
CS
SCK
NOP
RD
ADDR
SDI
RD
ADDR
READ DATA
SDO
FIGURE 28. FOUR BYTE READ SEQUENCE
Daisy Chain Write Operation
Applications Information
The write operation starts by a HIGH-to-LOW transition on the CS
line, followed by N number of two bytes write instructions on the
SDI line with reversed chain access sequence: the instruction
byte + data byte for the last DCP in chain is going first, as shown
in Figure 30, where N is a number of DCPs in chain. The serial
data is going through DCPs from DCP0 to DCP(N-1) as follows:
DCP0 --> DCP1 --> DCP2 --> ... --> DCP(N-1). The write instruction is
executed on the rising edge of CS for all N DCPs simultaneously.
Communicating with ISL23448
Communication with ISL23448 proceeds using SPI interface
through the ACR (address 10000b), WR0 (addresses 00000b),
WR1 (addresses 00001b), WR2 (addresses 00010b), WR3
(addresses 00011b) registers.
The wiper of the potentiometer is controlled by the WRi register.
Writes and reads can be made directly to these registers to
control and monitor the wiper position.
Daisy Chain Read Operation
The read operation consists of two parts: first, send the read
instructions (N two bytes operation) with valid address; second,
read the requested data while sending NOP instructions (N two
bytes operation), as shown in Figures 31 and 32.
Daisy Chain Configuration
When an application needs more than one ISL23448, it can
communicate with all of them without additional CS lines by
daisy chaining the DCPs, as shown in Figure 29. In Daisy Chain
configuration, the SDO pin of the previous chip is connected to
the SDI pin of the following chip, and each CS and SCK pins are
connected to the corresponding microcontroller pins in parallel,
like regular SPI interface implementation. The Daisy Chain
configuration can also be used for simultaneous setting of
multiple DCPs. Note, the number of daisy chained DCPs is
limited only by the driving capabilities of SCK and CS pins of
microcontroller; for larger number of SPI devices, buffering of
SCK and CS lines is required.
The first part starts by a HIGH-to-LOW transition on the CS line,
followed by N two bytes read instruction on the SDI line with
reversed chain access sequence: the instruction byte + dummy
data byte for the last DCP in chain is going first, followed by a
LOW-to-HIGH transition on the CS line. The read instructions are
executed during the second part of the read sequence. It also
starts by a HIGH-to-LOW transition on the CS line, followed by N
number of two bytes NOP instructions on the SDI line and
LOW-to-HIGH transition of CS. The data is read on every even byte
during the second part of the read sequence while every odd byte
contains code 111b followed by the address from which the data
is being read.
FN7905 Rev 0.00
August 19, 2011
Page 16 of 21
ISL23448
Wiper Transition
V
Requirements
LOGIC
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1µs). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
6Fh to 7Fh, which have higher transient glitch. Note, that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients,
but that will also reduce the useful bandwidth of the circuit, thus,
this may not be a good solution for some applications. It may be
a good idea, in this case, to use fast amplifiers in a signal chain
for fast recovery.
It is recommended to keep V
normal operation. In a case where turning V
LOGIC
necessary, it is recommended to ground the V
powered all the time during
OFF is
pin of the
LOGIC
LOGIC
and V does
ISL23448. Grounding the V
pin or both V
LOGIC
LOGIC
CC
not affect other devices on the same bus. It is good practice to put
a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to
the V
pin.
LOGIC
V
Requirements and Placement
CC
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the V pin.
CC
N DCP IN A CHAIN
CS
SCK
DCP0
DCP1
DCP2
DCP(N-1)
CS
MOSI
MISO
CS
CS
CS
SCK
SDI
SCK
SCK
SCK
SDI
µC
SDO
SDI
SDO
SDI
SDO
SDO
FIGURE 29. DAISY CHAIN CONFIGURATION
CS
SCK
16 CLKS
C P0
16 CLKLS
C P2
16 CLKS
WR
D
WR
D
D
C P1
WR
WR
D
SDI
D
C P1
C P2
SDO 0
WR
C P2
WR
D
SDO 1
SDO 2
FIGURE 30. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP
FN7905 Rev 0.00
August 19, 2011
Page 17 of 21
ISL23448
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
SDI
INSTRUCTION
ADDR
DATA IN
SDO
DATA OUT
FIGURE 31. TWO BYTE READ INSTRUCTION
CS
SCK
SDI
16 CLKS
RD DCP2
16 CLKS
RD DCP1
16 CLKS
RD DCP0
16 CLKS
NOP
16 CLKS
NOP
16 CLKS
NOP
DCP0 OUT
DCP2 OUT
DCP1 OUT
SDO
FIGURE 32. DAISY CHAIN READ SEQUENCE OF N = 3 DCP
FN7905 Rev 0.00
August 19, 2011
Page 18 of 21
ISL23448
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN7905.0
CHANGE
August 19, 2011
Initial release.
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FN7905 Rev 0.00
August 19, 2011
Page 19 of 21
ISL23448
Package Outline Drawing
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
6.50 ±0.10
SEE DETAIL "X"
10
20
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
9
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
H
- 0.05
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
0.25 +0.05/-0.06
5
0.10 C B A
M
0.10 C
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
(5.65)
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
(0.65 TYP)
(0.35 TYP)
6. Dimension in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153.
FN7905 Rev 0.00
August 19, 2011
Page 20 of 21
ISL23448
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
0.10 M
C
C
A
B
3.00
A
M
0.05
0.50
16X
20X 0.25 +0.05
6
B
4
-0.07
PIN 1 INDEX AREA
(C 0.40)
17
20
A
16
1
6
PIN 1
INDEX AREA
4.00
+0.10
2.65
-0.15
11
6
0.15 (4X)
A
10
7
VIEW "A-A"
1.65 +0.10
-0.15
TOP VIEW
20x 0.40±0.10
BOTTOM VIEW
SEE DETAIL "X"
C
C
0.10
0.9± 0.10
SEATING PLANE
0.08
C
SIDE VIEW
(16 x 0.50)
(2.65)
(3.80)
(20 x 0.25)
5
0.2 REF
C
(20 x 0.60)
0.00 MIN.
0.05 MAX.
(1.65)
(2.80)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN7905 Rev 0.00
August 19, 2011
Page 21 of 21
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