ICL3244EIB [RENESAS]
TRIPLE LINE TRANSCEIVER, PDSO28, PLASTIC, MS-013AE, SOIC-28;
| 型号： | ICL3244EIB |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | TRIPLE LINE TRANSCEIVER, PDSO28, PLASTIC, MS-013AE, SOIC-28 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总20页 (文件大小：846K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ICL3224E, ICL3226E, ICL3244E
+/-15kV ESD Protected, +3V to +5.5V, 1Microamp, 250kbps, RS-232 Transceivers
with Enhanced Automatic Powerdown
FN4899
Rev.6.00
Feb 27, 2006
The Intersil ICL32XXE devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/TIA-232 and
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
V.28/V.24 specifications, even at V
= 3.0V. Additionally,
CC
they provide 15kV ESD protection (IEC61000-4-2 Air Gap
and Human Body Model) on transmitter outputs and receiver
inputs (RS-232 pins). Targeted applications are PDAs,
Palmtops, and notebook and laptop computers where the
low operational, and even lower standby, power
• ESD Protection for RS-232 I/O Pins to 15kV (IEC61000)
• Manual and Enhanced Automatic Powerdown Features
• Drop in Replacements for MAX3224E, MAX3226E,
MAX3244E
consumption is critical. Efficient on-chip charge pumps,
coupled with manual and enhanced automatic powerdown
functions, reduce the standby supply current to a 1A trickle.
Small footprint packaging, and the use of small, low value
capacitors ensure board space savings as well. Data rates
greater than 250kbps are guaranteed at worst case load
conditions. This family is fully compatible with 3.3V only
systems, mixed 3.3V and 5.0V systems, and 5.0V only
systems.
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• RS-232 Compatible with V
• Latch-Up Free
= 2.7V
CC
• On-Chip Voltage Converters Require Only Four External
0.1F Capacitors
• Guaranteed Mouse Driveability (ICL3244E)
• “Ready to Transmit” Indicator Output (ICL3224E/26E)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
• Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 6V/s
• Wide Power Supply Range . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . . . .1A
The ICL3244E is a 3 driver, 5 receiver device that provides a
complete serial port suitable for laptop or notebook
computers. It also includes a noninverting always-active
receiver for “wake-up” capability.
These devices, feature an enhanced automatic
powerdown function which powers down the on-chip power-
supply and driver circuits. This occurs when all receiver and
transmitter inputs detect no signal transitions for a period of
30 seconds. These devices power back up, automatically,
whenever they sense a transition on any transmitter or
receiver input.
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and other Peripherals
- Digital Cameras
Table 1 summarizes the features of the devices represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the
ICL32XXE 3V family.
- Cellular/Mobile Phones
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
TABLE 1. SUMMARY OF FEATURES
ENHANCED
AUTOMATIC
POWERDOWN
FUNCTION?
NO. OF
MONITOR Rx.
DATA
RATE
(kbps)
MANUAL
POWER-
DOWN?
PART
NUMBER
NO. OF NO.OF
Rx. ENABLE
FUNCTION?
READY
OUTPUT?
Tx.
Rx.
(R
)
OUTB
ICL3224E
ICL3226E
ICL3244E
2
2
0
250
250
250
No
No
No
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
1
1
0
1
3
5
FN4899 Rev.6.00
Feb 27, 2006
Page 1 of 20
ICL3224E, ICL3226E, ICL3244E
Ordering Information
PART NO.
ICL3224ECAZ (Note)
ICL3224ECAZ-T (Note)
ICL3224EIA
PART MARKING
TEMP. RANGE (°C)
0 to 70
PACKAGE
20 Ld SSOP (Pb-free)
PKG. DWG. #
M20.209
M20.209
M20.209
M20.209
M20.209
M20.209
M16.209
M16.209
M16.209
M16.209
M16.209
M16.209
M16.209
M16.209
M28.209
M28.209
M28.209
M28.209
M28.209
M28.209
M28.209
M28.209
M28.3
3224ECAZ
3224ECAZ
ICL3224EIA
ICL3224EIA
3224EIAZ
0 to 70
20 Ld SSOP Tape and Reel (Pb-free)
20 Ld SSOP
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
ICL3224EIA-T
20 Ld SSOP Tape and Reel
20 Ld SSOP (Pb-free)
ICL3224EIAZ (Note)
ICL3224EIAZ-T (Note)
ICL3226ECA
3224EIAZ
20 Ld SSOP Tape and Reel (Pb-free)
16 Ld SSOP
ICL3226ECA
ICL3226ECA
3226ECAZ
3226ECAZ
ICL3226EIA
ICL3226EIA
3226EIAZ
ICL3226ECA-T
0 to 70
16 Ld SSOP Tape and Reel
16 Ld SSOP (Pb-free)
ICL3226ECAZ (Note)
ICL3226ECAZ-T
ICL3226EIA
0 to 70
0 to 70
16 Ld SSOP Tape and Reel (Pb-free)
16 Ld SSOP
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
ICL3226EIA-T
16 Ld SSOP Tape and Reel
16 Ld SSOP (Pb-free)
ICL3226EIAZ
ICL3226EIAZ-T
ICL3244ECA
3226EIAZ
16 Ld SSOP Tape and Reel (Pb-free)
28 Ld SSOP
ICL3244ECA
ICL3244ECA
ICL3244ECAZ
ICL3244ECAZ
ICL3244EIA
ICL3244EIA
ICL3244EIAZ
ICL3244EIAZ
ICL3244EIB
ICL3244ECA-T
0 to 70
28 Ld SSOP Tape and Reel
28 Ld SSOP (Pb-free)
ICL3244ECAZ (Note)
ICL3244ECAZ-T (Note)
ICL3244EIA
0 to 70
0 to 70
28 Ld SSOP Tape and Reel (Pb-free)
28 Ld SSOP
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
ICL3244EIA-T
28 Ld SSOP Tape and Reel
28 Ld SSOP (Pb-free)
ICL3244EIAZ (Note)
ICL3244EIAZ-T (Note)
ICL3244EIB
28 Ld SSOP Tape and Reel (Pb-free)
28 Ld SOIC
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
ICL3224E (SSOP)
ICL3226E (SSOP)
TOP VIEW
TOP VIEW
READY
C1+
V+
1
2
20 FORCEOFF
19
READY
C1+
V+
1
2
3
4
5
6
7
8
16 FORCEOFF
15
V
V
CC
CC
3
18 GND
17 T1
14 GND
13 T1
C1-
4
C1-
OUT
OUT
C2+
C2-
5
16 R1
15 R1
C2+
C2-
12 FORCEON
IN
6
11 T1
IN
OUT
V-
7
14 FORCEON
V-
10 INVALID
T2
8
13 T1
IN
R1
IN
9 R1
OUT
OUT
R2
IN
9
12
T2
IN
11 INVALID
10
R2
OUT
FN4899 Rev.6.00
Feb 27, 2006
Page 2 of 20
ICL3224E, ICL3226E, ICL3244E
Pinouts (Continued)
ICL3244E (SOIC, SSOP)
TOP VIEW
C2+
C2-
V-
1
2
28 C1+
27 V+
26
3
V
CC
25 GND
R1
R2
R3
R4
R5
4
IN
IN
IN
IN
IN
5
24 C1-
6
23 FORCEON
22 FORCEOFF
21 INVALID
7
8
T1
9
20
R2
OUT
OUT
OUT
OUTB
OUT
OUT
OUT
OUT
OUT
10
11
12
13
14
19 R1
18 R2
17 R3
16 R4
15 R5
T2
T3
T3
T2
T1
IN
IN
IN
Pin Descriptions
PIN
FUNCTION
V
System power supply input (3.0V to 5.5V).
CC
V+
Internally generated positive transmitter supply (+5.5V).
Internally generated negative transmitter supply (-5.5V).
Ground connection.
V-
GND
C1+
C1-
External capacitor (voltage doubler) is connected to this lead.
External capacitor (voltage doubler) is connected to this lead.
External capacitor (voltage inverter) is connected to this lead.
External capacitor (voltage inverter) is connected to this lead.
TTL/CMOS compatible transmitter Inputs.
C2+
C2-
T
IN
T
15kV ESD Protected, RS-232 level (nominally 5.5V) transmitter outputs.
15kV ESD Protected, RS-232 compatible receiver inputs.
OUT
R
IN
R
TTL/CMOS level receiver outputs.
OUT
R
TTL/CMOS level, noninverting, always enabled receiver outputs.
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
Active high output that indicates when the ICL32XXE is ready to transmit (i.e., V- -4V)
OUTB
INVALID
READY
FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2).
FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high).
FN4899 Rev.6.00
Feb 27, 2006
Page 3 of 20
ICL3224E, ICL3226E, ICL3244E
Typical Operating Circuits
ICL3224E
19
+3.3V
+
0.1F
2
C
0.1F
C1+
3
1
V
CC
C
0.1F
+
3
+
V+
V-
4
C1-
5
C
0.1F
2
C2+
+
7
C
4
6
C2-
0.1F
+
T
T
1
2
13
17
8
T1
T2
T1
IN
OUT
OUT
12
15
T2
IN
TTL/CMOS
RS-232
16
LOGIC LEVELS
LEVELS
R1
R2
R1
R2
OUT
IN
IN
5k
5k
R
1
10
9
OUT
R
2
1
20
11
READY
V
FORCEOFF
INVALID
CC
14
TO POWER
CONTROL LOGIC
FORCEON
GND
18
ICL3226E
15
+3.3V
+
0.1F
2
+
C
1
0.1F
3
7
C1+
V
C
0.1F
CC
3
+
V+
V-
4
C1-
5
C
2
C2+
+
0.1F
C
4
0.1F
6
C2-
+
T
1
11
9
13
8
TTL/CMOS
LOGIC LEVELS
T1
OUT
T1
RS-232
LEVELS
IN
R1
R1
OUT
IN
1
5k
R
1
READY
16
10
V
CC
FORCEOFF
INVALID
12
TO POWER
CONTROL LOGIC
FORCEON
GND
14
FN4899 Rev.6.00
Feb 27, 2006
Page 4 of 20
ICL3224E, ICL3226E, ICL3244E
Typical Operating Circuits (Continued)
ICL3244E
+3.3V
+
0.1F
26
28
27
C
1
0.1F
C1+
V
C
0.1F
CC
+
+
3
+
V+
V-
24
C1-
1
C
2
C2+
3
9
0.1F
C
4
2
C2-
0.1F
+
T
T
T
1
2
3
14
T1
T1
IN
OUT
13
12
10
11
RS-232
LEVELS
T2
T3
T2
T3
IN
IN
OUT
OUT
20
19
R2
OUTB
TTL/CMOS
LOGIC LEVELS
4
5
R1
R1
R2
OUT
IN
R
1
2
5k
5k
5k
18
R2
OUT
IN
R
17
16
6
7
RS-232
LEVELS
R3
R4
R3
R4
OUT
IN
R
R
3
4
OUT
IN
5k
5k
15
23
8
R5
R5
OUT
IN
R
5
FORCEON
22
21
V
CC
FORCEOFF
GND
TO POWER
CONTROL LOGIC
INVALID
25
FN4899 Rev.6.00
Feb 27, 2006
Page 5 of 20
ICL3224E, ICL3226E, ICL3244E
m
Absolute Maximum Ratings
Thermal Information
V
to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Thermal Resistance (Typical, Note 1)
JA (°C/W)
CC
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
28 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
75
140
125
100
T
, FORCEOFF, FORCEON. . . . . . . . . . . . . . . . . . . -0.3V to 6V
IN
R
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
IN
Output Voltages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2V
T
OUT
R
, INVALID, READY . . . . . . . . . . . . . . . . -0.3V to V +0.3V
OUT CC
Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
T
OUT
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Operating Conditions
Temperature Range
ICL32XXEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ICL32XXEI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1F; Unless Otherwise Specified.
CC
1
4
Typicals are at T = 25°C
A
TEMP
(°C)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Supply Current, Automatic
Powerdown
All R Open, FORCEON = GND, FORCEOFF = V
IN
25
-
1.0
10
A
CC
Supply Current, Powerdown
FORCEOFF = GND
25
25
-
-
1.0
0.3
10
A
Supply Current,
All Outputs Unloaded, FORCEON = FORCEOFF = V
1.0
mA
CC
Automatic Powerdown Disabled
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low
Input Logic Threshold High
T
T
, FORCEON, FORCEOFF
Full
Full
Full
25
-
-
0.8
V
V
IN
IN
, FORCEON, FORCEOFF
V
V
= 3.3V
= 5.0V
2.0
-
-
-
-
CC
CC
2.4
V
Transmitter Input Hysteresis
Input Leakage Current
Output Leakage Current
Output Voltage Low
-
-
-
-
0.5
0.01
0.05
-
-
V
T
, FORCEON, FORCEOFF
Full
Full
Full
Full
1.0
10
0.4
-
A
A
V
IN
FORCEOFF = GND, ICL3244E Only
I
= 1.6mA
= -1.0mA
OUT
OUT
Output Voltage High
RECEIVER INPUTS
Input Voltage Range
Input Threshold Low
I
V
-0.6 V
-0.1
CC
V
CC
Full
25
-25
0.6
0.8
-
25
-
V
V
V
V
V
= 3.3V
= 5.0V
1.2
1.5
CC
CC
25
-
FN4899 Rev.6.00
Feb 27, 2006
Page 6 of 20
ICL3224E, ICL3226E, ICL3244E
Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1F; Unless Otherwise Specified.
CC
1
4
Typicals are at T = 25°C (Continued)
A
TEMP
(°C)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.5
1.8
0.5
5
MAX
2.4
2.4
-
UNITS
Input Threshold High
V
V
= 3.3V
= 5.0V
25
25
25
25
-
-
V
V
CC
CC
Input Hysteresis
-
V
Input Resistance
3
7
k
TRANSMITTER OUTPUTS
Output Voltage Swing
Output Resistance
All Transmitter Outputs Loaded with 3k to Ground
Full
Full
Full
Full
5.0
5.4
10M
35
-
-
V
V
= V+ = V- = 0V, Transmitter Output = 2V
300
-
CC
Output Short-Circuit Current
Output Leakage Current
-
-
60
25
mA
A
V
= 12V, V
= 0V or 3V to 5.5V
CC
OUT
Automatic Powerdown or FORCEOFF = GND
MOUSE DRIVEABILITY (ICL3244E Only)
Transmitter Output Voltage
(See Figure 11)
T1 = T2 = GND, T3 = V , T3
Loaded with 3k
Full
5
-
-
V
IN
IN
OUT
IN
CC
OUT
to GND, T1
and T2
Loaded with 2.5mA Each
OUT
ENHANCED AUTOMATIC POWERDOWN (FORCEON = GND, FORCEOFF = V
)
CC
Receiver Input Thresholds to
INVALID High
See Figure 6
Full
Full
Full
Full
25
-2.7
-0.3
-
-
-
2.7
0.3
0.4
-
V
V
Receiver Input Thresholds to
INVALID Low
See Figure 6
INVALID, READY Output Voltage
Low
I
I
= 1.6mA
= -1.0mA
-
V
OUT
OUT
INVALID, READY Output Voltage
High
V
-0.6
-
V
CC
Receiver Positive or Negative
-
1
-
s
Threshold to INVALID High Delay
(t
INVH)
Receiver Positive or Negative
Threshold to INVALID Low Delay
25
-
-
30
-
s
(t
INVL)
Receiver or Transmitter Edge to
Transmitters Enabled Delay (t
Note 2
Note 2
25
100
30
-
s
)
WU
Receiver or Transmitter Edge to
Transmitters Disabled Delay
Full
15
60
sec
(t
)
AUTOPWDN
TIMING CHARACTERISTICS
Maximum Data Rate
R
= 3kC = 1000pF, One Transmitter Switching
Full
25
25
25
25
25
250
500
0.15
0.15
200
200
100
-
-
-
-
-
-
kbps
s
L
L
Receiver Propagation Delay
Receiver Input to Receiver
Output, C = 150pF
t
t
-
-
-
-
-
PHL
PLH
L
s
Receiver Output Enable Time
Receiver Output Disable Time
Transmitter Skew
Normal Operation (ICL3244E Only)
Normal Operation (ICL3244E Only)
ns
ns
t
- t
PHL PLH
ns
FN4899 Rev.6.00
Feb 27, 2006
Page 7 of 20
ICL3224E, ICL3226E, ICL3244E
Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1F; Unless Otherwise Specified.
CC
1
4
Typicals are at T = 25°C (Continued)
A
TEMP
(°C)
PARAMETER
Receiver Skew
TEST CONDITIONS
MIN
TYP
50
-
MAX
-
UNITS
ns
t
- t
PHL PLH
25
25
25
-
Transition Region Slew Rate
V
R
= 3.3V,
C = 150pF to 1000pF
6
4
30
30
V/s
V/s
CC
L
= 3kto 7k
L
C = 150pF to 2500pF
8
Measured From 3V to -3V or -3V
L
to 3V
ESD PERFORMANCE
RS-232 Pins (T
, R
)
Human Body Model
25
25
25
25
-
-
-
-
15
8
-
-
-
-
kV
kV
kV
kV
OUT IN
IEC61000-4-2 Contact Discharge
IEC61000-4-2 Air Gap Discharge
Human Body Model
15
3
All Other Pins
NOTE:
2. An “edge” is defined as a transition through the transmitter or receiver input thresholds.
operating at full speed. Under more typical conditions of
3.3V, R = 3k, and C = 250pF, one transmitter easily
operates at 1Mbps.
Detailed Description
V
CC
L
L
These ICL32XXE interface ICs operate from a single +3V to
+5.5V supply, guarantee a 250kbps minimum data rate, require
only four small external 0.1F capacitors, feature low power
consumption, and meet all ElA RS-232C and V.28
specifications. The circuit is divided into three sections: The
charge pump, the transmitters, and the receivers.
Transmitter inputs float if left unconnected, and may cause I
increases. Connect unused inputs to GND for the best
performance.
CC
Receivers
Charge-Pump
All the ICL32XXE devices contain standard inverting receivers,
but only the ICL3244E receivers can three-state, via the
FORCEOFF control line. Additionally, the ICL3244E includes a
Intersil’s new ICL32XXE family utilizes regulated on-chip dual
charge pumps as voltage doublers, and voltage inverters to
generate 5.5V transmitter supplies from a V
supply as low
noninverting (monitor) receiver (denoted by the R
label)
CC
OUTB
as 3.0V. This allows these devices to maintain RS-232
compliant output levels over the 10% tolerance range of 3.3V
powered systems. The efficient on-chip power supplies require
only four small, external 0.1F capacitors for the voltage
that is always active, regardless of the state of any control
lines. Both receiver types convert RS-232 signals to CMOS
output levels and accept inputs up to 25V while presenting
the required 3k to 7k input impedance (see Figure 1) even if
doubler and inverter functions at V
= 3.3V. See the
the power is off (V
= 0V). The receivers’ Schmitt trigger
CC
CC
“Capacitor Selection” section, and Table 3 for capacitor
recommendations for other operating conditions. The charge
pumps operate discontinuously (i.e., they turn off as soon as
the V+ and V- supplies are pumped up to the nominal values),
resulting in significant power savings.
input stage uses hysteresis to increase noise immunity and
decrease errors due to slow input signal transitions.
V
CC
R
R
XIN
XOUT
GND V
V
-25V V
+25V
5k
ROUT
CC
RIN
Transmitters
GND
The transmitters are proprietary, low dropout, inverting drivers
that translate TTL/CMOS inputs to EIA/TIA-232 output levels.
Coupled with the on-chip 5.5V supplies, these transmitters
deliver true RS-232 levels over a wide range of single supply
system voltages.
FIGURE 1. INVERTING RECEIVER CONNECTIONS
Transmitter outputs disable and assume a high impedance
state when the device enters the powerdown mode (see Table
2). These outputs may be driven to 12V when disabled.
All devices guarantee a 250kbps data rate for full load
conditions (3k and 1000pF), V
3.0V, with one transmitter
CC
FN4899 Rev.6.00
Feb 27, 2006
Page 8 of 20
ICL3224E, ICL3226E, ICL3244E
The ICL3244E inverting receivers disable during forced
(manual) powerdown, but not during automatic powerdown
(see Table 2). Conversely, the monitor receiver remains active
even during manual powerdown making it extremely useful for
Ring Indicator monitoring. Standard receivers driving powered
down peripherals must be disabled to prevent current flow
through the peripheral’s protection diodes (see Figures 2 and
3). This renders them useless for wake up functions, but the
corresponding monitor receiver can be dedicated to this task
as shown in Figure 3.
TABLE 2. POWERDOWN LOGIC TRUTH TABLE
RS-232
RCVR OR
LEVEL
XMTR
EDGE
PRESENT
AT
(NOTE 3)
WITHIN 30 FORCEOFF FORCEON TRANSMITTER RECEIVER
R
RECEIVER INVALID
OUTB
SEC?
INPUT
INPUT
OUTPUTS
OUTPUTS OUTPUTS
INPUT?
OUTPUT
MODE OF OPERATION
ICL3224E, ICL3226E
NO
NO
YES
YES
NO
NO
X
H
H
H
H
H
H
L
H
H
L
Active
Active
Active
Active
High-Z
High-Z
High-Z
High-Z
Active
Active
Active
Active
Active
Active
Active
Active
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
N.A.
NO
YES
NO
L
H
L
Normal Operation (Enhanced
Auto Powerdown Disabled)
Normal Operation (Enhanced
Auto Powerdown Enabled)
L
YES
NO
H
L
L
Powerdown Due to Enhanced
Auto Powerdown Logic
L
YES
NO
H
L
X
X
Manual Powerdown
X
L
YES
H
ICL322XE - INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
X
X
NOTE 4
NOTE 4
NOTE 4
NOTE 4
Active
Active
Active
N.A.
N.A.
YES
NO
H
L
Normal Operation
High-Z
Forced Auto Powerdown
ICL3244E
NO
H
H
H
H
H
H
L
H
H
L
Active
Active
Active
Active
High-Z
High-Z
High-Z
High-Z
Active
Active
Active
Active
Active
Active
High-Z
High-Z
Active
Active
Active
Active
Active
Active
Active
Active
NO
YES
NO
L
H
L
Normal Operation (Enhanced
Auto Powerdown Disabled)
NO
YES
YES
NO
Normal Operation (Enhanced
Auto Powerdown Enabled)
L
YES
NO
H
L
L
Powerdown Due to Enhanced
Auto Powerdown Logic
NO
L
YES
NO
H
L
X
X
X
Manual Powerdown
X
L
YES
H
ICL3244E - INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
X
X
NOTE 4
NOTE 4
NOTE 4
NOTE 4
Active
Active
Active
Active
YES
NO
H
L
Normal Operation
High-Z
High-Z
Forced Auto Powerdown
NOTES:
3. Applies only to the ICL3244E.
4. Input is connected to INVALID Output.
FN4899 Rev.6.00
Feb 27, 2006
Page 9 of 20
ICL3224E, ICL3226E, ICL3244E
powerdown modes, under logic or software control, only the
FORCEOFF input need be driven. The FORCEON state isn’t
critical, as FORCEOFF dominates over FORCEON.
Nevertheless, if strictly manual control over powerdown is
desired, the user must strap FORCEON high to disable the
enhanced automatic powerdown circuitry. ICL3244E inverting
(standard) receiver outputs also disable when the device is in
powerdown, thereby eliminating the possible current path
through a shutdown peripheral’s input protection diode (see
Figures 2 and 3).
V
CC
V
CC
CURRENT
FLOW
V
CC
V
= V
CC
OUT
Rx
POWERED
DOWN
UART
Tx
OLD
RS-232 CHIP
Connecting FORCEOFF and FORCEON together disables the
enhanced automatic powerdown feature, enabling them to
function as a manual SHUTDOWN input (see Figure 4).
SHDN = GND
GND
FORCEOFF
PWR
FIGURE 2. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
FORCEON
MGT
LOGIC
V
INVALID
CC
ICL32XXE
TRANSITION
DETECTOR
TO
WAKE-UP
LOGIC
ICL3244E
I/O
UART
V
R2
CC
OUTB
CPU
R
V
= HI-Z
X
OUT
R2
OUT
R2
IN
POWERED
DOWN
UART
T
T1
X
IN
FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
T1
OUT
FORCEOFF = GND
With any of the above control schemes, the time required to
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
exit powerdown, and resume transmission is only 100s.
Powerdown Functionality
When using both manual and enhanced automatic powerdown
(FORCEON = 0), the ICL32XXE won’t power up from manual
powerdown until both FORCEOFF and FORCEON are driven
high, or until a transition occurs on a receiver or transmitter
input. Figure 5 illustrates a circuit for ensuring that the
ICL32XXE powers up as soon as FORCEOFF switches high.
The rising edge of the Master Powerdown signal forces the
device to power up, and the ICL32XXE returns to enhanced
automatic powerdown mode an RC time constant after this
rising edge. The time constant isn’t critical, because the
ICL32XXE remains powered up for 30 seconds after the
FORCEON falling edge, even if there are no signal transitions.
This gives slow-to-wake systems (e.g., a mouse) plenty of time
to start transmitting, and as long as it starts transmitting within
30 seconds both systems remain enabled.
This 3V family of RS-232 interface devices requires a nominal
supply current of 0.3mA during normal operation (not in
powerdown mode). This is considerably less than the 5mA to
11mA current required of 5V RS-232 devices. The already low
current requirement drops significantly when the device enters
powerdown mode. In powerdown, supply current drops to 1A,
because the on-chip charge pump turns off (V+ collapses to
V
, V- collapses to GND), and the transmitter outputs three-
CC
state. Inverting receiver outputs may or may not disable in
powerdown; refer to Table 2 for details. This micro-power mode
makes these devices ideal for battery powered and portable
applications.
Software Controlled (Manual) Powerdown
These devices allow the user to force the IC into the low power,
standby state, and utilize a two pin approach where the
FORCEON and FORCEOFF inputs determine the IC’s mode.
For always enabled operation, FORCEON and FORCEOFF
are both strapped high. To switch between active and
FN4899 Rev.6.00
Feb 27, 2006
Page 10 of 20
ICL3224E, ICL3226E, ICL3244E
powerdown feature provides additional system power savings
without changes to the existing operating system.
MASTER POWERDOWN LINE
0.1F
POWER
MANAGEMENT
UNIT
Enhanced automatic powerdown operates when the
FORCEON input is low, and the FORCEOFF input is high.
Tying FORCEON high disables automatic powerdown, but
manual powerdown is always available via the overriding
FORCEOFF input. Table 2 summarizes the enhanced
automatic powerdown functionality.
1M
FORCEOFF
FORCEON
ICL32XXE
Figure 7 illustrates the enhanced powerdown control logic.
Note that once the ICL32XXE enters powerdown (manually or
automatically), the 30 second timer remains timed out (set),
keeping the ICL32XXE powered down until FORCEON
transitions high, or until a transition occurs on a receiver or
transmitter input.
FIGURE 5. CIRCUIT TO ENSURE IMMEDIATE POWER UP
WHEN EXITING FORCED POWERDOWN
INVALID Output
The INVALID output always indicates (see Table 2) whether or
not 30s have elapsed with invalid RS-232 signals (see
Figures 6 and 8) persisting on all of the receiver inputs, giving
the user an easy way to determine when the interface block
should power down. Invalid receiver levels occur whenever the
driving peripheral’s outputs are shut off (powered down) or
when the RS-232 interface cable is disconnected. In the case
of a disconnected interface cable where all the receiver inputs
are floating (but pulled to GND by the internal receiver pull
down resistors), the INVALID logic detects the invalid levels
and drives the output low. The power management logic then
uses this indicator to power down the interface block.
Reconnecting the cable restores valid levels at the receiver
inputs, INVALID switches high, and the power management
logic wakes up the interface block. INVALID can also be used
to indicate the DTR or RING INDICATOR signal, as long as the
other receiver inputs are floating, or driven to GND (as in the
case of a powered down driver).
FORCEOFF
EDGE
T_IN
DETECT
S
30s
AUTOSHDN
TIMER
R
EDGE
DETECT
R_IN
FORCEON
FIGURE 7. ENHANCED AUTOMATIC POWERDOWN LOGIC
The INVALID output signal switches low to indicate that invalid
levels have persisted on all of the receiver inputs for more than
30s (see Figure 8), but this has no direct effect on the state of
the ICL32XXE (see the next sections for methods of utilizing
INVALID to power down the device). INVALID switches high
1s after detecting a valid RS-232 level on a receiver input.
INVALID operates in all modes (forced or automatic
VALID RS-232 LEVEL - INVALID = 1
2.7V
INDETERMINATE
powerdown, or forced on), so it is also useful for systems
employing manual powerdown circuitry.
0.3V
INVALID LEVEL - INVALID = 0
-0.3V
The time to recover from automatic powerdown mode is
typically 100s.
INDETERMINATE
Emulating Standard Automatic Powerdown
-2.7V
If enhanced automatic powerdown isn’t desired, the user can
implement the standard automatic powerdown feature (mimics
the function on the ICL3221E/23E/43E) by connecting the
INVALID output to the FORCEON and FORCEOFF inputs, as
shown in Figure 9. After 30s of invalid receiver levels,
INVALID switches low and drives the ICL32XXE into a forced
powerdown condition. INVALID switches high as soon as a
receiver input senses a valid
RS-232 level, forcing the ICL32XXE to power on. See the
“INVALID DRIVING FORCEON AND FORCEOFF” section of
Table 2 for an operational summary. This operational mode is
perfect for handheld devices that communicate with another
computer via a detachable cable. Detaching the cable allows
the internal receiver pull-down resistors to pull the inputs to
VALID RS-232 LEVEL - INVALID = 1
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
Enhanced Automatic Powerdown
Even greater power savings is available by using these
devices which feature an enhanced automatic powerdown
function. When the enhanced powerdown logic determines
that no transitions have occurred on any of the transmitter nor
receiver inputs for 30 seconds, the charge pump and
transmitters powerdown, thereby reducing supply current to
1A. The ICL32XXE automatically powers back up whenever it
detects a transition on one of these inputs. This automatic
FN4899 Rev.6.00
Feb 27, 2006
Page 11 of 20
ICL3224E, ICL3226E, ICL3244E
RECEIVER
INPUTS
INVALID
REGION
}
TRANSMITTER
INPUTS
TRANSMITTER
OUTPUTS
t
INVH
INVALID
OUTPUT
t
INVL
t
AUTOPWDN
t
WU
t
WU
t
AUTOPWDN
READY
OUTPUT
V+
V
CC
0
V-
FIGURE 8. ENHANCED AUTOMATIC POWERDOWN, INVALID AND READY TIMING DIAGRAMS
GND (an invalid RS-232 level), causing the 30s timer to time-
out and drive the IC into powerdown. Reconnecting the cable
restores valid levels, causing the IC to power back up.
Hybrid Automatic Powerdown Options
ICL32XXE
For devices which communicate only through a detachable
cable, connecting INVALID to FORCEOFF (with
FORCEON = 0) may be a desirable configuration. While the
cable is attached INVALID and FORCEOFF remain high, so
the enhanced automatic powerdown logic powers down the
RS-232 device whenever there is 30 seconds of inactivity on
the receiver and transmitter inputs. Detaching the cable allows
the receiver inputs to drop to an invalid level (GND), so
INVALID switches low and forces the RS-232 device to power
down. The ICL32XXE remains powered down until the cable is
reconnected (INVALID = FORCEOFF = 1) and a transition
occurs on a receiver or transmitter input (see Figure 7). For
immediate power up when the cable is reattached, connect
FORCEON to FORCEOFF through a network similar to that
shown in Figure 5.
I/O
UART
CPU
FIGURE 9. CONNECTIONS FOR AUTOMATIC POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
Ready Output (ICL3224E and ICL3226E only)
The Ready output indicates that the ICL322XE is ready to
transmit. Ready switches low whenever the device enters
powerdown, and switches back high during power-up when V-
reaches -4V or lower.
Capacitor Selection
The charge pumps require 0.1F capacitors for 3.3V operation.
For other supply voltages refer to Table 3 for capacitor values.
Do not use values smaller than those listed in Table 3.
Increasing the capacitor values (by a factor of 2) reduces ripple
on the transmitter outputs and slightly reduces power
consumption. C , C , and C can be increased without
2
3
4
increasing C ’s value, however, do not increase C without
1
1
also increasing C , C , and C to maintain the proper ratios
2
3
4
(C to the other capacitors).
1
FN4899 Rev.6.00
Feb 27, 2006
Page 12 of 20
ICL3224E, ICL3226E, ICL3244E
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the amount
of ripple on V+ and V-.
Mouse Driveability
The ICL3244E is specifically designed to power a serial mouse
while operating from low voltage supplies. Figure 11 shows the
transmitter output voltages under increasing load current. The
on-chip switching regulator ensures the transmitters will supply
at least 5V during worst case conditions (15mA for paralleled
V+ transmitters, 7.3mA for single V- transmitter).
TABLE 3. REQUIRED CAPACITOR VALUES
6
5
V
(V)
C
(F)
C , C , C
CC
1
2
3
4
(F)
V
+
OUT
4
3
3.0 to 3.6
4.5 to 5.5
3.0 to 5.5
0.1
0.1
V
= 3.0V
CC
0.047
0.1
0.33
0.47
2
1
T1
0
V
+
OUT
-1
-2
-3
-4
-5
-6
Power Supply Decoupling
In most circumstances a 0.1F bypass capacitor is adequate.
T2
T3
ICL3244E
In applications that are particularly sensitive to power supply
V
V
-
CC
OUT
V
-
OUT
8
noise, decouple V
to ground with a capacitor of the same
CC
value as the charge-pump capacitor C . Connect the bypass
capacitor as close as possible to the IC.
1
0
1
2
3
4
5
6
7
9
10
LOAD CURRENT PER TRANSMITTER (mA)
Operation Down to 2.7V
ICL32XXE transmitter outputs meet RS-562 levels (3.7V), at
FIGURE 11. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CURRENT (PER TRANSMITTER, i.e., DOUBLE
CURRENT AXIS FOR TOTAL V CURRENT)
OUT+
full data rate, with V
as low as 2.7V. RS-562 levels typically
CC
ensure inter operability with RS-232 devices.
High Data Rates
The ICL32XXE maintain the RS-232 5V minimum transmitter
output voltages even at high data rates. Figure 12 details a
transmitter loopback test circuit, and Figure 13 illustrates the
loopback test result at 120kbps. For this test, all transmitters
were simultaneously driving RS-232 loads in parallel with
1000pF, at 120kbps. Figure 14 shows the loopback results for
a single transmitter driving 1000pF and an RS-232 load at
250kbps. The static transmitters were also loaded with an RS-
232 receiver.
Transmitter Outputs when Exiting
Powerdown
Figure 10 shows the response of two transmitter outputs when
exiting powerdown mode. As they activate, the two transmitter
outputs properly go to opposite RS-232 levels, with no
glitching, ringing, nor undesirable transients. Each transmitter
is loaded with 3kin parallel with 2500pF. Note that the
transmitters enable only when the magnitude of the supplies
exceed approximately 3V.
V
CC
+
0.1F
5V/DIV.
FORCEOFF
T1
V
CC
V+
V-
+
C1+
C1-
C2+
C2-
+
C
1
2
C
3
4
V
= +3.3V
C1 - C4 = 0.1F
CC
ICL32XXE
+
C
+
2V/DIV.
C
T
T
OUT
IN
T2
1000pF
R
IN
R
OUT
5V/DIV.
READY
TIME (20s/DIV.)
FORCEON
5K
V
FORCEOFF
CC
FIGURE 10. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
FIGURE 12. TRANSMITTER LOOPBACK TEST CIRCUIT
FN4899 Rev.6.00
Feb 27, 2006
Page 13 of 20
ICL3224E, ICL3226E, ICL3244E
15kV ESD Protection
5V/DIV.
All pins on ICL32XX devices include ESD protection
structures, but the ICL32XXE family incorporates advanced
structures which allow the RS-232 pins (transmitter outputs
and receiver inputs) to survive ESD events up to 15kV. The
RS-232 pins are particularly vulnerable to ESD damage
because they typically connect to an exposed port on the
exterior of the finished product. Simply touching the port pins,
or connecting a cable, can cause an ESD event that might
destroy unprotected ICs. These new ESD structures protect
the device whether or not it is powered up, protect without
allowing any latchup mechanism to activate, and don’t interfere
with RS-232 signals as large as 25V.
T1
IN
T1
OUT
OUT
R1
V
= +3.3V
CC
C1 - C4 = 0.1F
5s/DIV.
Human Body Model (HBM) Testing
FIGURE 13. LOOPBACK TEST AT 120kbps
As the name implies, this test method emulates the ESD event
delivered to an IC during human handling. The tester delivers
the charge through a 1.5k current limiting resistor, making the
test less severe than the IEC61000 test which utilizes a 330
limiting resistor. The HBM method determines an ICs ability to
withstand the ESD transients typically present during handling
and manufacturing. Due to the random nature of these events,
each pin is tested with respect to all other pins. The RS-232
pins on “E” family devices can withstand HBM ESD events to
15kV.
5V/DIV.
T1
IN
T1
OUT
IEC61000-4-2 Testing
The IEC 61000 test method applies to finished equipment, rather
than to an individual IC. Therefore, the pins most likely to suffer an
ESD event are those that are exposed to the outside world (the
RS-232 pins in this case), and the IC is tested in its typical
application configuration (power applied) rather than testing each
pin-to-pin combination. The lower current limiting resistor coupled
with the larger charge storage capacitor yields a test that is much
more severe than the HBM test. The extra ESD protection built
into this device’s RS-232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board level
protection on the RS-232 port.
R1
OUT
V
= +3.3V
CC
C1 - C4 = 0.1F
2s/DIV.
FIGURE 14. LOOPBACK TEST AT 250kbps
Interconnection with 3V and 5V Logic
The ICL32XXE directly interfaces with 5V CMOS and TTL logic
families. Nevertheless, with the ICL32XX at 3.3V, and the logic
supply at 5V, AC, HC, and CD4000 outputs can drive ICL32XX
AIR-GAP DISCHARGE TEST METHOD
inputs, but ICL32XX outputs do not reach the minimum V for
IH
these logic families. See Table 4 for more information.
For this test method, a charged probe tip moves toward the IC pin
until the voltage arcs to it. The current waveform delivered to the
IC pin depends on approach speed, humidity, temperature, etc.,
so it is difficult to obtain repeatable results. The “E” device RS-232
pins withstand 15kV air-gap discharges.
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM
V
CC
POWER-SUPPLY SUPPLY
VOLTAGE
(V)
VOLTAGE
(V)
CONTACT DISCHARGE TEST METHOD
COMPATIBILITY
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby eliminating
the variables associated with the air-gap discharge. The result
is a more repeatable and predictable test, but equipment limits
prevent testing devices at voltages higher than 8kV. All “E”
family devices survive 8kV contact discharges on the RS-232
pins.
3.3
3.3
Compatible with all CMOS
families.
5
5
Compatible with all TTL and
CMOS logic families.
5
3.3
Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX
outputs are incompatible with AC,
HC, and CD4000 CMOS inputs.
FN4899 Rev.6.00
Feb 27, 2006
Page 14 of 20
ICL3224E, ICL3226E, ICL3244E
Typical Performance Curves V = 3.3V, T = 25°C
CC
A
6
25
20
V
+
OUT
4
2
-SLEW
1 TRANSMITTER AT 250kbps
OTHER TRANSMITTERS AT 30kbps
0
15
10
5
+SLEW
-2
-4
V
-
OUT
-6
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FIGURE 15. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
FIGURE 16. SLEW RATE vs LOAD CAPACITANCE
35
40
ICL3226E
ICL3224E
35
30
250kbps
250kbps
25
20
30
25
120kbps
120kbps
15
10
20
15
20kbps
4000
20kbps
5
0
10
5
0
1000
2000
3000
5000
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FIGURE 18. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
3.5
45
NO LOAD
ALL OUTPUTS STATIC
ICL3244E
40
3.0
250kbps
35
2.5
2.0
1.5
1.0
0.5
0
30
120kbps
25
20
20kbps
15
10
4000
5000
2000
3000
1000
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
LOAD CAPACITANCE (pF)
SUPPLY VOLTAGE (V)
FIGURE 20. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 19. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FN4899 Rev.6.00
Feb 27, 2006
Page 15 of 20
ICL3224E, ICL3226E, ICL3244E
TRANSISTOR COUNT
Die Characteristics
ICL3224E: 937
ICL3226E: 825
ICL3244E: 1109
SUBSTRATE POTENTIAL (POWERED UP)
GND
PROCESS
Si Gate CMOS
FN4899 Rev.6.00
Feb 27, 2006
Page 16 of 20
ICL3224E, ICL3226E, ICL3244E
Shrink Small Outline Plastic Packages (SSOP)
M20.209 (JEDEC MO-150-AE ISSUE B)
N
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
M
M
B
0.25(0.010)
H
AREA
INCHES
MIN
MILLIMETERS
E
GAUGE
PLANE
SYMBOL
MAX
0.078
0.008’
0.070’
0.015
0.008
0.289
0.212
MIN
1.73
0.05
1.68
0.25
0.09
7.07
5.20’
MAX
1.99
0.21
1.78
0.38
0.20’
7.33
5.38
NOTES
-B-
A
A1
A2
B
0.068
0.002
0.066
0.010’
0.004
0.278
0.205
1
2
3
L
0.25
0.010
SEATING PLANE
A
9
-A-
C
D
E
D
3
4
-C-
e
0.026 BSC
0.65 BSC
A2
e
A1
C
H
L
0.301
0.025
0.311
0.037
7.65
0.63
7.90’
0.95
B
0.10(0.004)
6
7
M
M
S
B
0.25(0.010)
C
A
N
20
20
0 deg.
8 deg.
0 deg.
8 deg.
NOTES:
Rev. 3 11/02
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
FN4899 Rev.6.00
Feb 27, 2006
Page 17 of 20
ICL3224E, ICL3226E, ICL3244E
Small Outline Plastic Packages (SSOP)
M16.209 (JEDEC MO-150-AC ISSUE B)
N
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
GAUGE
PLANE
SYMBOL
MIN
MAX
0.078
-
MIN
-
MAX
2.00
-
NOTES
-B-
A
A1
A2
B
-
-
0.002
0.065
0.009
0.004
0.233
0.197
0.05
1.65
0.22
0.09
5.90
5.00
-
1
2
3
0.072
0.014
0.009
0.255
0.220
1.85
0.38
0.25
6.50
5.60
-
L
0.25
0.010
SEATING PLANE
A
9
-A-
C
D
E
-
D
3
-C-
4
e
0.026 BSC
0.65 BSC
-
A2
e
A1
C
H
L
0.292
0.022
0.322
0.037
7.40
0.55
8.20
0.95
-
B
0.10(0.004)
6
0.25(0.010) M
C
A M B S
N
16
16
7
0°
8°
0°
8°
-
NOTES:
Rev. 3 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimen-
sion at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4899 Rev.6.00
Feb 27, 2006
Page 18 of 20
ICL3224E, ICL3226E, ICL3244E
Shrink Small Outline Plastic Packages (SSOP)
M28.209 (JEDEC MO-150-AH ISSUE B)
N
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
GAUGE
PLANE
SYMBOL
MIN
MAX
0.078
-
MIN
-
MAX
2.00
-
NOTES
-B-
A
A1
A2
B
-
-
0.002
0.065
0.009
0.004
0.390
0.197
0.05
1.65
0.22
0.09
9.90
5.00
-
1
2
3
0.072
0.014
0.009
0.413
0.220
1.85
0.38
0.25
10.50
5.60
-
L
0.25
0.010
SEATING PLANE
A
9
-A-
C
D
E
-
D
3
-C-
4
e
0.026 BSC
0.65 BSC
-
A2
e
A1
C
H
L
0.292
0.022
0.322
0.037
7.40
0.55
8.20
0.95
-
B
0.10(0.004)
6
0.25(0.010) M
C
A M B S
N
28
28
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
Rev. 2 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN4899 Rev.6.00
Feb 27, 2006
Page 19 of 20
ICL3224E, ICL3226E, ICL3244E
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
-A-
0.7125 17.70
3
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
© Copyright Intersil Americas LLC 2001-2006. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4899 Rev.6.00
Feb 27, 2006
Page 20 of 20
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